JPH06177144A - Bipolar transistor and fabrication thereof - Google Patents

Abstract

PURPOSE:To prevent lowering of the breakdown voltage at C-B junction and increase of junction capacitance by providing a heavily doped semiconductor layer having the same conductivity type as the base on a region in the base where graft base is formed. CONSTITUTION:A buried layer 2 of N-type impurities is formed on a P-type semiconductor substrate 1 followed by formation of an N-type epitaxial layer 3. An isolation region 4 is then formed thereon, a collector contact part 5 is bored, and an N<+>-type heavily doped region 6 is formed immediately thereunder. Subsequently, a P-type base layer 7 is formed followed by formation of an oxide protective film 9 for forming graft base and formation of a graft base layer 10. Thereafter, oxide 11 is grown for example, a contact 12 is opened and polysilicon 13 is grown. This method can prevent breakdown voltage at C-B junction from lowering and the junction capacitance from increasing due to the graft base being provided in order to decrease base resistance of bipolar transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and its manufacturing method, and more particularly to the structure and manufacturing method of an IC.

[0002]

2. Description of the Related Art Recently, the speed of bipolar transistors has been increased.
Higher performance is being advanced rapidly. In order to improve the performance of a bipolar transistor, firstly, it has been attempted to reduce parasitic capacitance and base resistance by miniaturization and secondly shorten carrier transit time by making a junction shallow. Specifically, an improvement in f _T (cutoff frequency) and a decrease in rbb ′ (base resistance) are indicators of performance. Here, taking rbb 'as an example, rbb' can be expressed by the following equation. rbb ′ = (rb ₁ rb ₂ + rb ₃ / (number of emitters) where rb ₁ , rb ₂ and rb ₃ are 17 in FIG. 3,
Equivalent to a resistance of 18, 19. rb ₁ ; Intrinsic (directly below the emitter) base resistance rb ₂ ; External base resistance rb ₃ ; Contact part base resistance In case of double base rb ₁ = ρS ₁ · S ₁ / (12 · le) rb ₂ = ρS ₂ · S ₂ / (2 · le) rb is a _{3 = ρS3 · S 3 / (} 6 · le). Where ρS1; intrinsic base layer resistance ρS2; external base layer resistance ρS3; contact layer resistance S ₁ ; emitter width S ₂ ; emitter-base contact distance S ₃ ; base contact width le; emitter length reduce the base resistance from here As a method (1), the emitter width is reduced. (2) Shorten the distance between the base and emitter. (3) Lower the resistance of each base layer. Etc. Here, the miniaturization of the bipolar transistor for improving the performance contributes to (1) and (2). In order to reduce (3), the graft base 20
Are being adopted.

Further, in order to shorten the carrier traveling time,
Application based on thin epi-thickness by MBE etc. is performed. However, as the base becomes thinner, the layer resistance increases, which in turn causes an increase in the base resistance. Therefore, it is essential to reduce the base resistance by adopting a graft base. FIG. 3 shows a conventional example in which a graft base is applied to a thin base layer formed by MBE.

[0004]

Conventionally, the ion implantation method and the thermal diffusion method are used to form the graft base, so that the bond is generally deepened, resulting in a reduction in the effective epitaxial layer thickness under the graft base, resulting in C There are problems that the breakdown voltage between -B and the junction capacitance between C and B increase.

An object of the present invention is to provide a bipolar transistor and its manufacturing method which can prevent a decrease in the junction withstand voltage between C and B and an increase in the junction capacitance caused by a graft base provided to reduce the base resistance of the bipolar transistor. To provide.

[0006]

The bipolar transistor of the present invention is characterized by having a high-concentration semiconductor layer of the same conductivity type as that of the base on a region to be a graft base in the base. Further, the method for manufacturing a bipolar transistor of the present invention is configured to include a step of selectively forming a high-concentration semiconductor layer by using the MBE or CYD method on a region to be a graft base in the base of the bipolar transistor. .

[0007]

The present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor device shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, after a buried layer 2 of N-type impurities is formed on a P-type semiconductor substrate 1,
The N-type epitaxial layer 3 is grown. Next, after forming the element isolation region 4, the collector contact portion 5 is opened and phosphorus ions are extracted to form the N ⁺ -type high concentration region 6 immediately below the collector. After that, the P-type base layer 7 is made of boron having a thickness of 50 nm at 1 × 10 ¹⁸ atom / cm ³ , for example.

Next, as shown in FIG. 1B, a protective film 9 for forming a graft base is formed by using, for example, an oxide film, and the graft base layer 10 has a thickness of, for example, 100 nm and boron is 1 × 10 ²⁰ atom / cm. Form ³ . Here, for forming the base layer and the graft base, for example, MBE
(Molecular beam epitaxy method) or CVD (chemical vapor deposition) method is used.

Next, as shown in FIG. 1C, for example, an oxide film 11 (or a laminated film of an oxide film and a nitride film or the like may be grown) is grown on the entire surface, a contact 12 is opened, and polycrystalline silicon 13 is formed. Grow. Thereafter, as shown in FIG. 1D, As ⁺ I / I is performed to form the emitter 14 of the N ⁺ layer and further the respective electrodes 15 are formed. At this time, the polycrystalline silicon 13 doped with N-type impurities may be left on the emitter and collector.

Next, a second embodiment will be described with reference to FIG. In the first embodiment, the collector lead-out port is located at the upper part to form a transistor in an integrated circuit, but when the present invention is used for a discrete transistor, the collector part is arranged at 16 in FIG. Also in this case, the graft base manufacturing method is performed in the same manner as in the first embodiment.

[0012]

As described above, according to the present invention, by forming the graft base on the base of the bipolar transistor, unlike the conventional graft base, the junction capacitance of the device is not increased and the junction breakdown voltage is not reduced. In addition, it has become possible to reduce the base resistance. This means that the performance of the device is improved in terms of both high frequency characteristics and direct current characteristics. In particular, it can be calculated that the junction withstand voltage is simply improved by about 15% and the junction capacity is improved by about 20% from the conventional one with the graft base.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a bipolar transistor device shown in order of steps for explaining an embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device for explaining a structure and a manufacturing method of a conventional bipolar transistor.

[Explanation of symbols]

1 P-type semiconductor substrate 2 N ⁺ Buried layer 3 N ^- Epitaxial layer 4 Element isolation oxide film 5 Collector extraction part 6 High concentration region directly under collector 7 P-type base layer 8 Surface protective film 1 9 G / B formation protective film 10 G / B layer 11 Surface protection film 2 12 Emitter contact 13 Polycrystalline silicon growth film 14 High concentration emitter 15 Electrode 16 N-type semiconductor substrate 17 Intrinsic (directly under the emitter) base resistance 18 External base resistance 19 Contact part base resistance 20 Conventional G / B layer

Claims (2)

[Claims] 1. A base layer of one conductivity type formed on one main surface of a semiconductor substrate, and an impurity selectively formed on the base layer and having the same conductivity type as the base layer and having a higher concentration than the base layer. And a graft base layer having: 2. A step of forming a base layer of one conductivity type on one main surface of a semiconductor substrate, and a graft having the same conductivity type as the base layer and a higher concentration of impurities than the base layer on the base layer. And a step of selectively forming the base layer by using the MBE method or the CVD method.