JPH06169575A - Pwm pulse generator power conversion apparatus - Google Patents

Abstract

PURPOSE:To speed up processing and prevent the breakdown of a main circuit power element at abnormality by monitoring the processing time and the output data of an operating means, and the output pulse condition of a pulse generating means. CONSTITUTION:When a host CPU4 writes command information 10 into a storage means 1-1, an operating means 1-2 operates the pulse width equivalent to the conductivity time of the power element of a main circuit 6, and stores it in a storage means 1-3. A pulse generating means 1-4 outputs a PWM pulse original signal 14 corresponding to pulse width data. A monitoring means 1-5 monitors the operation signal 13 of the operating means 1-2, the data on pulse width stored in the storage means 1-3, and the PWM pulse original signals 14 outputted from the pulse generating means 1-4, and stores the monitor data in random storage means 1-6 and 1-7. Moreover, a monitor means 1-5 outputs a gate stop signal 15 for preventing output, in case that abnormality occurs in the PWM pulse original signal 14, and protects the power element of a main circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a PWM pulse generator for a power converter used in vehicles, elevators and the like.

[0002]

2. Description of the Related Art As a method for increasing the processing speed of a PWM pulse generator in a control device for an inverter or a converter, a method of dividing an arithmetic means and a pulse generating means and processing them in parallel is conceivable. It is described in the contributor article 890 "Instantaneous value control of PWM converter using DSP" in the first conference of the Japan Institute of Electrical Engineers. In this document, the calculation means is a DSP (Digital Signal Proc).
On the other hand, the speed is increased by configuring the pulse generating means discretely.

[0003]

According to the above known example,
Since the pulse generation means always outputs the PWM pulse according to the output of the DSP, if the DSP outputs incorrect data, the PWM pulse also becomes abnormal, and the power element of the main circuit may be damaged. Further, when the pulse generating means itself malfunctions, the power element may be damaged in the same manner. Also, in the inverter device used for vehicles and elevators,
In order to reduce noise, the frequency is increased, and for this purpose, it is essential to speed up the processing of the PWM pulse generator. An object of the present invention is to increase the processing speed of the PWM pulse generator and, at the same time, prevent damage to the power element of the main circuit when the PWM pulse generator is abnormal.

[0004]

In order to achieve the above object, monitoring means for monitoring the processing time of the computing means, the output data and the output pulse state of the pulse generating means are provided.

[0005]

The monitoring means judges that the arithmetic means is abnormal and outputs an error signal to the pulse generating means when the operation signal of the arithmetic means is not output in a predetermined cycle or when the output data of the arithmetic means is out of the allowable range. And acts to stop the output pulse in a predetermined procedure. Further, the monitoring means monitors the output pulse state of the pulse generation means, determines that the pulse generation means is abnormal when the pulse is in a mode other than the predetermined mode, and immediately stops the pulse.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.
A case where the present invention is applied to a three-level inverter device will be described. The three-level inverter device, as shown in FIG.
A master controller 2 that outputs a notch signal, an input / output interface unit 3 that converts the level of input / output signals, a host CPU 4 that manages the entire system, a PWM pulse generator 1 that outputs a PWM pulse for driving an inverter device. , A gate driver 5 for driving a power element of the main circuit, and a main circuit 6 including U, V, W three-phase inverters and DC power supplies Ep, Em. In this configuration, the upper CPU 4 has the input / output interface unit 3
A notch signal or the like output from the master controller 2 is fetched via the, and command information 10 such as an inverter frequency or an output voltage is output to the PWM pulse generator 1.
The PWM pulse generator 1 calculates an appropriate pulse width based on the command information 10, outputs the PWM pulse signal 11, and outputs the monitoring information 12 to the upper CPU 4. The upper CPU 4 uses the monitoring information 12 to perform PWM
The presence or absence of an abnormality in the pulse generator 1 is detected, and the main disconnector is cut off to protect the entire three-level inverter device.
Further, the gate driver 5 amplifies the PWM pulse signal and turns on or off the power element of the main circuit 6 by a signal S.
_{U1 to} S _U4 (U phase), S _{V1 to} S _V4 (V phase), S _{W1 to} S
_W4 (W phase) is output. Each phase of the three-phase inverter of the main circuit 6 has four power elements PDU1 to PDU as illustrated.
4 (U-phase) is connected in series, and AC power is supplied to the induction motor IM by making each intermediate point an output. Note that the four power elements of V phase and W phase are also U
Configure the same as the phase.

FIG. 1 shows a PWM pulse generator 1 of the present invention.
Shows the configuration of. This device is a storage means 1 for storing command information 10 from the upper CPU 4, that is, a frequency command and a voltage command.
-1, calculation means 1-2 for calculating the pulse width based on the command information 10, storage means 1-3 for storing the pulse width data obtained as a result of the calculation, and PWM pulse original signals for three phases based on the pulse width data Pulse generation means 1 for generating 14
-4, operation signal 1 indicating the processing time of the computing means 1-2
3 and monitoring means 1-5 for monitoring the pulse width data and the PWM pulse original signal 14 stored in the storage means 1-3,
Storage means 1-6 and 1-7 for storing this monitoring data,
The AND circuit 1-8 outputs the PWM pulse signal 11 by calculating the logical product of the PWM pulse original signal 14 and the gate stop signal 15 output by the monitoring means 1-5. In the above configuration, when the upper CPU 4 writes the command information 10 in the storage means 1-1, the calculation means 1-2 calculates the pulse width corresponding to the conduction time of the power element of the main circuit 6 based on the command, and the storage means. Store in 1-3. The pulse generation means 1-4 generates three phases of digital signals of "1" and "0" corresponding to the pulse width data, and the PWM pulse original signal 1
Output as 4. The monitoring means 1-5 is the calculation means 1-2.
Operation signal 13, the pulse width data stored in the storage unit 1-3, and the PW output from the pulse generation unit 1-4.
The M pulse original signal 14 is monitored, and the monitoring data is stored in the storage means 1-6 and 1-7 as needed. Also, monitoring means 1-5
Is an abnormality in the original PWM pulse signal 14,
The gate stop signal 15 for stopping the output is output to protect the power element of the main circuit 6.

A specific circuit configuration of the PWM pulse generator 1 is shown in FIG. This circuit includes a first microcomputer 1-2 for realizing the arithmetic means 1-2 of FIG. 1, a pulse generation means 1-4 and a monitoring means 1-5 (monitoring data 1 of FIG. 1).
Second microcomputer 1 for realizing (including -6)
-4 are provided independently, and a ROM (Read Onl) for storing the programs of the respective microcomputers is provided.
yMemory) 1-9 and 1-11, RAM for calculation
(Random Access Memory) 1-1
0 and 1-12, dual port RAMs 1-1 and 1-7 that interface with the upper CPU 4, and dual port R that interfaces with the first microcomputer 1-2 and the second microcomputer 1-4.
AM 1-3, AND circuit group (including NAND) 1-8 for obtaining logical product, and first microcomputer 1-2
And a clock generator 1-13 for generating a common clock signal for the second microcomputer 1-4, and a reset circuit 1-14 for generating a common reset signal. Note that reference numerals 13, 15 to 23 denote signal lines. The operation of this circuit will be described with reference to this figure and FIGS. 4 and 5. In this circuit, the second microcomputer 1-4 is mainly used to output the interrupt signal 22 of a constant cycle. This signal is commonly input to the first microcomputer 1-2 and the second microcomputer 1-4, and the relationship between the processing cycle T1 of the first microcomputer and the processing cycle T2 of the second microcomputer is T1 = Set to T2, first
And the second microcomputer is synchronized.
Further, the host CPU 4 writes the command information 10 in the dual port RAM 1-1 via the data bus 20 and the address bus 21 asynchronously with these two microcomputers, and reads the monitoring information 12 from the dual port RAM 1-7. Here, the monitoring information 12 is the upper CP
A central monitoring center (not shown) is notified and displayed via U4 (or via a master controller (driver's cab) or an input / output interface not shown). When the interrupt signal 22 is input, the first microcomputer 1-2 first sets the operation signal 13 to '1' in step 30, and then outputs the command information 10 in step 31, as shown in FIG. Read from dual port RAM 1-1. Next, in step 32, the pulse widths of the PWM pulses for three phases are calculated, and the result is calculated as the dual port RAM 1-3
Write in. Finally, in step 33, the operation signal 13
Is reset to "0", and a series of processing is completed. At this time, the presence or absence of abnormality of the first microcomputer 1-2 is detected by measuring the period of "1" of the operation signal 13. That is, when the operation time Tp of the first microcomputer shown in FIG. 7, which will be described later, is exceeded or insufficient, it is detected as an abnormality. On the other hand, as shown in FIG. 5, the second microcomputer 1-4 first reads the pulse width data from the dual port RAM 1-3 in step 40 and executes the pulse generation process. Next, in step 41, the monitoring process is executed, and the result is the dual port RAM.
The data is written in 1-7, and the series of processing is completed. As a result of the above processing, the second microcomputer 1-4 causes the pair of signals S _PU and S _NU , which form the basis of the U, V, and W phases shown in FIG.
Outputs S _PV and S _NV , and S _PW and S _NW . These signals are divided into four phases by the AND circuit group 1-8 and input to the gate driver 5, and the PWM pulse signals S _{U1 to} S _U4 , S _{V1 to} S _V4 , and S _{W1 to} S _{W4 which are} power-amplified are input. To get

The configuration and processing of the pulse generation means 1-4 will be described in detail below. The pulse generator 1-4 has
As shown in FIG. 6, the arithmetic processing unit CALC, one free running timer TIMER, six timer registers TRPU to TRNW, six comparators CMP, and 6
This consists of event registers IRPU to IRNW.
First, the arithmetic processing unit CALC converts the pulse width data output from the first microcomputer 1-2 into a relative value with respect to the free-running timer TIMER and sets it in each timer register TRPU to TRNW, and at each set time. Event information ('1' or '0') indicating the signal state is stored in each event register IRP.
Set to U to IRNW. Next, a free running timer TIMER and each timer register TRPU to TR
The values of NW are compared by the comparator CMP, and when they match, the value set in the event register is output. For example,
As shown in the timing chart of FIG. 7, at the value t0 of TIMER, the interrupt signal 22 of the interrupt cycle Ts is'
When it becomes 1 ', the pulse generation means 1-4 is activated, and the arithmetic processing unit CALC causes the timer register T
The time of t0 + T _UPU is _{stored in} the RPU and the event register I
Information of "1" is set in the RPU. As a result, the signal S
_PU becomes '1' after time T _UPU . Further, the value of TIMER t1 timer register TRPU t1 + T _DPU
The information of "0" is set in the event register IRPU for the time. As a result, the signal S _{PU becomes'after the} time T _DPU.
It becomes 0 '. Similarly, each signal is created. Also,
The operation signal 13 of the first microcomputer 1-2 is
By changing as shown in the figure and monitoring this operation time Tp, it is possible to know the presence or absence of an abnormality. FIG. 8 shows an overall flowchart of the pulse generation process including the above.
In the procedure 50, the arithmetic processing unit CALC reads the monitoring data, which will be described later, from the memory 1-6 built in the second microcomputer 1-4, and in the procedure 51, checks whether or not there is an abnormality. As a result, if there is no abnormality, proceed to step 5.
2 pulse width data in dual port RAM1-
Read from 3, convert and set in the timer register. Finally, in step 56, the value set in the event register is output when the signal is output from the comparator. On the other hand, if it is determined in step 51 that there is an abnormality, it is determined in step 53 whether or not it is an immediate stop. If it is an immediate stop, the gate stop signal 15 is set to "0", and in step 54, the main circuit 6 For the U phase, a pattern for turning off PDU1 and PDU4 and turning on PDU2 and PDU3 is set in each event register for the V and W phases. At this time, set each timer register as short as possible. Further, when it is determined in step 53 that the current is not the immediate stop, in step 55, a predetermined throttle pattern such that the current flowing through the induction motor IM becomes zero in a plurality of cycles of the interrupt signal 22 is set in each timer register and each event register. Set to.

The configuration and processing of the monitoring means 1-5 will be described in detail below. As shown in FIG. 9, the monitoring means 1-5 includes a free running timer TIMER and two capture registers CAPTURE1 and CAPTUR.
E2, subtractor SUB, time storage memory TIM, arithmetic processing unit CALC, memory ODAT for temporarily storing pulse width data output from the first microcomputer 1-2
A and a 6-bit memory SIG for storing the PWM pulse original signal 14 output from the pulse generation means 1-4. The monitoring means 1-5 monitors the operation status and calculation result (pulse width data) of the first microcomputer 1-2 and the PWM pulse original signal 14 of the pulse generation means 1-4. First, regarding the operation of the first microcomputer 1-2, the operation signal 13 is input to the capture registers CAPTURE1 and CAPTURE2 at the same time,
The value of the free-running timer TIMER is the operation signal 1
The data is stored in the capture register CAPTURE1 at the rising edge (processing start) of 3 and in the capture register CAPTURE2 at the falling edge (processing end). These values are subtracted by the subtractor SUB to obtain the operation time Tp of the first microcomputer 1-2, which is stored in the memory TIM. As a result, it is monitored whether the first microcomputer 1-2 is operating normally. Next, regarding the calculation result of the first microcomputer 1-2, the pulse width data written in the dual port RAM 1-3 is read to determine whether the data is larger than the interrupt cycle Ts or the previous data. The contents of the stored memory ODATA are compared, and it is monitored whether the amount of increase or decrease from the previous time is within the allowable range. Furthermore,
Regarding the monitoring of the PWM pulse original signal 14 of the pulse generation means 1-4, the state of each signal is read at the start of processing and stored in the memory SIG. The state of the signal at this time is the main circuit 6
It is monitored whether or not the pattern is an allowable pattern for the power element. Here, Table 1 of FIG. 11 shows a list of ignition modes in the case of using the U-phase power element of the main circuit 6 as an example. In the table, "0" indicates that the power element is off, and "1" indicates that the power element is on. According to the circuit shown in FIG. 3, among the modes shown in Table 1, modes 3, 6, 9, and 12 are actually conceivable (PDU1 and PDU3, PDU2 and PDU4 are in the opposite logic), but the state of mode 9 occurs. In that case, a phase short circuit may occur and the power element may be damaged. Therefore, it is monitored whether or not the state of the mode 9 is entered. FIG. 10 shows an overall flowchart of the monitoring process including the above process. The monitoring means 1-5 first takes in the PWM pulse original signal 14 in procedure 60, and determines whether or not there is an abnormality in the pulse in procedure 61 (mode 9 above).
Whether or not) is determined. As a result, if there is an abnormality, the least significant bit bit0 of the internal memory 1-6 is found in step 62.
Is set to "1" and if there is no abnormality, the procedure 62 is bypassed. Next, in step 63, the increase / decrease amount of the pulse width data is obtained, and in step 64, it is determined whether or not the pulse width data is normal. If there is an abnormality as a result, step 6
In step 5, bit1 of the internal memory 1-6 is set to "1", and if there is no abnormality, the procedure 65 is bypassed. Then, in step 66, the first microcomputer 1-
It is determined whether or not the operation time Tp of No. 2 is normal, and if there is an abnormality, the bit 2 of the internal memory 1-6 is set to'in step 67.
Set to 1 ', and if there is no abnormality, the procedure 67 is bypassed. Finally, the built-in memory 1-6 is a dual port RAM
After copying to 1-7, a series of processing is completed.

As described above, according to the present embodiment, the processing means and the pulse generating means are divided and processed by the microcomputers operating independently, so that the processing time can be shortened. Further, by providing the monitoring means, it is possible to prevent the power element of the main circuit from being damaged even when the PWM pulse generator is abnormal. In this embodiment, the first and second
, The microcomputer is activated in synchronization with the interrupt signal 22, but it can be asynchronous, and the first microcomputer has a longer interrupt cycle than the second microcomputer, and more It is also possible to perform the processing of. Further, the case where the present invention is applied to the three-level inverter device has been described.
It goes without saying that it can be applied to a two-level inverter device.

[0012]

According to the present invention, the processing of the PWM pulse generator can be speeded up, and at the same time, when the PWM pulse generator is abnormal, damage to the power element of the main circuit can be prevented. it can.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a PWM pulse generator.

FIG. 2 is a diagram showing a configuration of a three-level inverter control device.

FIG. 3 is a diagram showing a circuit configuration of an example.

FIG. 4 is a diagram showing an interrupt processing flowchart of the CPU 1.

FIG. 5 is a diagram showing an interrupt processing flowchart of the CPU 2.

FIG. 6 is a diagram showing a configuration of pulse generation means.

FIG. 7 is a diagram showing a PWM pulse output timing chart.

FIG. 8 is a diagram showing a pulse generation processing flowchart.

FIG. 9 is a diagram showing a configuration of monitoring means.

FIG. 10 is a diagram showing a monitoring processing flowchart.

FIG. 11 is a list of ignition modes of the power device (Table 1).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PWM pulse generator 1-2 Calculation means 1-4 Pulse generation means 1-5 Monitoring means 1-1, 1-3, 1-6, 1-7 Storage means

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Kiyoshi Nakamura 7-1, 1-1 Omika-cho, Hitachi City, Hitachi, Ltd. Hitachi Research Laboratory, Hitachi Ltd. (72) Inventor, Eiichi Toyota 1070, Ige, Katsuta-shi, Ibaraki Prefecture Hitachi Ltd. Mito Factory

Claims (14)

[Claims] 1. A calculation means for receiving at least a frequency command and an output voltage command from a higher-level processing device and calculating the pulse width of a PWM pulse based on these commands, and a pulse for generating a PWM pulse based on the output of the calculation means. A PWM pulse generator for a power converter having a generator, comprising means for monitoring the operations of the arithmetic means and the pulse generator, the PWM pulse generator for the power converter. 2. The calculating means and the pulse generating means are composed of two microcomputers that operate independently of each other, and the monitoring means is included in the microcomputer realizing the pulse generating means. Claim 1
The PWM pulse generator of the power converter according to. 3. A processing cycle T1 of a first microcomputer which realizes a computing means and a processing cycle T2 of a second microcomputer which realizes a monitoring means and a pulse generating means.
3. The PWM pulse generator for a power converter according to claim 2, wherein the relationship is set to T1 ≧ T2. 4. A processing cycle T1 of a first microcomputer which realizes a computing means and a processing cycle T2 of a second microcomputer which realizes a monitoring means and a pulse generating means.
3. The PWM pulse generator for a power conversion device according to claim 2, wherein the relationship is set to T1 = T2, and the first and second microcomputers are driven in synchronization. . 5. The calculation means outputs pulse width data corresponding to the conduction time of the power element of the main circuit, and the pulse generation means outputs PWM pulses for three phases based on the pulse width data. The PWM pulse generator of the power converter according to claim 1 or 2. 6. The pulse generation means converts the pulse width data output from the first microcomputer 1-2 into a relative value with respect to the free running timer TIMER and sets it in each of the timer registers TRPU to TRNW and sets the set time. The processing unit CALC sets event information indicating the state of each signal in each of the event registers IRPU to IRNW, and the comparator CMP that compares the values of the free running timer and each timer register. The PWM pulse generator of the power converter according to claim 5, wherein the set value is output. 7. The monitoring means monitors at least the processing time of the computing means, and when it determines that there is an abnormality, stops the output pulse of the pulse generating means in a predetermined procedure and notifies the upper processing device. The PWM of the power converter according to claim 1 or 2, further comprising:
Pulse generator. 8. The electric power according to claim 7, wherein the monitoring means determines that the computing means is abnormal when the processing time of the computing means becomes larger or smaller than a predetermined value. PWM pulse generator for converter. 9. The monitoring means monitors at least the pulse width data output from the computing means, and when it determines that there is an abnormality, stops the output pulse of the pulse generating means in a predetermined procedure, and at the same time, the upper processing device. The PWM pulse generator of the power converter according to claim 1 or 2, further comprising: 10. The monitoring means determines that the arithmetic means is abnormal when the pulse width data output from the arithmetic means becomes longer than the processing cycle of the pulse generating means. The PWM pulse generator of the power converter according to. 11. The monitoring means is configured to determine that the arithmetic means is abnormal when the increase / decrease amount of the pulse width data output from the arithmetic means is outside a predetermined range. PWM pulse generator for power converter. 12. The monitoring means monitors at least the output pulse state of the pulse generating means, and when it judges that there is an abnormality,
3. A means for immediately stopping the output pulse and notifying the upper processing device.
Alternatively, the PWM pulse generator of the power converter according to claim 2. 13. The monitoring means is in a pulse state of a pattern in which the output of the pulse generating means out of a plurality of power elements connected in series forming one phase of the power conversion device causes a phase short circuit when they are simultaneously conducted. The PWM pulse generation device of the power conversion device according to claim 12, wherein the pulse generation means is determined to be abnormal in the case. 14. The monitoring means comprises a free running timer TIMER and two capture registers CAP.
TURE1 and CAPTURE2, a subtractor SUB, a time storage memory TIM, an arithmetic processing unit CALC, a memory ODATA which temporarily stores the pulse width data output from the first microcomputer 1-2, and pulse generation means 1- 14. The PWM pulse generator of the power converter according to claim 7, further comprising a 6-bit memory SIG for storing the original PWM pulse signal 14 output from No. 4.