AU2020441878B2 - Frequency converter IGBT drive control method and control apparatus - Google Patents

Frequency converter IGBT drive control method and control apparatus Download PDF

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AU2020441878B2
AU2020441878B2 AU2020441878A AU2020441878A AU2020441878B2 AU 2020441878 B2 AU2020441878 B2 AU 2020441878B2 AU 2020441878 A AU2020441878 A AU 2020441878A AU 2020441878 A AU2020441878 A AU 2020441878A AU 2020441878 B2 AU2020441878 B2 AU 2020441878B2
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logic signal
flag
processor
level
trigger
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AU2020441878A1 (en
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Ning HAN
Kun Liu
Xian Liu
Chenglin SONG
Hongbo Zhang
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Qingdao CCS Electric Corp
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Qingdao CCS Electric Corp
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Control Of Direct Current Motors (AREA)
  • Control Of High-Frequency Heating Circuits (AREA)
  • Control Of Electric Motors In General (AREA)

Abstract

A frequency converter IGBT drive control method, and a control apparatus. The method comprises the following steps: a first processor determines whether to generate a trigger electrical level signal according to an operational state of a frequency converter (S1); if a trigger electrical level signal is generated, the first processor receives a feedback signal output by a drive circuit, and determines whether an output pulse is present in the feedback signal (S2); if an output pulse is present in the feedback signal, and an electrical level state of the trigger electrical level signal is the same as a current feedback signal, then the first processor outputs a drive abnormal electrical level signal to a second processor (S31); if an output pulse is present in the feedback signal, and the electrical level state of the trigger electrical level signal is opposite the current feedback signal, then the first processor outputs a drive normal electrical level signal to the second processor (S32). By utilizing the present method, A protection effect for an IGBT inverter unit can be achieved without configuring an external crystal oscillator, complete logic control can be accomplished with just a drive circuit being able to feed back a pulse signal, and a frequency converter system can be adapted for use with various drive circuits.

Description

Inverter IGBT Drive Control Method and Control Device
Technical field
The invention belongs to the technical field of power electronics, and in particular relates to an inverter IGBT drive control method and an inverter IGBT drive control device.
Background
In recent years, the frequency conversion technology with the inverter circuit as the core has been continuously improved and developed rapidly. Applications of high power inverter technology are growing. High-power inverters usually use high-power IGBTs as the main switching devices of inverter circuits and the changes of their on/off states are realized by main control circuits with microcontrollers as the core through driving circuits.
A variety of drivers available on the market could be selected as the driving circuit, such as the single-channel plug-and-play driver 1SP0335 produced and sold by Power Integrations. The driver can safely and reliably drive parallel, high-voltage and high-power IGBT modules with a driving logic for normal operation that returning a 700ns high-level pulse signal after receiving a trigger signal and returning a 700ns high-level pulse after receiving a shutdown signal to represent the normal operation of the driver. Furthermore if a fault occurs in during the triggering process a 9ps high-level signal is returned. In order to collect timing signals fed back by the driver, under normal circumstances, it is necessary to configure an external crystal oscillator with high precision and high processing performance for a CPLD to capture.
But if the IGBT module is used to drive an inductive load, such as a motor, etc., it is necessary to collect six IGBT timing signals, which puts very high requirements on the external crystal oscillator. In addition, since the driver may also be integrated with a DC voltage detection module, an output voltage detection module, and a current detection module on one same PCB circuit board, the external crystal oscillator may introduce high-frequency signals, which can easily lead to EMC exceeding the standard and affect the detection accuracy.
Summary
Aiming at solving problems in the prior art that the frequency converter IGBT needs to be assisted by an external crystal oscillator when the drive control is performed, the matching degree of between driving applications and the available chips in the prior art is low, and in additionally high-frequency signal are easily introduced to cause the
EMC exceeding its standard, an inverter IGBT drive control method is designed and proposed.
One aspect of the present invention is to provide an inverter IGBT drive control method including the following steps: a first processor determines whether or not to generate a trigger logic signal according to states of a frequency converter; when the frequency converter is in a working state and the trigger logic signal is generated, the first processor starts receiving a feedback logic signal from a driving circuit and determines whether or not there is an output pulse in the feedback logic signal; the driving circuit continues to send a current ongoing feedback logic signal after determining or not there is the output pulse of the feedback logic signal; if there is an output pulse in the feedback logic signal, and a level of the current ongoing feedback logic signal and a level of the trigger logic signal are the same, the first processor outputs an abnormal driving logic signal to a second processor; and if there is an output pulse in the feedback logic signal, and the level of the current ongoing feedback logic signal and the level of the trigger logic signal are the opposite, the first processor outputs a normal driving logic signal to a second processor.
In order to ensure normal control logic in a standby state, if the first processor determines to not generate the trigger logic signal according to states of the frequency converter, the first processor outputs a system maintaining logic signal to the second processor; wherein the level of the system maintaining logic signal is the same as the level of the abnormal driving logic signal.
Preferably, the abnormal driving logic signal is logical high, the normal driving logic signal is logical low, and the system maintaining logic signal is logical high.
Alternatively, the abnormal driving logic signal is logical low, the normal driving logic signal is logical high, and the system maintaining logic signal is logical low.
In order to improve processing speed and capability, the method further includes steps that: configuring a first flag, a second flag, a third flag and a fourth flag in the first processor; wherein in an initial state, flag values of the first flag, the second flag, the third flag and the fourth flag are assigned as 0 by default; if the first processor determines not to generate the trigger logic signal according to states of the frequency converter, the flag values of the first flag and the second flag are assigned unchanged as 0; if the first processor determines to generate the trigger logic signal according to states of the frequency converter and receives a feedback logic signal from the driving circuit, the flag values of the first flag and second flag are assigned as 1; if the first processor determines there is an output pulse in the feedback logic signal, the flag value of the third flag is assigned to follow the trigger logic signal; if the trigger logic signal is generated, the flag value of the third flag is assigned as 1; judging whether the flag values of the first flag, the second flag and the third flag are all assigned as 1; if the flag values of the first flag, the second flag and the third flag are all assigned as
1, the flag value of the fourth flag is assigned as 1 and the first processor outputs the abnormal driving logic signal to the second processor; if the flag values of the first flag, the second flag and the third flag are not all assigned as 1, the flag value of the fourth flag is assigned unchanged as 0; if the flag values of the first flag and the second flag are both assigned as 0, the first processor outputs the system maintaining logic signal; if the flag values of the first flag and the second flag are both assigned as 1, the first processor outputs the normal driving logic signal.
Preferably, the first processor is a CPLD controller.
Another aspect of the present invention is to provide an inverter IGBT drive control device including: a trigger logic signal generation module configured to determine whether or not generate a trigger logic signal according to states of the frequency converter; a first determination module configured to receive a feedback logic signal from the driving circuit and determine whether there is an output pulse in the feedback logic signal when the trigger logic signal is generated, wherein the driving circuit continues to send a current ongoing feedback logic signal after first determination module determines whether or not there is the output pulse of the feedback logic signal; a second determination module configured to determine whether a level of the current ongoing feedback logic signal and a level of the trigger logic signal are the same under the condition that there is an output pulse in the feedback logic signal; and a signal output module configured to output an abnormal driving logic signal to an external processor once the second determination module determines that the level of the current ongoing feedback logic signal and the level of the trigger logic signal are the same; or configured to output a normal driving logic signal to an external processor once the second determination module determines that the level of the current ongoing feedback logic signal and the level of the trigger logic signal are the opposite.
Further the signal output module is further configured to output a system maintaining logic signal to an external processor once no trigger logic signal is generated; wherein the level of the system maintaining logic signal is same as the level of the abnormal driving logic signal to guarantee the operation in the standby state.
Preferably, the abnormal driving logic signal is logical high, the normal driving logic signal is logical low, and the system maintaining logic signal is logical high.
Alternatively, the abnormal driving logic signal is logical low, the normal driving logic signal is logical high, and the system maintaining logic signal is logical low
By generating and outputting the trigger logic signal according to working states of the frequency converter, as well as collecting and monitoring an output pulse in the feedback logic signal from the driving circuit, the level of the current ongoing feedback logic signal and the level of the trigger logic signal, the protection for the
IGBT inverter unit could be realized without the assistance of an external crystal oscillator. The control method is realized as long as the driving circuit could provide the feedback logic signal with one or more output pulses, accordingly more driving circuits could be applied to the inverter system.
Description of drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, a brief description of the accompanying drawings to be used in the embodiments will be given below. It is obvious that the accompanying drawings in the following description are some embodiments of the present invention, and other accompanying drawings can be obtained according to these accompanying drawings without any creative work for a person of ordinary skill in the art.
Fig.1 is a flowchart of an inverter IGBT drive control method according to one aspect of the present invention.
Fig.2 is a flowchart of an inverter IGBT drive control method according to one aspect of the present invention.
Fig.3 is a flowchart of an inverter IGBT drive control method according to one aspect of the present invention.
Fig.4 is a system diagram of frequency converter control system.
Fig.5 is a schematic block diagram of an inverter IGBT drive control device according to another aspect of the present invention.
Detailed Description of the Present Invention
In order to make the object, technical solution and advantages of the invention clearer and more understandable, the invention will be described in further detail hereinafter in conjunction with the accompanying drawings and embodiments.
The terms "first", "second", "third", etc. in the specification and claims of the present invention and in the said drawings are used to distinguish between different objects and are not intended to describe a specific order. In addition, the terms "comprising" and "having", and any variation thereof, represent non-exclusive inclusion. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or optionally also includes other steps or units inherent to those processes, methods, products, or apparatus.
In the present invention "embodiment" means that a particular feature, structure or characteristic described in connection with an embodiment may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily mean the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It is understood by those of skill in the art that the embodiments described herein may be combined with other embodiments.
Served as an early warning and protection, an inverter IGBT drive control method is disclosed in Fig.1, aiming at provide a support for a frequency converter system with which the selection of driving circuits could be extended without the assistance of an external crystal oscillator. At first, the physical parts of a frequency converter control system are introduced with reference to Fig.4. In a comprehensive manner, in the frequency converter control system (such as a frequency converter system for speed regulation), PWM signals generated by DSP are output to an IGBT inverter unit to control its on/off states, further to control operation states of the system load. The PWM signals generated by DSP is either transmitted serially or in parallel, in which optical fibers are preferably used to serve as the media fit for long-distance signal transmission for high-power frequency converters. The operation and the protection functions of the IGBT inverter unit is realized by a driving circuit. In the present embodiment, the driving circuit could be selected from available integrated driving circuit chips produced and sold by a number of manufactures, including a single-channel plug-and play driver 1SP0335 or 1SP0635 produced and sold by Power Integrations. In the frequency converter control system, a bidirectional communication between the driving circuit and a first processor is established to upload working states of the IGBT inverter unit. Further taking into consideration that there may be a potential mismatch between an extension on signal channels and the limited output ports of a DSP, the first processor is preferably implemented by a CPLD controller in the present embodiment which has a more stable performance and a faster signal transmission speed to cope with the IGBT inverter unit, so as to fulfill various functions in a flexible way. Optical fibers are also used to serve as the transmission media of the CPLD controller fit for long-distance signal transmission of high-power frequency converters.
Automatic monitoring on working states of the IGBT inverter units without the assistance of an external crystal oscillator could be realized by a control method as follows which has detailed steps.
Sl: the first processor determines whether or not to generate a trigger logic signal according to states of the frequency converter. When the frequency converter is in a working state, the first processor generates a trigger logic signal to maintain the operation of the frequency converter system; when the frequency converter is in a standby state, the first processor interrupts generating the trigger logic signal. Preferably the trigger logic signal is logical high.
S2: when the frequency converter is in the working state and the trigger logic signal is generated, the first processor starts receiving a feedback logic signal from the IGBT inverter unit driving circuit. Specifically the first processor further determines whether or not there is an output pulse in the feedback logic signal. For further explanation the output pulse is defined by including one or more falling edge, which means if the first processor detects a complete combination of a high level, a falling edge and a low level in the feedback logic signal, thefirst processor determines that there is an output pulse in the feedback logic signal. The communication between the first processor and the driving circuit functions properly.
S31: if there is an output pulse in the feedback logic signal, thefirst processor further determines whether a level of a current ongoing feedback logic signal and a level of the trigger logic signal are same. If the level of the current ongoing feedback logic signal and the level of the trigger logic signal are same, it means that the switching actions of the IGBT inverter unit controlled by the driving circuit do not function well and the first processor starts outputting an abnormal driving logic signal to a second processor.
S32: if there is an output pulse in the feedback signal but the level of the current feedback signal and the level of the trigger level signal are opposite, it means that the switching actions of the IGBT inverter unit controlled by the driving circuit functions properly and the first processor starts outputting a normal driving logic signal to the second processor.
The second processor could be an upper computer of the CPLD controller or other integrated chips with data processing capability and independent multi-channel I/O. Other details of the second processor will not be further limited here.
By generating and outputting the trigger logic signal according to working states of the frequency converter, as well as collecting and monitoring an output pulse in the feedback logic signal from the driving circuit, the level of the current ongoing feedback logic signal and the level of the trigger logic signal, the protection for the IGBT inverter unit could be realized without the assistance of an external crystal oscillator. The control method is realized as long as the driving circuit could provide the feedback logic signal with one or more output pulses, accordingly more driving circuits could be applied to the inverter system.
As shown in Fig.2, when the frequency converter is in the standby state, in Step S22, the first processor determines to not to generate the trigger logic signal and the first processor further outputs a system maintaining logic signal to the second processor. The level of the system maintaining logic signal is same as the level of the abnormal driving logic signal.
In the present embodiment, preferably the abnormal driving logic signal is logical high, the normal driving logic signal is logical low, and the system maintaining logic signal is logical high.
Alternatively, possibly the abnormal driving logic signal is logical low, the normal driving logic signal is logic high, and the system maintaining logic signal is logical low.
Taking the abnormal driving logic signal is logical high, the normal driving logic signal is logical low, and the system maintaining logic signal is logical high as an example, a specified control method will be further explained with reference to Fig.3, which is applied to a system in which a CPLD controller is used as the first processor.
S10: configuring a first flag, a second flag, a third flag and a fourth flag in the first processor; wherein in an initial state, flag values of the first flag, the second flag, the third flag and the fourth flag are assigned as 0 by default.
S11: if the first processor determines not to generate the trigger logic signal according to states of the frequency converter, the flag values of the first flag and the second flag are assigned unchanged as 0 for further determination.
S12: if the first processor determines to generate the trigger logic signal according to states of the frequency converter and receives a feedback logic signal from the driving circuit, the flag values of the first flag and second flag are assigned as 1 for further determination.
S13: if the first processor determines there is an output pulse in the feedback logic signal, the flag value of the third flag is assigned to follow the trigger logic signal. That is to say, if thefirst processor determines to generate the trigger logic signal according to states of the frequency converter, the flag value of the third flag is assigned as 1; and if thefirst processor determines not to generate the trigger logic signal according to states of the frequency converter, the flag value of the third flag is assigned unchanged as 0.
S14: outputting a normal driving logic signal or an abnormal driving signal according to the flag values of the first flag, the second flag and the third flag; specifically by judging whether the flag values of the first flag, the second flag and the third flag are all assigned as 1.
S15: if the flag values of the first flag, the second flag and the third flag are all assigned as 1, the flag value of the fourth flag is assigned as 1 and thefirst processor outputs the abnormal driving logic signal to the second processor. That means an external processor could monitor real-time working states of the system by simply calling the sentinel value of the fourth flag for early warning or intervention in time.
S16: if the flag values of the first flag, the second flag and the third flag are not all assigned as 1, the flag value of the fourth flag is assigned unchanged as 0.
S17: if the flag values of the first flag and the second flag are both assigned as 0, the first processor outputs the system maintaining logic signal.
S18: if the flag values of the first flag and the second flag are both assigned as 1, the first processor outputs the normal driving logic signal.
By applying this preferable processing method, the system could output specific kinds of logic signals by judging the flag values of the first flag, the second flag and the third flag and determine states of the frequency converter. Additionally, an external processor could monitor real-time working states of the system by simply calling the sentinel value of the fourth flag and perform a quick intervene for the system if the flag value of the fourth flag is 1, thereby improving the response efficiency.
Another aspect of the present invention is to provide an inverter IGBT drive control device, as shown in Fig.5, including the following modules.
A trigger logic signal generation module 10 is configured to determine whether or not to generate a trigger logic signal according to states of the frequency converter: when the frequency converter is in a working state, the trigger logic signal generation module 10 is configured to output a trigger logic signal; when the frequency converter is in a standby state, the trigger logic signal generation module 10 is configured to interrupt generating the trigger logic signal. Preferably the trigger logic signal is logical high.
A first determination module 12 is configured to receive a feedback logic signal from the driving circuit and determine whether there is an output pulse in the feedback logic signal when the trigger logic signal is generated. The output pulse is defined by including one or more falling edge. So if a complete combination of a high level, a falling edge and a low level in the feedback logic signal is detected, the first determination module 12 is determined that there is an output pulse in the feedback logic signal.
A second determination module 13 is configured to determine whether a level of a current ongoing feedback logic signal and a level of the trigger logic signal are same under the condition that there is an output pulse in the feedback logic signal; if a level of a current ongoing feedback logic signal and a level of the trigger logic signal are same, it means the switching actions of the IGBT inverter unit controlled by the driving circuit do not function properly; if a level of a current ongoing feedback logic signal and a level of the trigger logic signal are opposite, it means the switching actions of the IGBT inverter unit controlled by the driving circuit function well.
A signal output module 14 is configured to output an abnormal driving logic signal to an external processor once the second determination module 13 determines that the level of the current ongoing feedback logic signal and the level of the trigger logic signal are same; or configured to output a normal driving logic signal to an external processor once the second determination module 13 determines that the level of the current ongoing feedback logic signal and the level of the trigger logic signal are opposite.
Through a coordinated control based on the above-mentioned multiple modules, it is possible to generate and output the trigger logic signal according to working states of the frequency converter, and to collect and monitor an output pulse in the feedback logic signal from the driving circuit, the level of the current ongoing feedback logic signal and the level of the trigger logic signal. The protection control device could match with a wide selection of driving circuits merely capable of generating and outputting a feedback pulse or square wave signal and there is no need to provide an external crystal oscillator, which is flexible in use.
The signal output module 14 is further configured to output a system maintaining logic signal to an external processor once no trigger logic signal is generated; wherein the level of the system maintaining logic signal is same as the level of the abnormal driving logic signal to guarantee the operation in the standby state.
In the present embodiment, preferably the abnormal driving logic signal is logical high, the normal driving logic signal is logical low, and the system maintaining logic signal is logical high. Alternatively the abnormal driving logic signal is logical low, the normal driving logic signal is logic high, and the system maintaining logic signal is logical low.
Embodiments of the present application further provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data interchange, the computer program causing the inverter to perform some or all of the steps of any of the methods as documented in the method embodiments above.
In the above embodiments, the description of each embodiment has its own focus, and the parts of an embodiment that are not described in detail can be found in the relevant descriptions of other embodiments.
In several of the embodiments provided in this application, it should be understood that the disclosed device can be implemented in other ways. For example, the above described embodiments of the device are only schematic, for example, the division of units or modules described above, is only a logical functional division, the actual implementation can be divided in another way, for example multiple units or components can be combined or can be integrated into another system, or some features can be ignored, or not implemented. On another point, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, either electrical or otherwise.
The units illustrated above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in a physical space or may also be distributed to a plurality of network units, some or all of which may be selected to achieve the purpose of the present embodiment solution, depending on practical needs.
In addition, each functional unit in each embodiment of the present application can be integrated in a single processing unit, or each unit can be physically present separately, or two or more units can be integrated in a single unit. The above integrated units can be implemented either in the form of hardware or in the form of software functional units.
The above embodiments are used only to illustrate the technical solution of the present invention, not to limit it; despite the detailed description of the invention with reference to the preceding embodiments, it is still possible for a person of ordinary skill in the art to modify the technical solution recorded in the preceding embodiments, or to make equivalent substitutions for some of the technical features thereof; and these modifications or substitutions do not make the essence of the corresponding technical solution depart from the spirit and scope of the technical solution claimed to be protected by the present invention.

Claims (10)

Claims:
1. An inverter IGBT drive control method, characterized in that it comprises steps that: a first processor determines whether or not to generate a trigger logic signal according to states of a frequency converter; when the frequency converter is in a working state and the trigger logic signal is generated, the first processor starts receiving a feedback logic signal from a driving circuit and determines whether or not there is an output pulse in the feedback logic signal; the driving circuit continues to send a current ongoing feedback logic signal after determining or not there is the output pulse of the feedback logic signal; if there is an output pulse in the feedback logic signal, and a level of the current ongoing feedback logic signal and a level of the trigger logic signal are the same, the first processor outputs an abnormal driving logic signal to a second processor; and if there is an output pulse in the feedback logic signal, and the level of the current ongoing feedback logic signal and the level of the trigger logic signal are the opposite, the first processor outputs a normal driving logic signal to a second processor.
2. An inverter IGBT drive control method according to claim 1, characterized in that, if the first processor determines to not generate the trigger logic signal according to states of the frequency converter, the first processor outputs a system maintaining logic signal to the second processor; wherein the level of the system maintaining logic signal is same as the level of the abnormal driving logic signal.
3. An inverter IGBT drive control method according to claim 2, characterized in that, the abnormal driving logic signal is logical high, the normal driving logic signal is logical low, and the system maintaining logic signal is logical high.
4. An inverter IGBT drive control method according to claim 2, characterized in that, the abnormal driving logic signal is logical low, the normal driving logic signal is logical high, and the system maintaining logic signal is logical low.
5. An inverter IGBT drive control method according to claim 3, characterized in that it includes steps that: configuring a first flag, a second flag, a third flag and a fourth flag in the first processor; wherein in an initial state, flag values of the first flag, the second flag, the third flag and the fourth flag are assigned as 0 by default; if the first processor determines not to generate the trigger logic signal according to states of the frequency converter, the flag values of the first flag and the second flag are assigned unchanged as 0; if the first processor determines to generate the trigger logic signal according to states of the frequency converter and receives a feedback logic signal from the driving circuit, the flag values of the first flag and second flag are assigned as 1; if the first processor determines there is an output pulse in the feedback logic signal, the flag value of the third flag is assigned to follow the trigger logic signal; if the trigger logic signal is generated, the flag value of the third flag is assigned as 1; judging whether the flag values of the first flag, the second flag and the third flag are all assigned as 1; if the flag values of the first flag, the second flag and the third flag are all assigned as 1, the flag value of the fourth flag is assigned as 1 and thefirst processor outputs the abnormal driving logic signal to the second processor; if the flag values of the first flag, the second flag and the third flag are not all assigned as 1, the flag value of the fourth flag is assigned unchanged as 0; the first processor outputs the system maintaining logic signal; if the flag values of the first flag and the second flag are both assigned as 1, the first processor outputs the normal driving logic signal.
6. An inverter IGBT drive control method, characterized in that, the first processor is a CPLD controller.
7. An inverter IGBT drive control device, characterized in that it includes: a trigger logic signal generation module configured to determine whether or not generate a trigger logic signal according to states of a frequency converter; a first determination module configured to receive a feedback logic signal from a driving circuit and determine whether there is an output pulse in the feedback logic signal when the trigger logic signal is generated, wherein the driving circuit continues to send a current ongoing feedback logic signal after first determination module determines whether or not there is the output pulse of the feedback logic signal; a second determination module configured to determine whether a level of the current ongoing feedback logic signal and a level of the trigger logic signal are the same under the condition that there is an output pulse in the feedback logic signal; and a signal output module configured to output an abnormal driving logic signal to an external processor once the second determination module determines that the level of the current ongoing feedback logic signal and the level of the trigger logic signal are the same; or configured to output a normal driving logic signal to an external processor once the second determination module determines that the level of the current ongoing feedback logic signal and the level of the trigger logic signal are the opposite.
8. An inverter IGBT drive control device according to claim 7, characterized in that: the signal output module is further configured to output a system maintaining logic signal to an external processor once no trigger logic signal is generated; wherein a level of the system maintaining logic signal is same as the level of the abnormal driving logic signal to guarantee operation in a standby state.
9. An inverter IGBT drive control device according to claim 8, characterized in that: the abnormal driving logic signal is logical high, the normal driving logic signal is logical low, and the system maintaining logic signal is logical high.
10. An inverter IGBT drive control device according to claim 8, characterized in that: the abnormal driving logic signal is logical low, the normal driving logic signal is logic high, and the system maintaining logic signal is logical low.
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