CN217428105U - Communication port circuit, chip and electronic equipment - Google Patents

Abstract

The embodiment of the disclosure relates to a communication port circuit, a chip and an electronic device. The communication port circuit includes: the output module is used for processing and outputting the input signal; and the control module is connected with the output module and is used for controlling the transient current change during the working of the output module. In the embodiment of the disclosure, the transient current change during the operation of the output module is controlled by the control module through the communication port circuit, so that the transient current during the opening of the output module is reduced, the overshoot voltage caused by the sudden change of the current is obviously reduced, and the electromagnetic interference is reduced.

Description

Communication port circuit, chip and electronic equipment

Technical Field

The embodiment of the disclosure relates to the technical field of communication, in particular to a communication port circuit, a chip and an electronic device.

Background

In IO (Input/Output) communication, there may be EMI (Electromagnetic Interference) problems in a circuit due to a circuit board layout, or there may be problems such as a large overshoot of an OD gate (open drain gate). A plurality of IO (input/output) ports are arranged between GPIO (general purpose input/output) communication ports of different chips, and a parasitic inductor L and a parasitic capacitor are arranged between the two chips. When the output signal of one of the IO ports is inverted to a high level and a low level 0-1, a current flowing in the direction of the capacitor is generated, and since the inductor current cannot be suddenly changed, a current in the opposite direction is generated inside the inductor, and the current in the opposite direction hinders the increasing trend of the current flowing in the direction of the capacitor, so that the current flows out of the capacitor to generate an overshoot voltage.

According to maxwell's equations, the overshoot voltage is excessive, and the current and voltage generate an alternating electromagnetic field that interacts with conductive components (e.g., copper traces on a printed circuit board), thereby presenting a significant EMI problem.

Therefore, there is a need to improve the problems of the above solutions.

SUMMERY OF THE UTILITY MODEL

An object of the embodiments of the present disclosure is to provide a communication port circuit, a chip and an electronic device, so as to at least improve the problem of electromagnetic interference.

The purpose of the embodiment of the disclosure is realized by adopting the following technical scheme:

in a first aspect, an embodiment of the present disclosure provides a communication port circuit, including:

the output module is used for processing and outputting the input signal; and

and the control module is connected with the output module and is used for controlling the transient current change during the working of the output module.

The beneficial effect of the embodiment is that the transient current change during the work of the output module is controlled by the control module through the communication port circuit, so that the transient current during the start of the output module is reduced, the overshoot voltage caused by the sudden change of the current is obviously reduced, and the electromagnetic interference is reduced.

Optionally, the output module includes N output port units, where the N output port units are connected in parallel; wherein N is an integer of 2 or more.

Optionally, the control module includes N-1 first delay control units, each of the first delay control units is connected to the other output port units except the first output port unit in a one-to-one correspondence manner, and each of the first delay control units controls the output port unit to operate in a time-sharing manner.

The embodiment has the advantages that each output port unit receives input signals at different moments under the control of the control signal, different output port units can be started at different moments due to different moments of the received input signals, and the starting of each output port unit is carried out in a time-sharing mode, so that the instantaneous current when the output port units are started is remarkably reduced, the sudden change current is further reduced, the corresponding sudden change voltage is also reduced, and the purpose of reducing electromagnetic interference is finally achieved.

Optionally, the first delay control unit includes an even number of inverters connected in series, and an input terminal of a first inverter receives the input signal and an output terminal of a last inverter is connected to the output port unit.

Optionally, the control module includes N-1 second delay control units, where the N-1 second delay control units receive an input signal and a control signal, and are connected to N-1 output port units, except for a first one of the output port units, of the N output port units in a one-to-one correspondence, and the N-1 second delay control units control the N output port units to operate in a time-sharing manner according to the input signal and the control signal, respectively.

Optionally, the second delay control unit includes a nor gate, a first input terminal of the nor gate receives the input signal, a second input terminal of the nor gate receives the control signal, and an output terminal of the nor gate is connected to one of the N-1 output port units.

Optionally, the control module includes at least one third delay control unit, and each third delay control unit is connected to the output port unit and controls the N output port units to operate in a time-sharing manner according to the input signal and the control signal.

Optionally, the third delay control unit includes a switch element and a capacitor, a first end of the switch element is connected to the output port unit and receives the input signal, a control end of the switch element receives the control signal, a second end of the switch element is connected to the first end of the capacitor, and a second end of the capacitor is grounded.

The embodiment has the advantages that after the switch element is switched on, the capacitor starts to charge, and the charge time of the capacitor is utilized to realize the inversion of the level, so that the opening degree of the output port unit is controlled, and the time-sharing work of the output port unit is realized.

In a second aspect, an embodiment of the present disclosure further provides a chip, where the chip includes the communication port circuit in any of the above embodiments.

In a third aspect, an embodiment of the present disclosure further provides an electronic device, where the electronic device includes: the chip of the above embodiment.

The technical scheme provided by the embodiment of the disclosure can have the following beneficial effects:

in the embodiment of the disclosure, the transient current change during the operation of the output module is controlled by the control module through the communication port circuit, so that the transient current during the opening of the output module is reduced, the overshoot voltage caused by the sudden change of the current is obviously reduced, and the electromagnetic interference is reduced.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of embodiments of the disclosure.

Drawings

The embodiments of the disclosure are further illustrated in the following figures and examples.

FIG. 1 is a block diagram of a communications port circuit in one embodiment of the present disclosure;

FIG. 2 is a block diagram of a communication port circuit in another embodiment of the present disclosure;

FIG. 3 is a block diagram of a communication port circuit in another embodiment of the present disclosure;

FIG. 4 is a block diagram of a communications port circuit in another embodiment of the present disclosure;

FIG. 5 is a schematic circuit diagram of a communication port circuit in another embodiment of the present disclosure;

FIG. 6 is a block diagram of a communication port circuit in another embodiment of the present disclosure;

FIG. 7 is a schematic circuit diagram of a communication port circuit in another embodiment of the present disclosure;

FIG. 8 is a block diagram of a communication port circuit in another embodiment of the present disclosure;

fig. 9 is a circuit configuration schematic diagram of a communication port circuit in another embodiment of the present disclosure;

fig. 10 is a schematic configuration diagram of a communication port circuit in the related art;

FIG. 11: FIG. 11a is a diagram illustrating current values generated by a communication port according to the related art, and FIG. 11b is a diagram illustrating current values generated by a communication port according to an embodiment of the present disclosure;

FIG. 12: fig. 12a is a schematic diagram of voltage values generated by a communication port in the related art, and fig. 12b is a schematic diagram of voltage values generated by a communication port in an embodiment of the present disclosure.

Reference numerals:

100. a communication port circuit; 101. an output module; 1011. an output port unit; 102. a control module; 1021. a first delay control unit; 10211. an inverter; 1022. a second delay control unit; 1023. a second delay control unit; 10231. a switching element; 10232. and (4) a capacitor.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features may be combined in any suitable manner in one or more embodiments.

Furthermore, the drawings are merely schematic illustrations of embodiments of the disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities.

First, in this exemplary embodiment, a communication port circuit 100 is provided, and referring to fig. 1, the communication port circuit 100 includes: an output module 101 and a control module 102. The output module 101 is configured to process and output an input signal. The control module 102 is connected to the output module 101, and is configured to control a transient current change during operation of the output module 101.

In this embodiment, the transient current change during the operation of the output module 101 is controlled by the control module 102 through the communication port circuit, so that the transient current during the start of the output module 101 is reduced, and the overshoot voltage caused by the sudden change of the current is significantly reduced, thereby reducing the electromagnetic interference.

The following describes the specific structure of the output module 101 in detail, as follows:

referring to fig. 2, the output module 101 includes N output port units 1011, where the N output port units 1011 are connected in parallel; wherein N is an integer of 2 or more. The input ends of the N output port units 1011 after being connected in parallel are connected to the control module 102, and the control module 102 receives an input signal to control the transient current magnitude when the N output port units 1011 are turned on, so that the transient current when the N output port units 1011 are turned on is reduced, and the current jump is reduced, thereby significantly reducing the overshoot voltage when the N output port units 1011 are turned on, and reducing the possibility of electromagnetic interference.

The above is a description of the structure of the output module 101, and the following is a detailed description of the specific structure of the control module 102, as follows:

referring to fig. 3, the control module 102 includes N-1 first delay control units 1021. Each first delay control unit 1021 is connected with the remaining output port units 1011 except the first output port unit 1011 in a one-to-one correspondence manner, and each first delay control unit 1021 controls the output port units 1011 to operate in a time-sharing manner. Wherein, the N-1 first delay control units 1021 may be all connected in series or may be independent of each other.

In this embodiment, a first delay control unit 1021 is connected to a second output port unit 1011, then the second first delay control unit 1021 is connected to a third output port unit 1011, when the first delay control units 1021 are connected in series, the third output port unit 1011 receives the delay caused by the two first delay control units 1021, and so on, the delay duration of each output port unit 1011 is different, and the N output ports 1011 implement time-sharing operation. It should be noted that the time-sharing operation of the N output port units 1011 means that the initial operating time nodes of the N output port units 1011 are different, that is, the N output port units 1011 are sequentially turned on according to different control delays and different durations, that is, the operating times of the N output port units 1011 may have an intersection, and it can be understood by those skilled in the art that, in other embodiments, after the N output port units 1011 are sequentially turned on according to different control delays and different durations as needed, the operating times may also have no intersection.

It is understood that, referring to fig. 4, N-1 first delay control units 1021 may be all connected in series. Specifically, the first delay control unit 1021 may include an even number of inverters 10211 (the case where the first delay control unit 1021 includes two inverters 10211 is exemplarily shown in the drawing, but the present application does not specifically limit the number of inverters 10211). In fig. 4, an even number of inverters 10211 in each first delay control unit 1021 are connected in series, and different first delay control units 1021 are connected in series, an input terminal of a first inverter 10211 of a first delay control unit 1021 receives an input signal, an output terminal of a last inverter 10211 of the first delay control unit 1021 is connected to an output port unit 1011 and an input terminal of a first inverter 10211 of a next first delay control unit 1021, that is, an output of a previous first delay control unit 1021 is an input of the next first delay control unit 1021. The first output port unit 1011 directly receives the input signal to realize the start, and the other output port units 1011 receive different delays, and respectively start to operate under different delays, so that the time-sharing start of the N output port units 1011 is achieved. That is, the second output port unit 1011 is connected to the two inverters 10211, so as to implement the first delay caused by the two inverters 10211; the third output port unit 1011 is connected to the four inverters 10211, and the second delay time caused by the four inverters 10211 is implemented. Thereby achieving the time-sharing opening of the N output port units 1011. For example, the second output port unit 1011 is delayed by time t by two inverters 10211, and the third output port unit 1011 is delayed by time 2t by four inverters 10211, so that the three output port units 1011 operate at 0, t and 2t, respectively, and thus the three output port units 1011 are sequentially delayed to be turned on.

In the above embodiment, N-1 first delay control units 1021 are all connected in series, and the turn-on times of the N output port units 1011 are sequentially increased, so that the N output port units 1011 are turned on in a time-sharing manner. However, different first delay control units 1021 may not be all serially connected, and referring to fig. 5, different first delay control units 1021 may be independent of each other. The N-1 output port units 1011 except the first output port unit 1011 are connected with the first delay control units 1021 in a one-to-one correspondence manner, each first delay control unit 1021 receives an input signal, each output port unit 1011 realizes delay opening under the control of the corresponding first delay control unit 1021, time-sharing operation is realized, transient current when the N output port units 1011 are opened can be reduced, and therefore the purpose of reducing electromagnetic interference is achieved. The delay time duration of each first delay control unit 1021 may be the same or different. It should be noted that the time-sharing operation of the N output port units 1011 means that the initial operating time nodes of the N output port units 1011 are different, that is, the N output port units 1011 are sequentially turned on according to different control delays and different durations, that is, the operating times of the N output port units 1011 may have an intersection, and it can be understood by those skilled in the art that, in other embodiments, after the N output port units 1011 are sequentially turned on according to different control delays and different durations as needed, the operating times may also have no intersection.

The above is an embodiment when the control module 102 includes the first latency control unit 1021, and an embodiment in which the control module 102 includes the second latency control unit 1022 is exemplarily described below.

Referring to fig. 6, the control module 102 includes N-1 second delay control units 1022, where the N-1 second delay control units 1022 receive the input signal and the control signal and are connected to N-1 output port units 1011 of the N output port units 1011 except for the first output port unit 1011 in a one-to-one correspondence manner, and the N-1 second delay control units 1022 control the N output port units 1011 to operate in a time-sharing manner according to the input signal and the control signal, respectively. It should be noted that the time-sharing operation of the N output port units 1011 means that the initial operating time nodes of the N output port units 1011 are different, that is, the N output port units 1011 are sequentially turned on according to different control delays and different durations, that is, the operating times of the N output port units 1011 may have an intersection, and it can be understood by those skilled in the art that, in other embodiments, after the N output port units 1011 are sequentially turned on according to different control delays and different durations as needed, the operating times may also have no intersection.

In the above embodiment, the N-1 second delay control units 1022 are independent from each other, each second delay control unit 1022 controls the on/off of the output port unit 1011 connected thereto, and the delay time duration of each second delay control unit 1022 may be the same or different. The N-1 second delay control units 1022 control N-1 output port units 1011 to be turned on at least partially in a time-sharing manner, so that the N output port units 1011 are turned on at least partially in a time-sharing manner, transient current when the N output port units 1011 are turned on is reduced, abrupt current is reduced, and abrupt voltage is reduced, thereby achieving the purpose of reducing electromagnetic interference.

It is understood that, referring to fig. 7, the second delay control unit 1022 may include a nor gate 10221, a first input terminal of the nor gate 10221 receives an input signal, a second input terminal of the nor gate 10221 receives a control signal, and an output terminal of the nor gate 10221 is connected to one output port unit of the N-1 output port units 1011. In this embodiment, the number of nor gates 10221 included in each second delay control unit 1022 is not particularly limited, and the number of nor gates 10221 in each second delay control unit 1022 may be the same or different. The nor gate 1022 circuit is used to control the N output port units 1011 to operate in a time-sharing manner. It should be noted that the time-sharing operation of the N output port units 1011 means that the nodes between the two start nodes are different, that is, the operation times of the two output port units 1011 may have an intersection or may not have an intersection.

The above is an embodiment when the control module 102 includes the second delay control unit 1022, and an embodiment in which the control module 102 includes the third delay control unit 1023 is exemplarily described below.

Referring to fig. 8, the control module 102 includes at least one third delay control unit 1023 (fig. 9 is only an example of the control module 102, and the application does not specifically limit the number of the third delay control units 1023, and the third delay control units 1023 may be one or multiple), and each third delay control unit 1023 is connected to the output port unit 1011, and controls the output port unit 1011 to operate in a time-sharing manner according to the input signal and the control signal.

Specifically, referring to fig. 9, the third delay control unit 1023 includes a switch element 10231 and a capacitor 10232, a first end of the switch element 10231 is connected to the output port unit 1011 and receives an input signal, a control end of the switch element 10231 receives a control signal, a second end of the switch element 10231 is connected to a first end of the capacitor 10232, and a second end of the capacitor 10232 is grounded. The switch element 10231 and the capacitor 10232 in each third delay control unit 1023 are paired, the number of the switch elements 10231 and the capacitors 10232 in each third delay control unit 1023 can be configured according to the practical application, and the access number of the capacitors 10232 can be controlled by the switch element 10231. In specific work, after the switch element 10231 is switched on, the capacitor 10232 starts to be charged, the charging degree of the capacitor 10232 corresponds to a certain electric potential, after the capacitor 10232 is fully charged, the electric level is reversed from initial 0 to 1, the output port units 1011 correspondingly connected are switched on, therefore, the on-time of each output port unit 1011 is controlled by controlling the charging time of the capacitor 10232, different output port units 1011 correspond to different on-times, the output port units 1011 operate at different delay durations, thereby realizing time-sharing work, the transient current size corresponding to the on-time is obviously reduced, and further reducing the influence of EMI. It should be noted that the time-sharing operation of the N output port units 1011 means that the initial operating time nodes of the N output port units 1011 are different, that is, the N output port units 1011 are sequentially turned on according to different control delays and different durations, that is, the operating times of the N output port units 1011 may have an intersection, and it can be understood by those skilled in the art that, in other embodiments, after the N output port units 1011 are sequentially turned on according to different control delays and different durations as needed, the operating times may also have no intersection.

In the above embodiment, the delay time may be set to several tens of ps (picoseconds) to several hundreds of ps, but is not limited thereto.

Referring to fig. 10, there are three IOs (output ports) between chip a and chip B, and parasitic inductance L and parasitic capacitance exist between different IOs, for example, parasitic capacitance C2 exists between IO1 and IO2, and parasitic capacitance C1 exists between IO2 and IO 3. When the output signal of IO2 is inverted by 0-1, I1 current is generated. Since the inductor current cannot change abruptly, the opposite current I2 will generate inside the inductor to block the current I1 from becoming larger, and the current I2 will flow out of the C1 to generate an overshoot voltage. The inductor current-voltage formula is: and U is equal to L (dI/dt).

According to the embodiment of the disclosure, aiming at the problem of overlarge instantaneous current caused by simultaneous opening of different IOs in the related art, the control module 102 is adopted to enable different output modules 101 to be opened in a time-sharing manner, so that the instantaneous current (fig. 11a) I in the related art is reduced to I/3 (fig. 11b), and the voltage is also reduced from U (fig. 12a) to U/3 (fig. 12 b). Because the instantaneous current in a short time is greatly reduced, but the driving capability of IO is hardly influenced, the parasitic inductance of a board level and a chip bonding line is marked as L, the overshoot voltage on the parasitic inductance caused by the sudden change of the current is also greatly reduced, and the overshoot problem of the output waveform can be greatly reduced and the EMI problem can be easily seen.

The disclosed embodiment also provides a chip, which includes the communication port circuit 100 in any one of the above embodiments, and the above chip can be used for chips of various devices, such as a power supply chip, a clock chip, and the like, but is not limited thereto.

An embodiment of the present disclosure further provides an electronic device, including: the above embodiments of the chip, the communication port circuit 100 and the chip in the embodiments of the present disclosure can be used in various electronic devices.

It is noted that although the various steps of the methods of the embodiments of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc. Additionally, it will also be readily appreciated that the steps may be performed synchronously or asynchronously, e.g., among multiple modules/processes/threads.

It should be noted that although several units and modules of the system for action execution are mentioned in the above detailed description, such division is not mandatory. Indeed, the features and functionality of two or more of the units or modules described above may be embodied in one unit or module, in accordance with implementations of embodiments of the present disclosure. Conversely, the features and functions of one unit or module described above may be further divided into embodiments by a plurality of units or modules. The components shown as units or modules may or may not be physical units, i.e. may be located in one place or may be distributed over a plurality of network elements. Some or all of the units or modules can be selected according to actual needs to achieve the purposes of the embodiments of the present disclosure. One of ordinary skill in the art can understand and implement it without inventive effort.

While the embodiments of the present disclosure have been described in connection with the drawings, the embodiments of the present disclosure are not limited to the specific embodiments described above, which are intended to be illustrative rather than limiting, and that those of ordinary skill in the art, in light of the teachings of the embodiments of the present disclosure, may make many forms without departing from the spirit of the embodiments of the present disclosure and the scope of the appended claims.

Claims (10)

1. A communication port circuit, comprising:

the output module is used for processing and outputting the input signal; and

and the control module is connected with the output module and is used for controlling the transient current change size of the output module during working.

2. The communication port circuit of claim 1, wherein the output module comprises N output port units, the N output port units being connected in parallel; wherein N is an integer of 2 or more.

3. The communication port circuit according to claim 2, wherein the control module comprises N-1 first delay control units, each of the first delay control units is connected to the remaining output port units except the first output port unit in a one-to-one correspondence manner, and each of the first delay control units controls the output port units to operate in a time-sharing manner.

4. The communication port circuit according to claim 3, wherein the first delay control unit comprises an even number of inverters connected in series, and wherein an input terminal of a first inverter receives an input signal and an output terminal of a last inverter is connected to the output port unit.

5. The communication port circuit according to claim 2, wherein the control module comprises N-1 second delay control units, the N-1 second delay control units receive an input signal and a control signal and are connected to N-1 output port units of the N output port units except for a first output port unit in a one-to-one correspondence manner, and the N-1 second delay control units control the N output port units to operate in a time-sharing manner according to the input signal and the control signal, respectively.

6. The communication port circuit of claim 5, wherein the second delay control unit comprises a NOR gate, a first input of the NOR gate receiving the input signal, a second input of the NOR gate receiving the control signal, and an output of the NOR gate being connected to one of the N-1 output port units.

7. The communication port circuit of claim 2, wherein the control module comprises at least one third delay control unit, each of the third delay control units is connected to the output port unit, and controls the N output port units to operate in a time-sharing manner according to the input signal and the control signal.

8. The communication port circuit of claim 7, wherein the third delay control unit comprises a switch element and a capacitor, a first terminal of the switch element is connected to the output port unit and receives the input signal, a control terminal of the switch element receives the control signal, a second terminal of the switch element is connected to the first terminal of the capacitor, and a second terminal of the capacitor is grounded.

9. A chip comprising the communication port circuit of any one of claims 1-8.

10. An electronic device, characterized in that the electronic device comprises: the chip of claim 9.

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