JPH10116213A - Oscillator monitoring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an oscillator monitoring circuit which can cope with not only stop of a clock pulse signal, but also abnormality of pulse cycles. SOLUTION: An inputted clock pulse signal 27 is branched in two, and one part is inputted to a clock pulse stop detecting circuit 4, which detects stop of the clock pulse 27 and outputs a clock pulse stop detection signal 9 to an OR gate 5. The other is inputted to a clock pulse cycle abnormality detecting circuit 6, which detects cycle abnormality of the clock pulse signal 27 and outputs a clock pulse cycle abnormality detection signal 11 to the OR gate 5. The OR gate 5 which has inputted the clock pulse stop detection signal 9 and clock pulse cycle abnormality detection signal 11 ORs the inputted signals and outputs a clock pulse abnormality detection signal 28 to a control part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an oscillator monitoring circuit, and more particularly to an oscillator monitoring circuit for generating a system clock of a computer system.

[0002]

2. Description of the Related Art Generally, a CPU of a computer system
Performs arithmetic processing, control processing, and the like based on a system clock pulse signal output from an oscillator. Therefore,
When an abnormality occurs in the clock pulse signal, that is, the oscillator, there is a serious effect on the computer system. Therefore, monitoring of the oscillator, that is, the system clock pulse signal, is particularly important in the self-diagnosis function of the computer system.

As shown in FIG. 2, a computer system comprises an oscillator 1 for generating a clock pulse signal 27, a CPU
A clock pulse signal output from the oscillator 1 which is composed of an oscillator monitoring circuit 3 which monitors the operation of the oscillator 1 and sends a clock pulse abnormality detection signal 28 to the control unit 2 27
Is input to the control unit 2 and the oscillator monitoring circuit 3.

In the control unit 2, a CPU executes arithmetic processing, various input / output processing, and the like based on the clock pulse signal 27. The oscillator monitoring circuit 3 monitors the supplied clock pulse signal 27, detects an abnormality when it occurs, and generates a clock pulse abnormality detection signal 28 as the control unit 2.
Alert. The control unit 1 generates a clock pulse abnormality detection signal 2
Upon receipt of the command 8, all the processes are immediately stopped, for example, and all the motors and the like are stopped.

The abnormality of the clock pulse signal 27, that is, the abnormality of the oscillator 1 is one of the stop of the clock pulse signal 27 and the other is an abnormality (change) of the cycle (frequency) of the clock pulse signal.

Japanese Patent Application Laid-Open No. 60-100235 discloses an example of a circuit for detecting a stop of a clock pulse signal. FIG. 6 shows an example of a clock pulse (signal) stop detection circuit described in Japanese Patent Application Laid-Open No. 60-100235.
Shown in In FIG. 6, the clock pulse stop detection circuit 4
Is an inverter 25 for inverting the phase of the clock pulse signal 27, a pull-up resistor 22-
1, 2, charging diode 19-1, 1-2, discharge resistor 20
-1,2, capacitors 21-1,2, clamp diodes 23-1,2, isolation resistor 24-1,
2 and a NOR gate 15.

The input clock pulse 27 is divided into two parts, one of which is used as it is, and the other is used with its phase inverted by an inverter 25. The operation of the charging / discharging circuit is such that each time the level of the clock pulse 27 repeats high / low, the charging / discharging of the capacitors 21-1 and 21-2 is repeated, and if any one of the capacitors 21-1 and 21-2 remains discharged. Continues, the NOR gate 15 detects and outputs the clock pulse stop detection signal 9. The capacitors 21-1 and 21-2 are charged through the diodes 19-1 and 19-1, and the discharge is performed through the resistors 20-1 and 20-2.

If the clock pulse signal 27 is normal and the pulse signal rises, the diodes 19-1 and 19-2
Of the capacitor 21-
The charging of the capacitors 1 and 2 is performed almost instantaneously, but when the pulse signal falls, the discharging is performed with a time constant determined by the resistance value of the resistors 20-1 and 20-1 and the capacitance value of the capacitors 21-1 and 21-2. Done.

Therefore, if the discharge time constant is selected to be appropriately long with respect to the frequency of the clock pulse signal 27, the capacitor 2
The charge potentials of 1-1 and 2 are always kept in the high level range, and the clock pulse stop detection signal 9 output from the NOR gate 26 is not generated.

When the clock pulse signal 27 stops,
For example, if the clock pulse signal 27 stops when the clock pulse signal 27 is at the low level, the charge potential of the capacitor 21-2 remains high, but the capacitor 21-1 continues to be discharged. A stop detection signal 9 is output.

Similarly, if the operation is stopped when the clock pulse signal 27 is at a high level, for example,
-1 remains high, but the capacitor 21-2
Continues to discharge, and after its charge potential goes low,
A clock pulse stop detection signal 9 is output.

[0012]

SUMMARY OF THE INVENTION FIG.
In the case of the oscillator monitoring circuit described in Japanese Patent Application Laid-Open No. 100235/1995, it is possible to cope when the clock pulse signal stops, but there remains a problem that it cannot cope when the pulse period of the clock pulse signal becomes abnormal.

An object of the present invention is to provide an oscillator monitoring circuit which can cope not only when the clock pulse signal stops but also when the pulse cycle becomes abnormal.

[0014]

According to the present invention, an oscillator monitoring circuit for an oscillator for generating a clock pulse signal includes a clock stop detecting means for detecting a stop of the clock pulse signal, and a period abnormality of the clock pulse signal. And a clock cycle abnormality detecting means.

The operation of the present invention is as follows. A clock pulse period abnormality detection circuit is provided in parallel with the clock pulse stop detection circuit.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment according to the present invention. In FIG. 1, an oscillator monitoring circuit (corresponding to the oscillator monitoring circuit 3 in FIG. 2 in the computer system shown in FIG. 2) includes a clock pulse signal 2
7, a clock pulse stop detection circuit 4 for detecting a stop of the clock pulse signal 27, a clock pulse cycle detection circuit 6 for detecting an abnormality in the clock cycle of the clock pulse signal 27, an output 9 of the clock pulse stop detection circuit 4, and a clock pulse cycle detection OR gate 5 for ORing with output 11 of circuit 6
Consists of

The operation of the embodiment of the present invention is as follows. The input clock pulse signal 27 is branched into two, one is input to the clock pulse stop detection circuit 4, and the stop of the clock pulse signal 27 is detected. Clock pulse stop detection signal 9
Is output to the OR gate 5. The other is input to the clock pulse period abnormality detection circuit 6, which detects the period abnormality of the clock pulse signal 27 and outputs the clock pulse period abnormality detection signal 1
1 is output to the OR gate 5. The OR gate 5 to which the clock pulse stop detection signal 9 and the clock pulse period abnormality detection signal 11 have been input takes the logical sum of the input signals and generates a clock pulse abnormality detection signal 28 as the control unit 2.
Output to

Next, a detailed embodiment of the clock pulse period abnormality detecting circuit 6 of the present invention is shown in FIG. 3 in the form of a block diagram.
In FIG. 3, the clock pulse cycle abnormality detection circuit 6
An F (Frequency) / V (Voltage) converter 7 for converting the frequency of the inputted clock pulse signal 27 into a voltage, reference voltage generators 10-1 and 10-2 for generating reference voltages 13 and 14, and F / Output 12 of V converter 7 and reference voltage 1
Comparing sections 8-1 and 8-2, comparing section 3-14, and comparing section 8-
OR gate 18 for taking the logical sum of outputs 16 and 17 of 1 and 2
And the clock pulse signal 27 from the oscillator 1
Is input to the F / V converter 7. The F / V converter 7 outputs an F / V conversion output signal 12 whose output voltage level changes in accordance with the cycle (frequency) of the input clock pulse signal 27.

Here, when the clock pulse signal 27 has a normal cycle, it is assumed that the F / V conversion output signal 12 outputs a voltage signal of, for example, V1. For example, the cycle of the clock pulse signal 27 is shortened. When the frequency increases, the voltage level of the F / V conversion output signal 12 increases, and when the period of the clock pulse signal 27 increases (the frequency decreases), the F / V conversion output signal 12 Suppose the voltage level drops.

Now, when the period of the clock pulse signal 27 is shortened and the control process of the control unit 2 is hindered, the voltage level of the F / V conversion output signal 12 is changed to V1 +
ΔV. The voltage level of the F / V conversion output signal 12 when the period of the clock pulse signal 27 becomes longer and hinders the control processing of the controller 2 is changed to V1
−ΔV.

Next, the operation of the clock pulse cycle abnormality detection circuit 6 when the cycle of the clock pulse signal 27 is shortened will be described with reference to the timing chart of FIG.

First, when the cycle of the clock pulse signal 27 is shortened and the voltage level of the F / V conversion output signal 12 is rising, a reference voltage generation set to output a fixed (reference) voltage of V1 + ΔV. The reference voltage 13 of the unit 10-1 and the F / V conversion output signal 12 are compared with the comparison unit 8-1.
When the F / V conversion output signal 12 exceeds the reference voltage 13, the comparison unit 8-1 outputs the output signal 16
Output to the R gate 18.

The operation of the clock pulse cycle abnormality detecting circuit 6 when the cycle of the clock pulse signal 27 becomes longer will be described with reference to the timing chart of FIG.

First, when the cycle of the clock pulse signal 27 becomes longer and the voltage level of the F / V conversion output signal 12 falls, a reference set to output a fixed (reference) voltage of V1-ΔV. The comparison unit 8-2 compares the reference voltage 14 of the voltage generation unit 10-2 with the F / V conversion output signal 12.
When the F / V conversion output signal 12 exceeds the reference voltage 14, the comparator 8-2 outputs the output signal 17
Output to the R gate 18.

The OR gate 18 performs a logical OR operation on the output signals 16 and 17 of the comparison units 8-1 and 2, and outputs the result to the OR gate 5 as the clock pulse period abnormality detection signal 11.

The clock pulse stop detection circuit 4 includes:
For example, the circuit shown in FIG. 6 can be used. 6, the clock pulse stop detection circuit 4 includes an inverter 25 for inverting the phase of the clock pulse signal 27, pull-up resistors 22-1 and 22 constituting a charge / discharge circuit, charging diodes 19-1 and 2, a discharge resistor. 20-1 and 20-2, capacitors 21-1 and 21 and clamp diodes 23-1 and 23-1
2. Isolation resistors 24-1 and 24-2 and NOR
It is constituted by a gate 15.

The input clock pulse 27 is divided into two parts, one of which is used as it is, and the other is used with its phase inverted by an inverter 25. The operation of the charging / discharging circuit is such that each time the level of the clock pulse 27 repeats high / low, the charging / discharging of the capacitors 21-1 and 21-2 is repeated, and if any one of the capacitors 21-1 and 21-2 remains discharged. Continues, the NOR gate 15 detects and outputs the clock pulse stop detection signal 9. The capacitors 21-1 and 21-2 are charged through the diodes 19-1 and 19-1, and the discharge is performed through the resistors 20-1 and 20-2.

When the clock pulse signal 27 is normal and the pulse signal rises, the diodes 19-1 and 19-2 are used.
Of the capacitor 21-
The charging of the capacitors 1 and 2 is performed almost instantaneously, but when the pulse signal falls, the discharging is performed with a time constant determined by the resistance value of the resistors 20-1 and 20-1 and the capacitance value of the capacitors 21-1 and 21-2. Done.

Therefore, if the discharge time constant is selected to be appropriately long with respect to the frequency of the clock pulse signal 27, the capacitor 2
The charge potentials of 1-1 and 2 are always kept in the high level range, and the clock pulse stop detection signal 9 output from the NOR gate 26 is not generated.

When the clock pulse signal 27 stops,
For example, if the clock pulse signal 27 stops when the clock pulse signal 27 is at the low level, the charge potential of the capacitor 21-2 remains high, but the capacitor 21-1 continues to be discharged. A stop detection signal 9 is output.

Similarly, if the operation is stopped when the clock pulse signal 27 is at a high level, for example,
-1 remains high, but the capacitor 21-2
Continues to discharge, and after its charge potential goes low,
A clock pulse stop detection signal 9 is output.

[0033]

As described above, according to the present invention, an oscillator monitoring circuit is provided in parallel with a conventional clock pulse stop detection circuit.
By adding a clock pulse period abnormality detection circuit, it is possible to detect the output stop of the clock pulse signal output from the oscillator and to detect the period abnormality of the clock pulse signal, and perform control processing based on the period of the clock pulse signal. In drive control and the like, there is an effect that danger such as runaway of the drive unit or the like can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a related computer system of the present invention.

FIG. 3 is a block diagram of a clock pulse period abnormality detection circuit.

FIG. 4 is an explanatory diagram of an operation of a clock pulse cycle abnormality detection circuit.

FIG. 5 is an explanatory diagram of an operation of the clock pulse period abnormality detection circuit.

FIG. 6 is a block diagram of a clock pulse stop detection circuit.

[Explanation of symbols]

 3 Oscillator monitoring circuit 4 Clock pulse stop detection circuit 5 OR gate 6 Clock pulse period abnormality detection circuit 9 Clock pulse stop detection signal 11 Clock pulse period abnormality detection signal 27 Clock pulse signal 28 Clock pulse abnormality detection signal

Claims (3)

[Claims] 1. A monitoring circuit for an oscillator for generating a clock pulse signal, comprising: a clock stop detection unit for detecting a stop of the clock pulse signal; and a clock period abnormality detection unit for detecting a period abnormality of the clock pulse signal. An oscillator monitoring circuit, comprising: 2. The clock cycle abnormality detecting means, wherein a cycle / voltage converting means for converting a cycle of the clock pulse signal into a clock cycle converted voltage, and a first reference voltage corresponding to an upper limit of the clock cycle converted voltage. Means to occur,
Means for generating a second reference voltage corresponding to a lower limit of the clock cycle conversion voltage, and a cycle abnormality of the clock pulse signal when the clock cycle conversion voltage exceeds the first or second reference voltage. 2. The oscillator monitoring circuit according to claim 1, further comprising voltage comparison means for detecting the occurrence. 3. The voltage comparison means for comparing the clock cycle converted voltage with the first reference voltage, and the voltage comparison means compares the clock cycle converted voltage with the second reference voltage. 3. The oscillator monitoring circuit according to claim 2, further comprising second comparing means for comparing, and means for calculating a logical sum of outputs of said first and second comparing means.