JP2581735B2 - Power failure detection device - Google Patents
Power failure detection deviceInfo
- Publication number
- JP2581735B2 JP2581735B2 JP63048234A JP4823488A JP2581735B2 JP 2581735 B2 JP2581735 B2 JP 2581735B2 JP 63048234 A JP63048234 A JP 63048234A JP 4823488 A JP4823488 A JP 4823488A JP 2581735 B2 JP2581735 B2 JP 2581735B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power failure
- output
- failure detection
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は交流電源の停電を検出する停電検出装置に
関し、特に位相急変並びに停電を高速且つ高精度に検出
可能な停電検出装置に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power failure detection device for detecting a power failure of an AC power supply, and more particularly to a power failure detection device capable of detecting a sudden phase change and a power failure at high speed and with high accuracy. .
第４図は例えば実用電子回路（４）P228〜231（CQ出
版株式会社昭和55年11月30日発行）に示された従来の停
電検出装置（20）を示す回路図であり、図において、
（1a）（1b）は検出する交流電圧信号を入力する入力端
子、（21a）〜（21d）はその交流電圧信号を整流するダ
イオード、（23）は抵抗器、（24）は定電圧ダイオー
ド、（25）はコンデンサ、（26）は抵抗器、（27）は電
圧比較器（コンパレータ）、（28）は可変抵抗で電源
（７）と共通電位とに接続され、中間端子はコンパレー
タ（27）のもう１つの入力端子に接続されており、（1
2）はコンパレータ（27）の出力端子である。FIG. 4 is a circuit diagram showing a conventional power failure detection device (20) shown in, for example, practical electronic circuits (4) P228 to 231 (CQ Publishing Co., Ltd. issued on November 30, 1980).
(1a) and (1b) are input terminals for inputting an AC voltage signal to be detected, (21a) to (21d) are diodes for rectifying the AC voltage signal, (23) is a resistor, (24) is a constant voltage diode, (25) is a capacitor, (26) is a resistor, (27) is a voltage comparator (comparator), (28) is a variable resistor connected to a power supply (7) and a common potential, and an intermediate terminal is a comparator (27) Connected to the other input terminal of (1
2) is an output terminal of the comparator (27).
次に動作について説明する。入力端子（1a）（1b）よ
り入力された交流電圧信号（第５図（ａ）に波形を示
す）はブリッジ接続されたダイオード（21a）〜（21d）
によって整流され（第５図（ｂ））、抵抗器（23）を通
して定電圧ダイオード（24）、コンデンサ（25）抵抗器
（26）に印加され、コンパレータ（27）のマイナス側入
力端子（点）に入力される。コンパレータ（27）のプ
ラス側入力端子には可変抵抗器（28）により設定される
基準電圧が入力される。点電圧は第５図（ｃ）の実線
に示すように、まず抵抗器（23）を通してコンデンサン
（25）が充電され電圧が上昇し、次に定電圧ダイオード
（24）の制限電圧＝Vzに制限され、やがて交流電圧の方
がVzよりも低くなると、コンデンサ（25）から抵抗（2
6）を通して放電するという動作を半周期ごとに繰り返
す。コンパレータ（27）はマイナス側入力端子の電圧が
プラス側入力端子の電圧よりも低くなると出力端子（1
2）に出力信号を出すように動作する。Next, the operation will be described. AC voltage signals (waveforms shown in FIG. 5 (a)) input from the input terminals (1a) and (1b) are bridge-connected diodes (21a) to (21d).
Is rectified (FIG. 5 (b)), applied to a constant voltage diode (24), a capacitor (25) and a resistor (26) through a resistor (23), and a negative input terminal (point) of a comparator (27). Is input to The reference voltage set by the variable resistor (28) is input to the positive input terminal of the comparator (27). As shown by the solid line in FIG. 5 (c), the point voltage is first charged by the capacitor (25) through the resistor (23), the voltage rises, and then the limit voltage of the constant voltage diode (24) becomes Vz. When the AC voltage becomes lower than Vz, the capacitor (25)
The operation of discharging through 6) is repeated every half cycle. When the voltage of the negative input terminal becomes lower than the voltage of the positive input terminal, the comparator (27) outputs the output terminal (1
2) Operate to output signal.
ここでＦ時点で入力の交流電圧信号が停電（電圧低
下）することを考えると、交流電圧信号が低下しコンデ
ンサ（25）の電荷が放電して点の電圧が可変抵抗器
（28）により設定された基準電圧よりも低くなると第５
図（ｄ）Ｇ時点でコンパレータ（27）が動作して出力端
子（12）に停電検出信号が出力される。Here, considering that the input AC voltage signal causes a power failure (voltage drop) at the time point F, the AC voltage signal drops, the electric charge of the capacitor (25) is discharged, and the voltage at the point is set by the variable resistor (28). When the voltage becomes lower than the reference voltage
(D) At time point G, the comparator (27) operates to output a power failure detection signal to the output terminal (12).
従来の停電検出装置は以上のように構成されているの
で、検出速度と検出精度はコンデンサ（25）のキャパシ
タンスと抵抗器（26）の抵抗値とで定まる放電時定数
と、基準電圧の設定値とに依存する。従って放電時定数
をあまり小さくすると検出回路での消費電力が大きくな
り、又通常状態での点の電圧リップルが大きくなって
検出精度が悪くなるので、実用的な検出速度は１〜２サ
イクルよりも速くできないという課題があった。Since the conventional power failure detection device is configured as described above, the detection speed and detection accuracy are determined by the discharge time constant determined by the capacitance of the capacitor (25) and the resistance of the resistor (26), and the set value of the reference voltage. And depends on. Therefore, if the discharge time constant is too small, the power consumption in the detection circuit increases, and the voltage ripple at the point in the normal state increases, and the detection accuracy deteriorates. Therefore, the practical detection speed is more than 1-2 cycles. There was a problem that we couldn't go faster.
この発明は上記のような課題を解消するためになされ
たもので、位相急変並びに停電を短時間でかつ精度良く
検出できる停電検出装置を得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a power failure detection device capable of detecting a sudden phase change and a power failure in a short time and with high accuracy.
この発明に係る停電検出装置は、交流入力電圧に同期
した同期信号を発生するPLL回路、同期信号に基づい
て、交流入力電圧に同期した所定電圧値の基準正弦波電
圧を発生する手段、入力電圧と基準正弦波電圧との差を
演算する手段、及び、差の電圧が所望の第１の設定値を
越えると第１の出力を発生する比較手段からなる第１の
停電検出手段と、入力電圧を整流しフィルタをかけた後
の電圧が所望の第２の設定値を越えると第２の出力を発
生する第２の停電検出手段と、第１の出力と第２の出力
との論理和を出力するORゲートとを備え、PLL回路に含
まれるフィルタの時定数を、交流入力電圧の停電直後の
位相を保持するのに十分な大きさに設定し、第１の設定
値を第２の設定値よりも低電圧で動作するように設定し
たものである。A power failure detection device according to the present invention includes a PLL circuit that generates a synchronization signal synchronized with an AC input voltage, a unit that generates a reference sine wave voltage having a predetermined voltage value synchronized with the AC input voltage based on the synchronization signal, First power failure detection means comprising: means for calculating a difference between the input voltage and a reference sine wave voltage; and a comparison means for generating a first output when the voltage of the difference exceeds a desired first set value. The second power failure detection means for generating a second output when the voltage after rectifying and filtering the signal exceeds a desired second set value, and the logical sum of the first output and the second output. An output OR gate, and the time constant of the filter included in the PLL circuit is set to a value large enough to maintain the phase immediately after the power failure of the AC input voltage, and the first setting value is set to the second setting It is set to operate at a voltage lower than the value.
この発明における交流入力電圧に同期した正弦波電圧
の基準信号は交流入力電圧と比較され、両者の差が所定
の値を越えた時に停電と判断される。The reference signal of the sine wave voltage synchronized with the AC input voltage in the present invention is compared with the AC input voltage, and when the difference between the two exceeds a predetermined value, it is determined that a power failure has occurred.
又、第１の停電検出回路においては、十分に大きなフ
ィルタ時定数を有するPLL回路で構成された同期回路か
らの同期信号に基づいて基準正弦波電圧が発生されるの
で、交流入力電圧を全波整流することなく直接検出する
ことができ、交流入力電圧の異常により位相が急変して
も正確且つ迅速に電圧異常を検出して機器を保護可能に
する。In the first power failure detection circuit, a reference sine wave voltage is generated based on a synchronization signal from a synchronization circuit constituted by a PLL circuit having a sufficiently large filter time constant. Direct detection can be performed without rectification, and even if the phase suddenly changes due to an AC input voltage abnormality, the voltage abnormality can be accurately and quickly detected to protect the device.
更に、電圧低下量の小さな停電が継続する場合には、
従来構成の第２の停電検出回路において、フィルタ時定
数後に高精度に検出する。Furthermore, when a power failure with a small voltage drop continues,
In the second power failure detection circuit having the conventional configuration, detection is performed with high accuracy after the filter time constant.
以下、この発明の一実施例を図について説明する。ま
ず、この発明の特徴的な構成要件の１つである第１の停
電検出回路について、第１図及び第３図を参照しながら
説明する。An embodiment of the present invention will be described below with reference to the drawings. First, a first power failure detection circuit, which is one of the characteristic components of the present invention, will be described with reference to FIG. 1 and FIG.
第１図（ａ）において、（１）は入力端子、（２）は
例えばフェーズロックドループ（PLL）回路により構成
される同期回路、（３）は同期回路（２）の出力が入力
され、入力交流電圧に同期しかつ所定の大きさを有する
正弦波電圧を発生する正弦波発生回路、 （４）は上記入力電圧と上記正弦波電圧との差の信号を
発生する減算器 （５）、（６）は電圧比較器（コンパレータ） （７）は制御電源（正極、電圧Vp）（８）は制御電源
（負極、電圧VN） （９）、（11）は実質的に同一の抵抗値R1を有する抵抗
器（10）は抵抗値R2に設定された可変抵抗器 （12）は電圧比較器（５）（６）のいずれかに出力があ
れば出力を発生する出力端子である。In FIG. 1 (a), (1) is an input terminal, (2) is a synchronous circuit constituted by, for example, a phase locked loop (PLL) circuit, and (3) is an output of the synchronous circuit (2). A sine wave generation circuit that generates a sine wave voltage having a predetermined magnitude in synchronization with the AC voltage; (4) a subtractor (5) that generates a signal representing a difference between the input voltage and the sine wave voltage; 6) is a voltage comparator (comparator) (7) is a control power supply (positive pole, voltage Vp) (8) is a control power supply (negative pole, voltage V N ) (9), (11) are substantially the same resistance R resistor having a 1 (10) a variable resistor which is set to a resistance value R 2 (12) is an output terminal for providing an output if the output to either voltage comparator (5) (6).
次に動作について説明する。 Next, the operation will be described.
入力端子（１）には交流入力電圧（第３図（ａ））が
印加される。同期回路（２）は例えば第１図（ｂ）に示
すようにフェーズロックドループ（PLL）回路を構成し
ており、入力信号と出力信号を1/2n（但しｎは整数）分
周器（204）で1/2nの周波数に分周した信号との位相を
比較する位相比較器（201）と、その出力に接続された
フィルタ（202）と、そのフィルタ出力電圧に応じた周
波数の信号を発振する電圧制御発振器（VCO）とにより
入力電圧の１、２、…2n倍の周波数のｎ個の同期信号を
発生する（第３図（ｂ））。この回路の応答速度はフィ
ルタ（202）の時定数により決定される。正弦波発生回
路（２）は例えば第１図（ｃ）に示すように正弦波パタ
ーンを記憶させた読出し専用メモリ（ROM）（301）とデ
ィジタル／アナログ（D/A）変換器、（302）とにより入
力電圧に同期して、電圧の一定な正弦波電圧を発生する
（第３図（ｃ））。減算器（４）は上記入力電圧と上記
正弦波電圧との差を演算して求める。ここで上記正弦波
電圧の大きさを入力電圧の定格値に設定しておけば上記
差の電圧は入力電圧の定格電圧からの変動分に相当す
る。An AC input voltage (FIG. 3A) is applied to the input terminal (1). The synchronizing circuit (2) forms a phase locked loop (PLL) circuit as shown in FIG. 1 (b), for example, and divides an input signal and an output signal by a 1 / 2n (where n is an integer) frequency divider (204). ), A phase comparator (201) that compares the phase with the signal divided to a frequency of 1 / 2n, a filter (202) connected to its output, and a signal having a frequency corresponding to the filter output voltage. .., 2 n times the input voltage is generated by the voltage-controlled oscillator (VCO) (FIG. 3 (b)). The response speed of this circuit is determined by the time constant of the filter (202). The sine wave generation circuit (2) includes, for example, a read-only memory (ROM) (301) storing a sine wave pattern and a digital / analog (D / A) converter as shown in FIG. Generates a sinusoidal voltage with a constant voltage in synchronization with the input voltage (FIG. 3 (c)). The subtractor (4) calculates and calculates a difference between the input voltage and the sine wave voltage. Here, if the magnitude of the sine wave voltage is set to the rated value of the input voltage, the voltage of the difference corresponds to a variation of the input voltage from the rated voltage.
コンパレータ（５）及び（６）はウィンドウコンパレ
ータ回路を構成しており、入力電圧Ｖが よりも大きい場合、又は よりも小さい場合に出力を発生する。（但しVp＝VNの場
合） 上記差の電圧は上記ウィンドウコンパレータ回路に入
力され、入力電圧の定格電圧からの変動が上記検出レベ
ル（Ｖ）を逸脱した場合に停電とみなして出力を発生す
る。The comparators (5) and (6) constitute a window comparator circuit, and the input voltage V Greater than, or Generates output if less than. (However, if the Vp = V N) voltage of the difference is input to the window comparator circuit, the variation from the rated voltage of the input voltage to generate the output is regarded as a power failure when deviating from the above detection level (V) .
即ち、第３図（ａ）の最初の１サイクルでは入力電圧
が定格電圧よりも小さかったり大きかったりしている
が、その差が所定の検出レベルよりも小さいので検出出
力（第３図（ｅ））は出ないが、Ｆ時点で停電が発生し
入力電圧が低下すると、上記正弦波電圧との差が上記検
出レベルを越え遅滞なく検出出力が発生する。That is, in the first cycle of FIG. 3A, the input voltage is smaller or larger than the rated voltage, but the difference is smaller than the predetermined detection level, so that the detected output (FIG. 3E) ) Does not occur, but if a power failure occurs at the point F and the input voltage decreases, the difference between the sine wave voltage and the sine wave voltage exceeds the detection level and a detection output is generated without delay.
この場合フィルタ（202）の時定数を十分長くしてお
けば、停電直後は停電前の入力電圧の位相が保持され
る。In this case, if the time constant of the filter (202) is made sufficiently long, the phase of the input voltage before the power failure is maintained immediately after the power failure.
又、同期回路（２）がPLL回路で構成されているの
で、交流入力電圧の異常を直接検出することができ、例
えば交流入力電圧の位相が急変しても、正確且つ迅速に
電圧異常を検出し、機器を保護することができる。In addition, since the synchronization circuit (2) is composed of a PLL circuit, it is possible to directly detect an abnormality in the AC input voltage, and, for example, even if the phase of the AC input voltage suddenly changes, accurately and quickly detect the voltage abnormality. And protect the equipment.
第２図はこの発明の一実施例を示す回路図であり、図
において、（20）は従来の停電検出回路で検出レベルは
精密に設定されており（例えば−10％）、（13）は図１
に関してで説明した停電検出回路で検出レベルは（20）
よりもやや広く設定されており（例えば−30％）（14）
は論理和（オア）ゲートで、（20）又は（13）のいずれ
か一方の出力が有る場合に出力を発生する。（13）の停
電検出回路は応答速度が速いが、電圧波形歪の影響によ
り誤動作する可能性がやや高いので、検出レベルを広げ
て不要な動作をしないようにする。一方（20）の検出回
路はフィルタがあり電圧波形歪の影響を受けにくいの
で、検出レベルを精密に設定する。FIG. 2 is a circuit diagram showing an embodiment of the present invention. In FIG. 2, (20) is a conventional power failure detection circuit, the detection level is set precisely (for example, -10%), and (13) is FIG.
The detection level is (20) in the power failure detection circuit described in
It is set slightly wider than (for example, -30%) (14)
Is a logical sum (OR) gate, which generates an output when there is an output of either (20) or (13). Although the power failure detection circuit of (13) has a high response speed, the possibility of malfunction due to the influence of voltage waveform distortion is somewhat high. Therefore, the detection level is increased to prevent unnecessary operation. On the other hand, since the detection circuit (20) has a filter and is not easily affected by voltage waveform distortion, the detection level is set precisely.
即ち、電圧低下量の小さな停電（電圧低下）が継続す
る場合は停電検出回路（20）で所定のフィルタ時定数後
に検出することができ、電圧低下量の大きな停電の場合
は停電検出回路（13）で高速に検出することができるの
で、両者の長所を生かした、高速で精度の高い停電検出
装置を得ることができる。That is, when a power failure (voltage drop) with a small voltage drop continues, the power failure detection circuit (20) can detect it after a predetermined filter time constant, and when a power failure with a large voltage drop occurs, the power failure detection circuit (13) ) Can be detected at high speed, so that a high-speed and high-precision power failure detection device utilizing the advantages of both can be obtained.
なお、上記実施例の構成をディジタル回路とソフトウ
エアで組んでもよく、上記実施例と同様の効果を奏す
る。Note that the configuration of the above-described embodiment may be combined with a digital circuit and software, and the same effects as in the above-described embodiment can be obtained.
以上のように、この発明によれば、交流入力電圧に同
期した同期信号を発生するPLL回路、同期信号に基づい
て、交流入力電圧に同期した所定電圧値の基準正弦波電
圧を発生する手段、入力電圧と基準正弦波電圧との差を
演算する手段、及び、差の電圧が所望の第１の設定値を
越えると第１の出力を発生する比較手段からなる第１の
停電検出手段と、入力電圧を整流しフィルタをかけた後
の電圧が所望の第２の設定値を越えると第２の出力を発
生する第２の停電検出手段と、第１の出力と第２の出力
との論理和を出力するORゲートとを備え、PLL回路に含
まれるフィルタの時定数を、交流入力電圧の停電直後の
位相を保持するのに十分な大きさに設定し、第１の設定
値を第２の設定値よりも低電圧で動作するように設定し
たので、PLL回路を含む第１の停電検出回路により、位
相急変時並びに電圧低下量の大きな停電を高速且つ高精
度に検出し、平均値を用いた第２の停電検出回路によ
り、電圧低下量の小さな停電をフィルタ時定数後に検出
することができ、第１及び第２の停電検出回路の各長所
を生かした高速且つ高精度の停電検出装置が得られる効
果がある。As described above, according to the present invention, a PLL circuit that generates a synchronization signal synchronized with an AC input voltage, a unit that generates a reference sine wave voltage of a predetermined voltage value synchronized with the AC input voltage based on the synchronization signal, First power failure detection means including means for calculating a difference between the input voltage and the reference sine wave voltage, and comparison means for generating a first output when the voltage of the difference exceeds a desired first set value; A second power failure detecting means for generating a second output when a voltage after rectifying and filtering the input voltage exceeds a desired second set value, and a logic between the first output and the second output An OR gate that outputs a sum, the time constant of a filter included in the PLL circuit is set to a value large enough to maintain the phase of the AC input voltage immediately after the power failure, and the first set value is set to the second It is set to operate at a voltage lower than the set value of The power outage detection circuit detects high-speed and high-precision power outages at the time of sudden phase change and large voltage drop, and the power failure with small voltage drop is detected after the filter time constant by the second power failure detection circuit using the average value. And a high-speed and high-precision power failure detection device utilizing the advantages of the first and second power failure detection circuits can be obtained.
第１図（ａ）はこの発明の一実施例に用いられる停電検
出装置を示す回路図、第１図ｂ）は第１図（ａ）の同期
回路の回路図、第１図（ｃ）は第１図（ａ）の正弦波発
生回路の回路図、第２図はこの発明の一実施例を示す停
電検出装置の回路図、第３図はこの発明の一実施例の波
形図、第４図は従来の停電検出装置を示す回路図、第５
図は第４図の動作を示す波形図である。 （１）は入力端子、（２）は同期回路、（３）は正弦波
発生回路、（４）は減算器、（５）、（６）は電圧比較
器（コンパレータ）、（７）は制御電源（正極）、
（８）は制御電源（負極）、（９）、（11）は抵抗器、
（10）は可変抵抗器、（12）は出力端子、（201）は位
相比較器、（202）はフィルタ、（202）は電圧制御発振
器、（204）は1/2n分周器、（301）は読出し専用メモリ
（ROM）、（302）はディジタル／アナログ（D/A）変換
器、（13）は本発明による停電検出回路、（14）は論理
和（オア）ゲート、（20）は従来の停電検出回路、（21
a）〜（21d）はダイオード、（23）は抵抗器、（24）は
定電圧ダイオード、（25）はコンデンサ、（26）は抵抗
器、（27）は電圧比較器、（28）は可変抵抗器 なお、図中、同一符号は同一、又は相当部分を示す。1 (a) is a circuit diagram showing a power failure detection device used in one embodiment of the present invention, FIG. 1 (b) is a circuit diagram of a synchronous circuit of FIG. 1 (a), and FIG. 1 (c) is FIG. 1 (a) is a circuit diagram of a sine wave generating circuit, FIG. 2 is a circuit diagram of a power failure detection device showing one embodiment of the present invention, FIG. 3 is a waveform diagram of one embodiment of the present invention, FIG. FIG. 5 is a circuit diagram showing a conventional power failure detection device, and FIG.
The figure is a waveform chart showing the operation of FIG. (1) is an input terminal, (2) is a synchronous circuit, (3) is a sine wave generation circuit, (4) is a subtractor, (5) and (6) are voltage comparators, and (7) is control. Power supply (positive electrode),
(8) is a control power supply (negative electrode), (9) and (11) are resistors,
(10) is a variable resistor, (12) is an output terminal, (201) is a phase comparator, (202) is a filter, (202) is a voltage controlled oscillator, (204) is a 1 / 2n frequency divider, and (301) ) Is a read only memory (ROM), (302) is a digital / analog (D / A) converter, (13) is a power failure detection circuit according to the present invention, (14) is a logical sum (OR) gate, and (20) is Conventional power failure detection circuit, (21
a) to (21d) are diodes, (23) is a resistor, (24) is a constant voltage diode, (25) is a capacitor, (26) is a resistor, (27) is a voltage comparator, and (28) is variable. Resistor In the drawings, the same reference numerals indicate the same or corresponding parts.
フロントページの続き (56)参考文献 特開 昭59−206773（ＪＰ，Ａ) 特開 昭54−119646（ＪＰ，Ａ) 特開 昭58−33923（ＪＰ，Ａ) 実開 昭60−181677（ＪＰ，Ｕ) 実開 昭57−45244（ＪＰ，Ｕ) 実開 昭59−179383（ＪＰ，Ｕ)Continuation of the front page (56) References JP-A-59-206773 (JP, A) JP-A-54-119646 (JP, A) JP-A-58-33923 (JP, A) , U) Japanese Utility Model Showa 57-45244 (JP, U) Japanese Utility Model Showa 59-179383 (JP, U)
Claims (1)
るPLL回路、上記同期信号に基づいて、上記交流入力電
圧に同期した所定電圧値の基準正弦波電圧を発生する手
段、上記入力電圧と上記基準正弦波電圧との差を演算す
る手段、及び、上記差の電圧が所望の第１の設定値を越
えると第１の出力を発生する比較手段からなる第１の停
電検出手段と、 上記入力電圧を整流しフィルタをかけた後の電圧が所望
の第２の設定値を越えると第２の出力を発生する第２の
停電検出手段と、 上記第１の出力と上記第２の出力との論理和を出力する
ORゲートと を備え、 上記PLL回路に含まれるフィルタの時定数を、上記交流
入力電圧の停電直後の位相を保持するのに十分な大きさ
に設定し、 上記第１の設定値を上記第２の設定値よりも低電圧で動
作するように設定したことを特徴とする停電検出装置。1. A PLL circuit for generating a synchronization signal synchronized with an AC input voltage, means for generating a reference sine wave voltage of a predetermined voltage value synchronized with the AC input voltage based on the synchronization signal, A first power failure detecting means comprising a means for calculating a difference from the reference sine wave voltage, and a comparing means for generating a first output when the voltage of the difference exceeds a desired first set value; A second power failure detecting means for generating a second output when the voltage after rectifying and filtering the input voltage exceeds a desired second set value; and Outputs the logical sum of
An OR gate; and a time constant of a filter included in the PLL circuit is set to be large enough to maintain a phase immediately after a power failure of the AC input voltage, and the first set value is set to the second A power failure detection device set to operate at a voltage lower than the set value of the power failure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63048234A JP2581735B2 (en) | 1988-02-29 | 1988-02-29 | Power failure detection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63048234A JP2581735B2 (en) | 1988-02-29 | 1988-02-29 | Power failure detection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01221677A JPH01221677A (en) | 1989-09-05 |
| JP2581735B2 true JP2581735B2 (en) | 1997-02-12 |
Family
ID=12797751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63048234A Expired - Lifetime JP2581735B2 (en) | 1988-02-29 | 1988-02-29 | Power failure detection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2581735B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2539668B2 (en) * | 1988-06-30 | 1996-10-02 | 山洋電気株式会社 | Sine wave generation circuit using digital PLL |
| JP2575923B2 (en) * | 1990-05-10 | 1997-01-29 | 三菱重工業株式会社 | Control method of multi-room air conditioner |
| JPH0478572U (en) * | 1990-11-16 | 1992-07-08 | ||
| JPH09297156A (en) * | 1996-05-07 | 1997-11-18 | Shindengen Electric Mfg Co Ltd | Instantaneous service interruption detecting circuit for commercial power supply |
| US7091676B2 (en) * | 2001-03-15 | 2006-08-15 | The Bodine Company, Inc. | Arc maintenance device for high density discharge lamps including an adaptive wave form monitor |
| JP4085853B2 (en) * | 2003-03-18 | 2008-05-14 | 松下電器産業株式会社 | Electronics |
| JP4191582B2 (en) * | 2003-12-05 | 2008-12-03 | 三菱電機株式会社 | AC voltage drop detection device |
| JP6855818B2 (en) * | 2016-02-03 | 2021-04-07 | 富士電機株式会社 | Voltage abnormality detection device, program, voltage abnormality detection method |
| WO2020022255A1 (en) * | 2018-07-23 | 2020-01-30 | 日本電気株式会社 | Measuring device, and voltage generating method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54119646A (en) * | 1978-03-08 | 1979-09-17 | Fuji Electric Co Ltd | Ac voltage abnormality detector |
| JPS59206773A (en) * | 1983-05-11 | 1984-11-22 | Tohoku Oki Denki Kk | Circuit for detecting abnormality of ac power supply |
-
1988
- 1988-02-29 JP JP63048234A patent/JP2581735B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01221677A (en) | 1989-09-05 |
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