JPH06169301A - Pattern detecting circuit - Google Patents

Abstract

PURPOSE:To provide a pattern detecting circuit which is free from the inversion of patterns and needs no multiframe length timing pulse in a simple constitution by applying a P pattern detecting circuit, a PN pattern detecting circuit, and a multiframe detecting circuit. CONSTITUTION:A check signal 11 consists of a pattern P and its inverted pattern PN. A P pattern detecting circuit 12 detects only the pattern P out of the input signal 11, and a PN pattern detecting circuit 13 detects only the PN pattern out of the signal 11 respectively. Both circuits 12 and 13 detect the coincidence or discordance of patterns respectively. Based on these detecting results, an exclusive OR circuit 14 decides the coincidence or discordance of patterns. The detecting result of the circuit 13 is supplied to a multiframe detecting circuit 17 which detects the coincidence/discordance sequence in each pattern detecting cycle of both patterns P and PN respectively. Thus the pattern coincidence information 19 is acquired as the output of an OR circuit 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern detection circuit in a digital circuit.

[0002]

2. Description of the Related Art Generally, pattern detection circuits are used in digital circuits to check the normality of data paths through which data is transmitted. When checking the normality of the data path, the sending side creates a check signal with a check pattern inserted in the open time slot of the data in the section where the data path is checked, and the receiving side uses the pattern detection circuit to send on the sending side. The inserted check pattern is detected, and the normality of the data path is checked by checking whether or not the check pattern matches the predetermined pattern.

The pattern used for such pattern detection is composed of a multi-frame of a fixed pattern P and its inverted pattern PN in order to detect the all 1's or all 0's of the data path. It is normal. FIG. 2 shows a configuration diagram of a conventional pattern detection circuit. The pattern detection circuit 22 to which the check signal 21 is input, the timing generation circuit 24 that generates timing by receiving the timing pulse 23 having the multiframe length, and the check signal 21 configured by the multiframe of the pattern P and the pattern PN The phase is detected by the timing pulse from the timing generation circuit 24-1,
It is composed of a pattern P or a pattern PN check pattern generation circuit 25 which is used by the two circuits to generate a multi-frame timing signal and which is detected by the pattern detection circuit 22 by the signal. The pattern detection result is obtained as pattern matching information 26 by the output of the pattern detection circuit 22.

[0004]

However, in the conventional circuit configuration shown in FIG. 2, the multi-frame length timing pulse 23 is received from the outside and the check pattern generating circuit 25 is received.
Since the P pattern is generated by -1 and the PN pattern is generated by 25-2, the detection pattern is selected by 25-3, and the pattern is detected by the pattern detection circuit 22, the circuit becomes complicated and the multi-frame length becomes longer. There was the problem of requiring timing pulses.

The present invention has been made in order to solve the problems that the circuit structure becomes complicated and the problems of the conventional pattern detection circuit that requires timing pulses of multiframe length. An object of the present invention is to provide a pattern detection circuit that does not require pattern inversion and does not require multiframe length timing pulses and has a simplified circuit configuration.

[0006]

A pattern detecting circuit of the present invention is a P pattern detecting circuit for detecting only a pattern P signal in a check signal, and a PN pattern detecting circuit for detecting only a pattern PN signal in the check signal. When,
A multi-frame detection circuit is provided for inputting match / mismatch information from either the P pattern detection circuit or the PN pattern detection circuit and detecting the order of match / mismatch.

[0007]

In the present invention, the normality of the pattern is confirmed by the disagreement between the detection results of the P pattern detection circuit and the PN pattern detection circuit, and the normality of the multiframe is confirmed by the order of the detection results of the multiframe detection circuit. Pattern detection is performed as information.

[0008]

1 is a block diagram of a pattern detection circuit showing an embodiment of the present invention. Pattern P and its inverted pattern P
The check signal 11 consisting of N and P respectively includes a P pattern detection circuit 12 for detecting only the pattern P signal and a pattern P.
It is input to the PN pattern detection circuit 13 which detects only the N signal. The detection output is the exclusive NOR circuit 14
Is connected to one input of the OR circuit 18. In the present invention, the timing pulse 15 does not require a multi-frame length timing pulse as in the conventional case, and a normal timing pulse is input to the timing generation circuit 16.

The timing signal from the timing generation circuit 16 is supplied to the P pattern detection circuit 12, the PN pattern detection circuit 13 and the multi-frame detection circuit 17, respectively. The check signals are detected by the detection circuits 12, 13, and 17 through this timing signal. The detection output of the multi-frame detection circuit 17 is connected to the other input of the OR circuit 18. As a result, the pattern matching information 19 is obtained as the output of the OR circuit 18.

Next, the operation of the pattern detection circuit shown in FIG. 1 will be described. First, in the input check signal 11, only the pattern P is detected by the P pattern detection circuit 12. Further, only the pattern PN is detected by the PN pattern detection circuit 13 to detect whether they match or not. The detection result obtained in this way is judged by the exclusive OR circuit 14 as coincidence or non-coincidence. If the patterns are normal, the results detected by the P pattern detection circuit 12 and the PN pattern detection circuit 13 will always be inconsistent in either circuit, and will be in agreement in the other circuit. Will be output.

On the other hand, the match / mismatch information from either the P pattern detection circuit 12 or the PN pattern detection circuit 13 is input to the multi-frame detection circuit 17. In the embodiment shown in FIG. 1, the PN pattern detection circuit 13
The detection result from is input to the multi-frame detection circuit 17. Matching and non-matching are detected for each arrangement of the P pattern and PN pattern in the multi-frame. Therefore, the multi-frame detecting circuit 17 detects the order of matching and non-matching for each pattern detection cycle of the pattern P and the pattern PN. In this way, the P pattern detection circuit 12 and the PN
The circuit configuration is simplified by providing the pattern detection circuit 13 and the pattern detection circuit 13 separately, and checking the normality of the pattern by detecting the mismatch between the circuits. Further, since it is not necessary to receive the timing pulse having the length of the multi-frame, the P pattern detection circuit 12 or the PN pattern detection circuit 1
The pattern can be easily detected by detecting the coincidence or non-coincidence order of one of the detection circuits of No. 3 for each detection cycle.

[0012]

As described above in detail based on the embodiments, the following effects can be expected in the present invention.

Since the detection circuit dedicated to the P pattern and the PN pattern is provided, a signal for separately decoding the phase of the P pattern and the phase of the PN pattern is unnecessary, so that the circuit is simplified and the detection of the P pattern and the detection of the PN pattern are performed. Therefore, it is not necessary to invert the detection circuit to detect.

Since it is possible to confirm in multiple frames by detecting the order of coincidence or non-coincidence of the detection circuit of either the P pattern or the PN pattern without receiving the timing pulse having the length of the multiframe, the multiframe can be confirmed. No longer need timing pulses.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a pattern detection circuit showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional pattern detection circuit.

[Explanation of symbols]

 11 check signal 12 P pattern detection circuit 13 PN pattern detection circuit 14 exclusive OR circuit 15 timing pulse 16 timing generation circuit 17 multi-frame detection circuit 18 OR circuit 19 pattern matching information

Claims (1)

[Claims] 1. A pattern detection circuit for inputting a check signal composed of a pattern P inserted in a data open time slot and its inverted pattern PN and detecting the normality of a data path as pattern matching information. One of a P pattern detection circuit that detects only the pattern P signal from the inside, a PN pattern detection circuit that detects only the pattern PN signal from the check signal, and either the P pattern detection circuit or the PN pattern detection circuit And a multi-frame detection circuit for detecting the order of coincidence and non-coincidence are provided, and the normality of the pattern is confirmed by the non-coincidence of the detection results of the P pattern detection circuit and the PN pattern detection circuit. ,
A pattern detection circuit, wherein normality of a multi-frame is confirmed by the order of detection results of the multi-frame detection circuit to obtain the pattern matching information.