JPH06168099A - Addition circuit - Google Patents

Abstract

PURPOSE:To execute high-speed addition processing with a small circuit scale and at low cost and low power consumption. CONSTITUTION:Repeating data and former data read out of a dual port memory 3 are inputted to an adder 2, and these are summed by a prescribed bit unit, and are written again in the dual port memory 3. Since the write-in of the dual port memory 3 can be executed independently of its read-out, the data after the addition processing can be written again while executing the addition processing of the data in the course of the read-out by the bit unit if the data is shifted by the prescribed number of bits, and overall addition processing speed can be made high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adder circuit, and more particularly to an adder circuit capable of high-speed addition processing of an input signal repeated a plurality of times such as scan data.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional adder circuit. The adder circuit 30 is of a pipeline type, and a latch / divider circuit 32 is provided after the A / D converter 31, and n adders 33a to 33d are provided in parallel after the latch / divider circuit 32. It is provided. The outputs of the adders 33a to 33d are fed back to the input side, and the outputs of the adders 33a to 33d are stored in the memory 3 respectively.
4a to 34d.

FIG. 5 is a timing chart of the adder circuit. As shown in FIG. 5A, the data after A / D conversion by the A / D converter 31 is further processed by the latch / divider circuit 32. The adders 33a to 33d are sequentially switched and input in units of a predetermined processing bit, for example, every 8 bits. The adders 33a to 33d read the stored previous data from the memories 34a to 34d (period R in the figure) by the control of the processing unit (not shown), add the present data to this ((Σ in the figure), and store the data again. Write in 34a to 34d (W in the figure).

With the above structure, the memories 34a to 34d,
High-speed sampling of 1 / n of the operation speed unique to the adders 33a to 33d can be performed, and high-speed sampling is possible without using an adder and a memory that operate at high speed.

Here, the data is the scanned data, and the data added by the adders 33a to 33d is divided by the number of additions in a processing circuit in the subsequent stage, not shown, as an added value for each scan, and an average value. If it is configured to obtain, it is possible to obtain the average value of the added values of a plurality of times. The adder circuit having the above configuration is used, for example, when averaging the frequency sweep data a plurality of times in the spectrum analyzer and averaging the received data of the backscattered light a plurality of times in the optical pulse tester. .

[0006]

However, in the conventional adder circuit, since the read time and write time of the memory must be taken into consideration when determining the sampling period, a memory that operates at high speed for that time must be used. The cost is high and the power consumption is high. Further, the above-mentioned pipeline type addition circuit 3
In the case of 0, since a plurality of adders 33a to 33d and memories 34a to 34d are used, the circuit scale becomes large, the cost is high, the power consumption is large, and the installation space is required.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an adder circuit having a small circuit scale, low cost, and low power consumption and capable of high-speed sampling.

[0008]

In order to achieve the above object, the adder circuit of the present invention is configured such that data is repeatedly input in a predetermined bit unit for each predetermined data length, and the predetermined bit is added together with the data of the other input terminal. An adder 2 for adding and outputting for each unit, and data of a predetermined data length output from the adder is freely writable from the one input terminal 3a for each of the predetermined bits and is arbitrarily output from the other output terminal 3b. The dual port memory 3 is configured to be able to read the data stored at every timing of each predetermined bit and to be supplied to the other input terminal of the adder.

[0009]

According to the above structure, the data A / D converted by the A / D converter 1 is repeatedly input to the adder 2 and added together with the data read from the dual port memory 3 for each predetermined bit unit. After the addition processing is performed by the device 2, it can be written again in the dual port memory 3 in the same predetermined bit unit. Therefore, the data being read from the dual port memory 3 can be added and simultaneously rewritten to the dual port memory 3 in a predetermined bit unit, so that the addition processing speed can be increased with a simple configuration.

[0010]

1 is a block diagram showing an adder circuit according to the present invention. The analog data is repeatedly input to the A / D converter 1, and the corresponding digital data is input to the clock signal CL.
It is repeatedly output at a predetermined cycle based on K. The adder 2 is
It has two input terminals 2a and 2b, each of which inputs data in a predetermined bit unit (for example, 16 bits). The input terminal 2a side is connected to the output of the A / D converter 1, and the input terminal 2a
The output terminal 3 of the dual port memory 3 described later on the b side
b is connected. The adder 2 has both of these input terminals 2a,
The input data of 2b are added and output from the output terminal 2c.

The dual port memory 3 is a memory element having a FIFO structure having a data input terminal 3a and a data output terminal 3b. The data fetch timing of the input terminal 3a is based on the write enable signal WE and the write reset signal WRST, while the data read timing of the output terminal 3b is based on the read enable signal RE and the read reset signal RRST. The dual port memory 3 can perform a write operation or a read operation according to the write enable signal WE and the read enable signal RE input at arbitrary timings.

The timing generator 4 supplies the above-mentioned CLK signal to each section, and at the same time, WRST is applied to the write address counter 3d of the dual port memory 3 shown in FIG.
Signal and WE signal are output, and read address counter 3e
In response, the RRST and RE signals are output at different timings from the WRST and WE signals. On the other hand, the CPU 5 reads out the added data by using the WRST signal and the WE signal at the timing different from that at the time of the addition, independently of the RRST signal and the R signal.
The E signal and the RCLK signal are output to the read address counter 3e via the timing generator 4.

As a result, the write address counter 3d is supplied with the WE signal, the write address counter is initialized by the WRST signal, and then the address is sequentially incremented based on the CLK signal. Are automatically added and written to the memory array 3f.

Similarly, when the RRST signal and the RE signal are supplied also to the read address counter 3e, CLK
The data of the addresses sequentially updated based on the signal is read from the memory array 3f. Further, in the write operation and the read operation in the present embodiment, it is described that the write clock WCLK and the read clock RCLK are generated by the timing generator 4 and these are synchronized with each other. (asynchronous)
You can also do this.

The adder circuit configured as described above operates at the timing shown in the timing chart of FIG. Figure 3 (a) shows
Read clock R generated by the timing generator 4
CLK and a write clock WCLK. A /
As shown in FIG. 2B, the D converter 1 outputs the input data by a predetermined data length based on WCLK, sequentially by A for each predetermined bit unit.
/ D conversion, and output to the input terminal 2a of the adder 2.

The previous data read from the dual port memory 3 is input to the other input terminal 2b of the adder 2. That is, the RE signal output from the timing generator 4 shown in FIG. 6C is synchronized with RCLK from the dual port memory 3 as shown in FIG. Read out.

The adder 2 has both of these input terminals 2a, 2
Both data supplied to b are added and output in synchronization with CLK (WCLK). The data after this addition is shown in FIG.
By the WE signal of the timing generator 4 shown in (4), data is rewritten in the dual port memory 3 at the cycle of WCLK as shown in FIG. At this time, data is being read from the dual port memory 3, and WRST
No data is supplied, and data is written to an address different from the data being read. In this way, in the dual port memory 3, an address for a minimum of 2 data lengths is reserved and used cyclically.

By repeating the above operation for each data length, each data is sequentially added and the dual port memory 3 is added.
Memorized in. Then, the CPU 5 performs the addition process a predetermined number of times and then uses the WE signal to output the dual port memory 3
The data can be read from and output to the outside.

The first addition operation by the adder 2 is performed after the data from the A / D converter 1 is once written in the dual port memory 3 and then read out, as shown in FIG. As shown in, A / D converters 1 to 2
The addition process starts when the second data is supplied,
After that, the addition processing is sequentially performed. Further, according to the above-described embodiment, since the addition process can be performed immediately after being read from the dual port memory 3 in units of a predetermined bit and can be immediately written again in parallel, the addition process of the entire system can be speeded up. You can

In the above embodiment, the data having a predetermined data length is repeatedly and sequentially added. However, the application of this adding circuit to an optical pulse tester will be described as an example. The optical pulse tester measures the optical loss of the measured fiber, the position of a failure point, etc. from the received light level of the returning condition (backscattered light) of the light by injecting light into the measured fiber at a predetermined repetition period. Since the backscattered light returning from the fiber to be measured contains noise and the like, the data of the predetermined length are added and subjected to the averaging process.

In this optical pulse tester, the A / D converter 1
An O / E converter that receives the backscattered light and converts it into an electric signal corresponding to the received light level is provided in the front stage. Also, CPU5
Is the average value (averaging) of the data obtained by dividing the data that has been added multiple times in the adder circuit by the number of additions.
Perform processing.

As shown in FIG. 3 (g), in the O / E converter, backscattered light having a predetermined attenuation characteristic is received at each incident timing. By using this backscattered light as a predetermined data length, A / D conversion is performed by the A / D converter 1 for each of a plurality of points, and the addition processing is performed,
The CPU 5 can obtain the data after the addition of a plurality of times,
The CPU 5 divides this data by the number of additions to obtain the average value of the data, and can obtain a stable measurement value of the backscattered light.

By applying the adder circuit to the optical pulse tester as described above, high-speed add processing can be performed with a simple structure, and the cost can be reduced.

[0024]

According to the present invention, the data for addition processing is read from the dual port memory, and rewriting is possible if the time required for the addition processing after this read operation has passed by a predetermined bit unit. Therefore, high-speed addition processing can be performed with a simple configuration.
In particular, the number of adders and memories can be configured with the minimum number as compared with the conventional pipeline type adder circuit, an equivalent processing speed can be obtained, and further power saving, space saving, and low cost can be achieved. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an adder circuit of the present invention.

FIG. 2 is an internal configuration diagram of a dual port memory of the adder circuit.

FIG. 3 is a timing chart of the adder circuit.

FIG. 4 is a block diagram showing an adder circuit according to a conventional pipeline method.

FIG. 5 is a timing chart of the conventional adder circuit.

[Explanation of symbols]

1 ... A / D converter, 2 ... Adder, 3 ... Dual port memory, 3a ... Input terminal, 3b ... Output terminal, 4 ... Timing generator, 5 ... CPU.

Claims (1)

[Claims] 1. An adder (2) for repeatedly inputting data in a predetermined bit unit for each predetermined data length, adding together with the data of the other input terminal for each predetermined bit unit, and outputting the same. Data having a predetermined data length output from one of the input terminals (3a) can be freely written for each predetermined bit, and data stored from the other output terminal (3b) at any timing can be written for each predetermined bit. And a dual port memory (3) configured to be readable and supplying the other input terminal of the adder.