GB2448066A

GB2448066A - RAM circuit with accumulator

Info

Publication number: GB2448066A
Application number: GB0805507A
Authority: GB
Inventors: John Patrick Warrington
Original assignee: Calrec Audio Ltd
Current assignee: Calrec Audio Ltd
Priority date: 2007-03-26
Filing date: 2008-03-26
Publication date: 2008-10-01
Anticipated expiration: 2028-03-26
Also published as: GB0705733D0; GB2448066B; WO2008117042A2; WO2008117042A3; GB0805507D0

Abstract

A dual port RAM 10 is connected to an addition circuit 18 such that when a data value is written to the RAM, the current value at the address to be written is retrieved, added to the value to be written and the total value is stored in the dual port RAM. A reset signal 20 causes the circuit to write the new value to the addressed location without adding the current value. A second dual port RAM 12 may be used to store a duplicate copy of the value to allow one value to be read while another is being written. The reset signal may be used to select which portion of the dual port RAM is currently being read or written.

Description

RAM CIRCUIT

The present invention relates to a system of digital signal processing in which a large number of signals are processed and combined to create a variety of outputs which are used in applications such as television and radio broadcasting, music recording, sound reinforcement and public address system, theatre, and film post production. More specifically the invention relates to a sLLuuue and method for the down-mixing of digital signals in such systems in which a large number of related signals are reduced into a smaller number of signals in a controlled manner, for example the production of a stereo (two channel) signal from a 5.1 surround (6 channel signal), or stereo functions which include width, left to both and right to both, in which the resulting signal may require contributions from several input signals.

This type of digital signal processing finds a particular application in large-scale digital mixing consoles. Typically, digital processing equipment makes use of commercially available specialised digital processing integrated circuits (DSP devices) and/or microprocessors to sum together the digital audio signal streams. This requires the creation of expensive specialist software in order to control the operation.

The downmixing of signals referred to above is essentially a process of adding together selected ones of the signals in chosen ratios. Therefore, an important part of the equipment for carrying this out is an addition or accumulation unit. In the current equipment, in order to perform an accumulation, the partial sum is retrieved from a memory and brought into the processors arithmetic unit, added to a new input and the result stored in the memory. This has the disadvantage of being a multistage operation arid as such is time consuming.

DSP devices comprise permanent, fixed hardware architecture and as mentioned above are programmable by software which cn.ble them to provide ultra-fast instruction sequences, enabling them to process signals in real time. For example, they can handle audio signals of circa 20 kilohertz enabling the device to perform hundreds of millions of operations per second. However, their design means that they are dedicated to a single group of tasks. In a digital mixer many different types of tasks are required and therefore vast arrays of differently designed DSP devices are required, housed on multiple printed circuit cards; typically 6 to 8 of such devices per card. However, such mixers contain a large number of components with a large number of relatively complex interconnects. lAlso, the implementation of a processor circuit requires additional complex hardware, such as a processor, RA and RaM. Therefore, they are relatively expensive to construct and are intrinsically unreliable. Furthermore, DSP devices consume a large amount of energy, and consequently generate a large quantity of heat. If there are many sample streams to sum, the burden of performing the necessary accumulations may consume a significant proportion of the DSP device's processing capacity, or worse, require the addition of extra DSP devices.

Field-programmable gate arrays (FPGA) are integrated

circuits that can be programmed in the field after

manufacture, enabling the user to tailor such to their own individual needs. Once programmed such devices run using solely fixed architectures comprising an array of configurable logic blocks and routing channels. They have the disadvantage that they run at much lower speeds when compared to the software operated DSP devices, making them unsuitable for use in mixing consoles where real time processing is required Rowever they have the advantage that they can handle a larger number of different tasks and can be reconfigured so that they can handle different tasks.

It is an object of the present invention to provide a system of digital signal processing which overcomes or alleviates one or more of the above described drawbacks.

At its most general, the invention provides a system in which a large number of digital signals can be down-mixed to a smaller number of signals in a controlled manner, using fixed architecture, requiring no software or DSP processing. In one embodiment, such a system may be provided using a FPGA to enable its use in the fast processing of digital signals by incorporating an innovative RAM which enables the operating speed of the FGPA to increase to enable real time processing and thereby its use in mixing consoles.

In accordance with a first aspect of the present invention there is provided apparatus for incremental data storage including: first dual port RAM for storing a plurality of data values, each data value being stored at a respective address of the RAM; addressing means for selecting an address of the RAM; writing means for writing a data value to a selected address; receiving means for receiving a subsequent data value to be added to an initial data value stored at a selented address.

reading means for reading the initial data value from the selected address; adding means for adding the subsequent data value to the initial data value, so that the writing means can write the resulting cumulative data value to the selected address so replacing the initial data value and becoming the initial data value for subsequent operations; reset control means for controlling the write_means so as to selectively ignore the output of the adding means when it is desired to write an initial data value to the selected address.

Effectively, using this arrangement each location in the RAM's memory is adapted to function as both an accumulator and a storage element. The apparatus operates to successively write new data values to each location in the memory which data value is an accumulation of a data value stored in said location and a new data value.

The reset control means operates to terminate a succession of accumulations and start a new succession of accumulations.

"Dual port RAM" is a known type of RAM in which each memory location (selected by address) can be simultaneously written to and read from.

Clearly in preferred embodiments, the operation of the apparatus is such that the process is repeated in the same fashion for a plurality of addresses and/or for a plurality of data values added to each address as required. For example, if downmixing a six channel (5.1) audio signal to a two channel (stereo) signal and each channel is sampled at a rate of 48 kHz, then a signal sample period will be approximately 20 micro seconds.

Within a single sample period, a predetermined combination of any, some or all of the six channel signals may be required to achieve the desired downmixing effect. Therefore, the value of each channel (as modified by any desired coefficient) would be added in turn to a single selected memory location. This process may then be repeated a number of times within the same sample period, so as to provide different mixes of the chosen channels and/or mixes of different channels, as desired. Each of these "mixes" (i.e. addition operations) is stored in a respectively different memory location.

One possible drawback of the above arrangement, in some practical situations, may be that while it is possible to write to and read from the same address in a dual-port RAM simultaneously, some degree of control might need to be exercised in order to ensure smooth operation, for example that a data value was not being written-over whilst it was still being read.

Accordingly, in some preferred embodiments the invention also includes a second dual-port RAM to which the writing means writes the same data value as is written to the first dual-port RAM. This second dual- port RAM may also include access means for accessing the data value at a selected address to nhle it to be read and utilised by further circuitry.

The reset control means may also be arranged to control the read and write_addresses of the second dual-port RAM. Preferably, only up to half of the available memory locations in the second dual-port RAM are used at any given time for write_processes, and preferably up to the other half of the available memory addresses are used at any one time for read processes. When a reset operation occurs (i.e. when the reset control means controls the write_means so as to write the initial data value to the selected memory address), the reset control means also "pages" the second dual-port RAM. By "pages" is meant that the data values in the half of the memory locations which were being used as write_addresses are copied to the other half of the memory locations which were being used as read addresses.

In a preferred embodiment the apparatus is implemented on a FPGA and may be used in a mixing console and in a preferred embodiment a digital mixing console.

In a further aspect, the present invention provides a method for incremental data storage which includes the steps of: 1. For a selected address of a first dual-port RAM storing an initial data value at that address, 2. Receiving a subsequent data value to be added to the initial data value, 3. Reading the initial data value from the selected address, 4. Adding the initial data value to the subsequent data value so as to produce a resulting cumulative data value, 5. Writing that cumulative data value to the selected address so that it replaces the initial data value and becomes the initial data value for subsequent operations.

Preferably, the method further includes the step of repeating the process for further subsequent data values.

Preferably the method also includes the step of repeating the process for further selected address of the dual-port RAM.

Other preferred features of the method will be

apparent from the corresponding description of the

apparatus.

By way of example only embodiments of the invention will now be described with reference to the accompanying drawings in which: Figure 1 illustrates a first embodiment of a digital signal processor constructed in accordance with the present invention; Figure 2 illustrates a second embodiment of a digital signal processor constructed in accordance with the present invention; Figure 3 is a schematic timing diagram illustrating the operation of the digital signal processors of Figures 1 and 2. 1(

Figure 1 shows the digital signal processor in which the block of random access memory (RAM) 10 is operated such that it has the novel property that each location in the memory acts like an accumulator and a storage element. For example if a location contains a value X, and subsequently, a value Y is written to the same location, then the resulting stored value is X+Y. The acronym ARAM (Additive Ram) is adopted herein to refer to this digital signal processor. In a standard RAM the subsequent values would overwrite the previously stored value.

Figure 2 shows a second embodiment of a digital signal processor in accordance with the present invention. The processor of Figure 2 is essentially that of Figure 1 with the addition of an additional block of dual-port RAM 12. This additional block of dual-port RAM 12 carries out the function of the "second dual-port RAM" referred to previously, The only other difference is in the production of the relevant reset or page control signals. In Figure 1, the reset signal itself may be a simple pulse, which pulse is then converted by flip-flop 2 into a signal which goes alternatively high and low as shown in new page control signal Figure 3. This is also the functionality of the page control signal of the processor shown in Figure 2.

Like reference numerals are used for like components in both Figures 1 and 2. To avoid unnecessary repetition, the function of the two embodiments will now be described together. in

The ARAMs include a number of discrete memory and logic components namely dual-port RAM's 10, and 26 (and also 12 in Figure 2), an adder 18, an XOR gate 22, and a multiplexor 24. Although hereinunder a circuit is described made of such discrete components, the circuit may also be implemented onto a FPGA device.

The ARAMs of the present invention have a number of control inputs for writing data from external circuitry into the ARAM including write_data 4, write_address 6, write enable 8 and read_address 14. These values are stored in one or two of the dual-port RAM's 10, 12. The ARAt1s of the present invention have the property that it appears to external circuitry as if it were a standard dual-port RAM, in that the external circuit (not shown) expects that on any positive edge of the write_enable signal 8 that write_data 4 will be written into location write_address 6 of the ARAMs. The ARAM 2 has a control input read_address 14 and an output read_data 16. At any time, the output of the ARAM of Figure 2 is determined by the value of read_address 14. However, in the embodiment of Figure 1, the write_address 6 also functions to -10-control the read address for the output of dual-port RAM 10.

When any value is written by external circuitry into the ARAM, the value is stored in the one or two separate dual-port RAN's 10, 12. Each of these RAM's 10, 12 has independent read and write controls and input and output data buses.

The dual-port RAM 10 is provided fo store a set of values in that when a data value is first written it is stored therein having passed through the adder 18 and the multiplexor 24. When the next value is to be written during an accumulation the output of dual-port RAM 10 is fed to the input of an adder circuit 18. The adder 18 then sums said stored value with the new value and outputs the summation to the multiplexor 24, which provides the sum of the previously stored result from dual-port RAM 10 and the new write_data back to the dual-port RAM 10 for storage and for subsequent use in the next accumulation. The multiplexor 24 additionally provides the summation to the optional dual-port RAM 12 of Figure 2 which is provided to contain the final results of the accumulation and is accessed by external circuitry through the read_address input 14. Hence the output of the multiplexor 24 may be stored in both the dual-port RAM 10, where it may be used in subsequent accumulation operations, and in dual-port RAM 12, where it will become available for external circuitry to access.

In short this system operates as follows: If it is the first value, after the start of a new sample period, to be written to any given location, then this new value is simply stored, as with a standard RAM. If however one or more values have been previously written to this location, within its current sample period, then the location is updated with the sum of the new value and the existing value. This process continues to the end of the sample period and when the start of a new sample period i detected, the system ignores the previous set of accumulated values and begins the process again by clearing the memory and writing a new first value to a given location.

To this end the sample period is detected by the provision of reset or page_control input 20 which indicates new sample periods. For example in the case of processing digital audio the sample period may be 20.Bps, corresponding to a sample rate of 48kHz. At the start of each new sample period, the state of page_control changes from low to high, or high to low as shown in Figure 3, and then remains constant until the beginning of the next sample period, thus defining a square wave at a frequency of half the sample rate. (In the following description the change from low to high is used to provide indication of a new sample period) . At the start of each new sample period a bit value is written to the third dual-port RAM 26 to indicate the state of the sample period.

When an external circuit writes a new data value to a location in the ARAM, the write_address 6 is used to read out a value from each of the dual-port RAM's 10 and -12 - 26. As mentioned above dual-port RAM 10 contains the result of the previous write and accumulation operations.

Dual-port RAM 26 contains the value of the page-control bit from the last time a value was written to dual-port RAM 10. This stored value of page control is compared to the current value of page-control using XOR gate 22. The absolute value of page control is irrelevant, the comparison is to determine whether the stored arid current values are the same or different. If 11) they are different, this indicates that since the last accumulation to this location, a new sample period has begun and that the value stored in dual-port RAM 10 is to be discarded and that the new data value forms the first value in a new accumulation.

The output of the XOR gate 22, if high and such indicates the start of a new accumulation, controls multiplexor 24. The multiplexor 24 then selects the current write data rather than the output of the adder in order to start a new accumulation and to write this as a new first value to dual-port RAM 10, overwriting the previously stored value. The process then restarts with each subsequent value added to the stored value as described above until the end of the sample period.

In short if the output of the XOR gate 22 is high and as such indicates the start of a new accumulation, the multiplexer 24 then selects the current write data in order to start a new accumulation and the value stored in dual-port RAM is then discarded in order that a new data value can form a first value in a new accumulation. -13-

The data bus has a width of n bits. Dual-port RN"IS and 12 are therefore also n bits wide. However, dual-port RAM need only be 1 bit wide, in that it only stores the page_control value, which is 0 or 1.

The write_address buswidth is m bits. This means that up to 2m Locations can be addressed in each dual-port RAM, allowing up to 2m separate accumulations to be created. This has the advantage that during each sample period, it is possihl to perform a large number of write operations to the ARAM, into any of its locations, enabling the creation of a number of unique accumulation results. Hence by the provision of simple means using simple components there is a system and method of creating an array of accumulations at a very high rate.

If this architecture is mapped onto an FPGA the speed of operation is sufficient to enable real time processing and the use of the FPGA in for example a digital signal processor console such as a mixing desk, eliminating or alleviating the need for expensive DSP devices and software. Furthermore, each FPGA can incorporate a number of such digital signal processor or include other circuitry, further enabling miniturazation, and further increasing the number of operations.

The page_control value is also provided to dual-port RAM 12, whereat it is input at different locations. It is fed in at the read_address bus 14, but also passes through an invertor 28 before being input as an inverted version of page_control appended to the write_address bus 14a. This has the effect of paging the dual-port RAM 12. -14-

This means that during one sample period, a set of accumulations are created in one half of the dual-port RAM's address range, while an external circuit can access accumulated results from the previous sample period, in the other half of the dual-port RAM's address range. At the next sample boundary, the value of page_control changes and the new set of results are available to be read out. This has the advantage that it prevents the possibility of the value in a given location being changed t exactly the same time that the external circuitry is reading from the location. Thereby eliminating the possibility of unpredictability in the results.

The speed of the ARAM may be further increased enabling it to operate at significantly higher speeds by the addition of registered pipeline stages at the input and output of the dual-port RAM's. Also, compensatory pipelining may be inserted into the input and address data paths. By the introduction of such pipeline stages an approximate four times increase in speed has been seen. In tests a pipelined version of the ARAM implemented in a FPGA has been measured with a speed of 200MHz. In a system where the audio sample rate is 48kHz, it is possible to have 200 millon/48000-which is the equivalent of 4166 accumulation operations. This could be utilised in practice as 4166 accumulations to a single location, or smaller numbers of accumulations to a larger number of addresses.

Figure 3 shows in the form of a schematic timing diagram the function of the ARAMs which has been -15 -described above. As mentioned, the page control signal alternates between high and low. Aj each transition (which marks the start of a new sample period) the output of the XOR gate 22 will provide a control signal for each selective address which permits the reset of that address when being written with the initial data value in each sample period. The blocks titled "data writing" illustrate that during each sample period up to 2m addresses of dual-port RAMS 10 and optionally 12 may be written to and then reiritten to wit.h accumulated values as required. At the end of each sample period, the previous period's calculations may then be accessed by a subsequent process via the read output whilst at the same time the first process is then being carried out again on the next sample period's set of data, and so on.

It is to be understood that the invention is not intended to be restricted to the details of the above described embodiments which are described by way of

example only.

Claims

1. Apparatus for incremental data storage including: first dual port RAM for storing a plurality of data values, each data value being stored at a respective address of the RAM; addressing means for selecting an address of the RAM; writing means for writing a data value to a selected address; receiving means for receiving a subsequent data value to be added to an initial data value stored at a selected address; reading means for reading the initial data value from the selected address; adding means for adding the subsequent data value to the initial data value, so that the writing means can write the resulting cumulative data value to the selected address so replacing the initial data value and becoming the initial data value for subsequent operations; reset control means for controlling the write_means so as to selectively ignore the output of the adding means when it is desired to write an initial data value to the selected address.

2. Apparatus according to Claim 1 including a second dual-port RAM arranged so that in use the writing means writes to it the same data value as is written to the first dual-port RAM.

3. Apparatus according to Claim 2 wherein the dual-port RAM also includes access means for accessing the data value at a selected address to enable it to be read and utilised by further circuitry.

4. Apparatus according to Claim 2 or Claim 3 wherein the reset control means is also arranged to control the read and write addresses of the second dual-port RAM.

5. Apparatus according to any of Claims 2 to 4 wherein the second dual-port RAM is arranged so that in use only up to half of the available memory locations in the second dual-port RAM are used at any given time for write_processes, and up to the other half of the available memory addresses are used at any one time for read processes.

6. Apparatus according to Claim 5, wherein the reset control means is operable such that the data values in the half of the memory locations which were being used as write_addresses are copied to the other half of the memory locations which were being used as read addresses.

7. A method for incremental data storage which includes the steps of: 1. For a selected address of a first dual-port RAM storing an initial data value at that address; 2. Receiving a subsequent data value to be added to the initial data value; 3. Reading the initial data value from the selected address; 4. Adding the initial data value to the subsequent data value so as to produce a resulting cumulative data iialue; 5. Writing that cumulative data value to the selected address so that it replaces the initial data value and becomes the initial data value for subsequent operations.

8. A method according to Claim 7 further including the step of repeating the process for further subsequent data values.

9. A method according to Claim 7 or Claim 8 further including the step of repeating the process for further selected address of the dual-port RAM.