JPH06164247A - Input amplifier circuit - Google Patents

Abstract

PURPOSE:To provide an input amplifier circuit which has the high resistance to the power noises regardless of the amplification factor of an amplifier part. CONSTITUTION:An input amplifier circuit contains an input signal line 3 to which an input signal IN is supplied, a bias potential supply means 4 which supplies the bias voltage of a prescribed level to the line 3, and a Schmitt trigger circuit 7 which is connected to the line 3. The circuit 7 is switched based on the first threshold voltage higher than the bias voltage and the second threshold voltage lower than the bias voltage. Then the amplified signal OUT is transmitted from the circuit 7. In such a constitution, the signal OUT is obtained based on the threshold voltage levels VthH and VthL of the circuit 7. Therefore the level of the signal OUT is not fluctuated despite the occurrence of power noises. Furthermore the amplification factor can be optionally set since the input signal IN is amplified by the circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input amplifier circuit, and more particularly to an input amplifier circuit suitable for amplifying an AC signal.

[0002]

2. Description of the Related Art As shown in FIG. 4A, an input amplifier circuit 44 for inputting an AC signal and amplifying the input signal is basically composed of an amplifier section 40 and a bias section 41. The bias voltage is set so that the input stage voltage V1 and the output stage voltage V2 are equal to each other. In the figure, reference numeral 1 is an AC signal source, and reference numeral 2 is a coupling capacitor.

However, the circuit shown in FIG. 4A may malfunction when the input signal IN has a low frequency (small amplitude). The cause of the malfunction is shown in FIG. 4 (b) and FIG. 4 (c).
Will be explained. As shown in FIG. 4B, the VDD line and the GND line always have an inductance component 42 and a resistance component 43. It should be noted that the wiring line also has an inductance component and a resistance component, but they are ignored here because they are small.

Since the VDD line and the GND line have the inductance component 42 and the resistance component 43, each circuit performs a switching operation, and when the switching operation current flows into the VDD / GND line, the potentials of these lines vibrate. Let This is called power supply noise. The power supply noise is easily affected when the input signal IN is near the threshold voltage Vth of the inverter 46 which constitutes the amplifier section, that is, when the input signal IN has a small amplitude and a low frequency. . Figure 4 shows the timing chart at this time.
It shows in (c).

The timing chart shown in FIG. 4C shows the case where the input signal IN changes from the "L" level to the "H" level, and the input signal IN is the threshold value of the inverter 46. The waveforms of the main terminals when each circuit performs the switching operation across the voltage Vth (here, it is assumed that it is set to (VDD-GND) / 2) are shown.

As shown in FIGS. 4B and 4C, the input signal IN constitutes the input amplifier circuit 44 and the inverter 4 is provided.
When it becomes higher than the threshold voltage Vth of 6, the amplifier circuit 44
The output signal OUT of the output signal falls from the "H" level to the "L" level (time t0). At this time, it is assumed that a switching operation current is generated in the input amplifier circuit 44 or another circuit 45 connected to the subsequent stage of the input amplifier circuit 44 and flows into the VDD / GND line to oscillate the potential of the VDD / GND line. At this time, the threshold voltage Vth is VDD / G
Since it vibrates in accordance with the vibration of the potential of the ND line, there are times when the voltage level of the threshold voltage Vth becomes higher than the voltage level of the input signal IN. At this time, the output signal OUT, which has fallen in the "L" level direction, rises in the "H" level direction (time t1). After that, the changed threshold voltage Vth due to the above-mentioned vibration changes from rising to falling, and when the voltage level of the threshold voltage Vth becomes lower than the voltage level of the input signal IN, it rises in the “H” level direction. The output signal OUT again falls in the "L" level direction (time t2). In this way, the waveform of the output signal OUT of the input amplifier circuit 44 fluctuates with the power supply noise. If the output waveform fluctuates, there is a possibility that the other circuit 45 connected to the subsequent stage of the input amplifier circuit 44 may malfunction.

As an input amplifying circuit for preventing this kind of malfunction, there is a circuit in which a Schmitt trigger circuit 50 is added after the amplifier section 40 as shown in FIG. 5 (a). In such an input amplifier circuit, the Schmitt trigger circuit 50
Threshold voltage V of the inverter 52 having a low threshold voltage of
thL is set to be lower than the minimum point of the waveform fluctuation of the output signal OUT40 of the amplifier section, and the threshold voltage VthH of the inverter 51 having a high threshold voltage is set to the maximum point of the fluctuation of the output waveform of the amplifier section. Set higher. 5 (b) is shown in FIG.
It is a timing chart of the input amplifier circuit shown in (a). As shown in FIG. 5B, the waveform of the output signal OUT40 of the amplifier section 40 fluctuates due to power supply noise, but the output signal OUT of the Schmitt trigger circuit 50 does not fluctuate. Therefore, there is no fluctuation in the waveform of the final output signal OUT of the input amplifier circuit.

However, in the circuit shown in FIG. 5A, if the amplification factor of the amplifier section 40 is increased so that the circuit can operate even if the amplitude of the input signal IN is reduced, the output of the amplifier section 40 will be increased. The waveform of the signal OUT40 will greatly fluctuate. Therefore, the threshold voltage VthH of the inverter 51 of the Schmitt trigger circuit 50 is higher, and
The threshold voltage VthL of the inverter 52 must be set lower. For example, the output signal OU of the amplifier unit 40
If the amplification factor of the amplifier section 40 is increased so that the waveform of T40 becomes the full swing state, it becomes almost impossible to realize the Schmitt trigger circuit 50 for eliminating the fluctuation of the final output signal OUT.

[0009]

As described above, in the conventional input amplifier circuit in which the Schmitt trigger circuit is added after the amplifier unit to prevent the fluctuation of the output waveform due to the power supply noise, the Schmitt trigger circuit is Since it is necessary to consider the threshold voltage of the configured inverter, there is a problem that the amplification factor setting of the amplifier section is limited.

The present invention has been made in view of the above points, and an object thereof is to provide an input amplifier circuit that is strong against power supply noise without depending on the amplification factor of the amplifier section.

[0011]

An input amplifier circuit according to the present invention includes an input signal line to which an input signal is supplied, a bias potential supply means for supplying a predetermined bias voltage to the input signal line, and the input signal. Schmidt connected to the wire
And a trigger circuit. And the Schmitt trigger circuit has a first threshold voltage higher than the bias voltage,
It is characterized in that switching is performed based on a second threshold voltage lower than the bias voltage, and a signal amplified by this Schmitt trigger circuit is output.

[0012]

According to the input amplifier circuit as described above, the amplified and output signal can be obtained depending on the threshold voltages VthH and VthL of the Schmitt trigger circuit, so that power source noise is generated. However, the level of the signal does not fluctuate. Therefore, strong resistance to power supply noise can be obtained.

Further, since the signal amplified by the Schmitt trigger circuit is output, the amplification factor can be set arbitrarily.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 1 (a) is a circuit diagram of an input amplifier circuit according to an embodiment of the present invention, and FIG. 1 (b) is a timing chart of the circuit shown in FIG. 1 (a).

As shown in FIG. 1, an AC signal source 1 for generating an input signal is connected to an input signal line 3 via a coupling capacitor 2. The input signal IN and the AC signal source 1 are supplied to the input signal line 3 via the capacitor 2. The input signal line 3 is connected to a bias unit 4 that supplies a predetermined bias voltage and biases the input signal line 3 to a predetermined voltage. In this embodiment, the bias voltage is set to (VthH + VthL) / 2. It should be noted that VthH indicates the higher threshold voltage of the Schmitt trigger circuit 7, and VthL indicates the lower threshold voltage of the Schmitt trigger circuit 7. Bias section 4
Is a resistor 5 having one end connected to the input signal line 3 and an input connected to the other end of the resistor 5 so that the output is fed back to this input, and the inverter 6 functions as a constant current source.
It consists of and. The input signal line 3 is connected to the Schmitt trigger circuit 7. The Schmitt trigger circuit 7 has an input connected to the input signal line 3, an inverter 11 having a threshold voltage VthH higher than the bias voltage of the input signal line 3, and an input connected to the input signal line 3. Threshold voltage VthL lower than the bias voltage of the input signal line 3
And an inverter section 12 having an inverter. The output of the inverter 11 is the NAND gate 9-1.
Of the NAND gate 9-2 is connected to the first input of the NAND gate 9-2 via the inverter 10. The output of the NAND gate 9-1 is the NAND gate.
Gate 9-2 is connected to the second input, and the output of NAND gate 9-2 is connected to the second input of NAND gate 9-1. The final output signal OUT of the input amplifier circuit is NAN
It is obtained from the interconnection point between the output of the D gate 9-2 and the second input of the NAND gate 9-1.

Next, the operation of the above circuit will be described with reference to the timing chart when the input signal IN changes from "L" level to "H" level.

As shown in FIG. 1B, when the input signal IN becomes higher than the threshold voltage VthH, the output signal OUT
Changes from "H" level to "L" level (time t
0). At this time, when each circuit performs a switching operation to generate power supply noise, the bias voltage and the threshold voltages VthH and VthL of the Schmitt trigger circuit 7 vary. However, NAND gates 9-1 and 9-2 connected to the amplifier unit 8
Since the connection state of is a flip-flop configuration, even if the input signal IN becomes lower than the bias potential as shown at time t1, the output signal OUT changes unless the input signal IN becomes lower than VthL. There is no. Therefore, the waveform of the output signal OUT does not fluctuate even if power supply noise occurs. The amplification factor can be adjusted in various ways by changing the transistor size of the inverters 11 and 12 that form the amplifier 8.

Although not shown in the drawing, when the input signal IN changes from "H" level to "L" level, the output signal OUT changes unless the input signal IN becomes higher than VthH, as described above. do not do.

In the input amplifier circuit having the above structure, the input signal I
Since the change of the output signal OUT due to N depends on the threshold voltages VthH and VthL of the Schmitt trigger circuit 7, even if the power supply noise occurs, the output signal OUT
Does not waver. Further, since the change of the output signal OUT does not depend on the amplification factor of the amplifier section 8, the amplification factor setting is not limited.

In the above embodiment, the reason why the bias voltage is set to (VthH + VthL) / 2 is that the operable minimum input signal amplitude can be set to (VthH-VthL). The setting of such a bias voltage is the best because the amplitude of the input signal can be minimized.

However, the bias voltage is (1)
If the relationship as expressed by the equation (2) is satisfied, various changes can be made according to the circuit specifications.

VthH ≤ bias voltage + minimum input amplitude / 2 (1) VthL ≤ bias voltage-minimum input amplitude / 2 (2) Further, according to the present invention, the Schmitt trigger circuit 7
There is also an advantage that the threshold voltage VthH and the threshold voltage VthL can be set in the vicinity of VDD / 2. Conventionally, the threshold voltage Vth of the Schmitt trigger circuit 7 is
It is necessary to make the difference between H and the threshold voltage VthL wider than the fluctuation range of the output signal of the amplifier section. In order to increase the difference between the threshold voltage VthH and the threshold voltage VthL in this way, it is necessary to greatly differ in the dimensions of the transistors that realize the threshold voltages. However, in the present invention, the threshold voltage VthH and the threshold voltage VthL are
Can be realized without changing the size of the transistor that realizes the threshold voltage of both, and the size of the integrated circuit can be reduced, and the parasitic capacitance can be reduced. The effect can also be obtained.

Next, various modifications of the above embodiment will be described.

FIGS. 2A and 2B are views showing modified examples of the bias section 4.

The bias circuit constituting the bias section 4 shown in FIG. 1A can be changed to the bias circuit shown in FIGS. 2A and 2B.

The bias circuit shown in FIG. 2A is one in which the input signal line 3 is connected to the power supply 22 via the resistor 21.

In the bias circuit shown in FIG. 2B, the high potential power supply VDD and the input signal line 3 are connected by the resistor 23, and the low potential power supply (for example, ground) and the input signal line 3 are connected by the resistor 24. It was done.

In addition, various bias circuits can be used.

3A to 3E are diagrams showing modifications of the Schmitt trigger circuit 7, respectively.

The Schmitt trigger circuit 7 shown in FIG. 1 (a) can be changed to a Schmitt trigger circuit 7 as shown in FIGS. 3 (a) to 3 (e).

In the Schmitt trigger circuit 7 shown in FIG. 3A, the output of the inverter 11 is connected to the input of the inverter 30, and the output of the inverter 30 is the first output of the NOR gate 31. Connected to the input of. The output of the inverter 12 is connected to the first input of the NOR gate 32,
The output of the R gate 32 is connected to the second input of the NOR gate 31. The output of NOR gate 31 is NOR
It is connected to the second input of gate 32. Output signal O
The UT is extracted from the interconnection point between the output of NOR gate 31 and the second input of NOR gate 32.

In the Schmitt trigger circuit 7 shown in FIG. 3B, the output of the inverter 11 is input to the input of the inverter 35 via the first transfer gate 33 composed of the CMOS circuit. The output of the inverter 12 is connected to the input of an inverter 35 via a second transfer gate 34 composed of a CMOS circuit.
The input of the inverter 35 is further the transfer gate 3
The gates of the N-channel MOSFETs 3 and 34 are connected to each other. The output of the inverter 35 is the P channel type M of each of the transfer gates 33 and 34.
It is connected to the gate of the OSFET. Output signal OUT
Is the output of the inverter 35 and the transfer gate 33,
Each of the 34 P-channel MOSFETs is extracted from its interconnection point with the gate.

In the Schmitt trigger circuit 7 shown in FIG. 3C, the resistor 36 and the inverters 38 and 39 are connected in series. A resistor 37 is connected in parallel to the inverters 38 and 39. Input signal IN is resistor 3
6 and the output signal OUT is supplied to one end of the inverter 39.
Is output from the interconnection point of the output of the resistor and the resistor 37. The two threshold values VthH and VthL of the Schmitt trigger circuit 7 can be set by the resistance ratio of the resistors 36 and 37, respectively. The amplification factor can be adjusted in various ways by changing the size of the transistor forming the inverter 38.

In the Schmitt trigger circuit 7 shown in FIG. 3D, the P-channel MOSFETs 61 and 62 and the N-channel M are provided between the high potential power supply VDD and the low potential power supply GND.
The OSFETs 63 and 64 are connected in series. The gates of these MOSFETs 61 to 64 are commonly connected. Current path of MOSFET 62 and MOSFE
The input of an inverter 67 is connected to the interconnection point of T63 with the current path, and the output of this inverter 67 is an inverter.
Is connected to the input to the data 68. The output of the inverter 68 is connected to the gate of the P-channel type MOSFET 65 and the gate of the N-channel type MOSFET 66. One end of the current path of the MOSFET 65 is
It is connected to an interconnection point between the current path of the MOSFET 61 and the current path of the MOSFET 62, and the other end is connected to the low potential power supply GND. Further, one end of the current path of the MOSFET 66 is connected to the MO of the current path of the MOSFET 63.
It is connected to the interconnection point of the SFET 64 with the current path, and the other end is connected to the high potential power supply VDD. The input signal IN is supplied to the common connection point of the gates of the MOSFETs 61 to 64, and the output signal OUT is the inverter 68.
Is extracted from the interconnection point between the output of the MOSFET and the gates of the MOSFETs 65 and 66. The two threshold values VthH and VthL of the Schmitt trigger circuit 7 can be set by providing MOSFETs 65 and 66, respectively. That is, using the MOSFET 65, the MOSFET 6
The current that tries to flow to 2 is sent to the ground (GND),
In addition, a difference (hysteresis) between the on-potential and the off-potential of the inverter constituted by the MOSFETs 61 to 64 is caused by causing the current that is about to flow to the MOSFET 63 to flow from the high potential power source (VDD) using the MOSFET 66. Obtainable. The amplification factor is MOSFET 61
Various adjustments can be made by varying the size of ~ 64.

The Schmitt trigger circuit 7 shown in FIG. 3 (e) is an inverter 6 compared to the circuit shown in FIG. 3 (d).
8 is removed, the other end of the current path of the MOSFET 65 is connected to the high potential power supply VDD, and the other end of the current path of the MOSFET 66 is connected to the low potential power supply GND. Even in such a circuit, a difference (hysteresis) can be obtained between the on-potential and the off-potential of the inverter constituted by the MOSFETs 61-64.

In addition, various Schmitt trigger circuits can be used.

[0038]

As described above, according to the present invention, it is possible to provide an input amplifier circuit that is resistant to power supply noise without depending on the amplification factor of the amplifier section.

[Brief description of drawings]

1A is a circuit diagram of an input amplifier circuit according to an embodiment of the present invention, and FIG. 1B is a timing chart of an input amplifier circuit according to an embodiment of the present invention.

FIG. 2A and FIG. 2B are circuit diagrams of modified examples of a bias unit.

3A to 3E are circuit diagrams of modified examples of the Schmitt trigger circuit.

FIG. 4 (a) is a circuit diagram of a conventional input amplifier circuit, FIG. 4 (b) is a diagram showing a usage state of the circuit shown in FIG. 4 (a),
FIG. 4C is a timing chart of the circuit shown in FIG.
To.

5A is a circuit diagram of another conventional input amplifier circuit, and FIG. 5B is a timing chart of the circuit shown in FIG. 5A.

[Explanation of symbols]

1 ... AC signal source, 2 ... Coupling capacitor, 3 ...
Input signal lines, 4 ... Bias section, 7 ... Schmitt trigger circuit, 8 ... Amplifier section.

Claims (2)

[Claims] 1. An input signal line to which an input signal is supplied, a bias potential supply means for supplying a predetermined bias voltage to the input signal line, and a first voltage line connected to the input signal line and having a voltage higher than the bias voltage. A Schmitt configured to output an amplified signal that is switched based on a threshold voltage of the second threshold voltage and a second threshold voltage that is lower than the bias voltage.
An input amplifier circuit comprising a trigger circuit. 2. The bias voltage is: VthH ≦ bias voltage + minimum input amplitude / 2 VthL ≧ bias voltage−minimum input amplitude / 2 (where VthH is a first threshold voltage and VthL is a second threshold voltage).
Threshold voltage of. 2. The input amplifier circuit according to claim 1, wherein the input amplifier circuit is set so as to satisfy the relationship (1).