JP3105435B2 - Input circuit - Google Patents

Input circuit

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Publication number
JP3105435B2
JP3105435B2 JP07300820A JP30082095A JP3105435B2 JP 3105435 B2 JP3105435 B2 JP 3105435B2 JP 07300820 A JP07300820 A JP 07300820A JP 30082095 A JP30082095 A JP 30082095A JP 3105435 B2 JP3105435 B2 JP 3105435B2
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Prior art keywords
input
signal
current
output
node
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JPH09148911A (en
Inventor
浩幸 山田
正久 根本
昇平 関
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沖電気工業株式会社
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Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit provided in a semiconductor integrated circuit or the like, in particular, a clock signal of, for example, several hundred MHz or more constituted by a Schottky gate type field effect transistor (hereinafter referred to as "FET"). Of the input circuit of FIG.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. Reference: IEICE Technical Report, ED93-15
5 (1994-1) Ichioka et al., "10Gb / S GaAs"
DCFL 8: 1 multiplexer, 1: 8 demultiplexer "p. 53-58 FIG. 2 is a circuit diagram showing one configuration example of a conventional input circuit described in the above-mentioned document. This input circuit is provided in a semiconductor integrated circuit and has an input terminal 1 for inputting an input signal Vi.
Is connected to one end of the terminating resistor 3 via the coupling capacitor 2. The other end of the terminating resistor 3 is connected to the ground potential VSS via the coupling capacitor 4 and is connected to the inverter 5.
Are connected to the input side and the output side. One end of the terminating resistor 3 is connected to the input side of the inverter 6.
The output side of the inverter 6 is connected to a logic circuit in a semiconductor integrated circuit composed of the inverters 7, 8 and the like.

Each of the inverters 5 to 8 is composed of the same circuit, and a general circuit diagram is shown in FIG. FIG.
3 is a circuit diagram of the inverter 6 in FIG. The inverter 6 is of a DCFL (Direct Coupled FET Logic) type, and is an N-channel GaAs MESFET (GaAs
And a switch-type enhancement FET 6a and a load depletion FET 6b. FET 6a is:
Gate is input terminal IN, drain is output terminal OUT
And the source is connected to the ground potential VSS. In the FET 6b, the gate and the source are connected to the output terminal OUT, and the drain is connected to the power supply potential VDD. The input terminal IN is connected to one end of the terminating resistor 3 shown in FIG. 2, and the output terminal OUT is connected to the input side of the inverter 7 shown in FIG.

Next, the operation of FIGS. 2 and 3 will be described. Since the input side and the output side of the inverter 5 are connected, the potential of the input / output side is substantially equal to the threshold voltage Vth, and this voltage is supplied as a bias voltage to the input of the inverter 6 via the terminating resistor 3. Since the vicinity of the threshold voltage Vth is the point where the voltage gain is the highest in the input / output characteristics, the inverter 6 biased at this point can operate at the operating point where the input sensitivity is almost maximum. As a result, the input signal Vi input to the input terminal 1 has the DC component removed by the coupling capacitor 2 and only the AC component is applied to the input side of the inverter 6 biased to the optimum value. On the output side of the inverter 6, an output signal Vo whose waveform is shaped into a substantially perfect rectangular wave is supplied to logic circuits such as the inverters 7 and 8 in the integrated circuit.

[0005]

However, the conventional input circuit as described above has the following problems.
The amplitude of the input signal Vi increases, and F
When the gate-source voltage Vgs of the ET 6a exceeds a certain threshold voltage Vth (about 0.7 V), the FET 6a is immediately turned on. Then, a current corresponding to the voltage (Vgs-Vth) flows into the gate of the FET 6a, and charges are accumulated in the gate capacitance Cg of the FET 6a by this current. Next, when the input signal Vi falls and the gate-source voltage Vgs becomes equal to or lower than the threshold voltage Vth, the accumulated charge exists in the gate capacitance Cg.
a does not immediately turn off, but stays on until the charge of the gate capacitance Cg is discharged. For this reason, a phenomenon occurs in which the output delay time for the rise and fall of the input signal Vi differs. In particular, the input signal Vi
Is large, the gate current of the FET 6a also increases, thereby increasing the amount of charge stored in the gate capacitance Cg. Therefore, the output delay time when the input signal Vi falls is increased. Such a phenomenon is illustrated in FIGS.
This will be further described with reference to FIG.

FIGS. 4A to 4C are input / output signal waveform diagrams of the input circuit shown in FIG. 2, in which the horizontal axis is a time axis and the vertical axis is an instantaneous value of the input / output signal. This waveform diagram is 5
The waveform of the output signal Vo when the GHz sine wave input signal Vi is applied to the input terminal 1 is obtained by circuit simulation by a computer. FIG. 4A shows the waveform of the input signal Vi. FIG. 4B shows the input signal V
Output signal Vo when the peak value Vp of i is 0.5 Vp-p
And an output having a duty ratio of about 50% is obtained. On the other hand, FIG. 4C shows the waveform of the output signal Vo when the peak value Vp of the input signal Vi is 8 Vp-p, and the duty ratio has deteriorated to about 29%. In a semiconductor integrated circuit including an input circuit as shown in FIG.
When operating with a clock having the above frequency, high-speed operation is usually realized by using both the rising and falling timings of the clock. The operating speed is limited by the shorter pulse width of the clock. For this reason, a clock with a duty ratio of 50% is ideal, and as the duty ratio departs from 50%, the desired operation speed cannot be obtained. An object of the present invention is to provide an input circuit which solves the problem of the prior art, in a wide range of the input signal level, the deterioration of the duty ratio caused by the difference in the delay time of the output signal with respect to the rise and fall of the input signal. Is provided.

[0007]

According to a first aspect of the present invention, there is provided an input circuit including a current suppressing unit and a waveform shaping unit. The current suppressing means inputs an input signal that changes in a positive direction and a negative direction with reference to a certain level from an input node, and when the amplitude of the input signal is smaller than a certain value, the resistance value becomes smaller and the input signal becomes The current is passed almost as it is, and when the amplitude of the input signal becomes larger than the certain value, the resistance value becomes large and a substantially constant current is output. Further, the waveform shaping means has the constant level threshold value, receives an output current of the current suppressing means, and outputs a first logic level output signal when the output current is larger than the threshold value. When the threshold value is smaller than the threshold value, an output signal of a second logic level different from the first logic level is output. The current suppressing means according to the first invention comprises a first FET (for example, a Schottky gate FET), and the waveform shaping means comprises a second FET.
(For example, a Schottky gate FET) and load means.

According to a second aspect, in the input circuit, the first
The present invention includes the same current suppressing means and waveform shaping means as those of the invention of the first aspect, and impedance matching means. The impedance matching means matches the impedance when the current suppression means is viewed from the input node with the impedance when the input signal supply side is viewed from the input node.
The impedance matching means of the second invention may be constituted by a terminating resistor. Also, this impedance matching means
It may be constituted by a terminating resistor, a coupling capacitor and a bias means. According to a third aspect, in the input circuit, the input circuit includes a DC removing unit, a current suppressing unit, a waveform shaping unit, and an impedance matching unit. The DC suppression unit removes a DC component from an input signal that changes in a positive direction and a negative direction with reference to a certain level, and outputs only an AC component to an input node. When the amplitude of the signal on the input node is smaller than a certain value, the current suppressing means decreases the resistance value and allows the current of the signal on the input node to pass almost as it is, and the amplitude of the signal on the input node becomes smaller. When the resistance value becomes larger than the certain value, the resistance value becomes large and a substantially constant current is output. The waveform shaping means has the constant level threshold value, and outputs an output signal of a first logic level when the output current of the current suppressing means is input and the output current is larger than the threshold value, and is smaller than the threshold value. Sometimes it outputs an output signal of a second logic level different from the first logic level. Further, the impedance matching means matches the impedance when the current suppression means is viewed from the input node with the impedance when the DC removal means is viewed from the input node.

According to the first aspect, since the input circuit is configured as described above, when an input signal is input from the input node to the current suppressing means, when the amplitude of the input signal is small, the input signal is It is sent to the waveform shaping means almost as it is. On the other hand, when the amplitude of the input signal is large, a constant current is output from the current suppressing means and sent to the waveform shaping means. The waveform shaping means outputs an output signal of a first logic level when the input current from the current suppressing means is small,
When the input current is large, an output signal of the second logic level is output. According to the second aspect, when the input signal is supplied to the input node, impedance matching on the input node is achieved by the impedance matching means.
For this reason, the input signal supplied to the input node is efficiently input to the current suppressing means as it is, and the current suppressing means and the waveform shaping means operate almost in the same manner as in the first invention.
According to the third aspect, when the input signal is supplied to the DC removing unit, the DC component of the input signal is removed by the current suppressing unit and sent to the input node. The current suppressing means, the waveform shaping means and the impedance matching means act on the signal sent to the input node in substantially the same manner as in the second invention.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram of an input circuit showing a first embodiment of the present invention. This input circuit is provided in a semiconductor integrated circuit, for example, is connected to an output side of an optical sensor or the like in optical communication, and has an input terminal 11 for inputting an input signal Vi.
The input terminal 11 is connected to the input node N1 via a DC removing means (for example, a coupling capacitor) 12 for removing a DC component from the input signal Vi. Input node N1
Is connected to the impedance matching means 20.
The impedance matching means 20 includes a terminating resistor 21 for matching the input impedance of the input circuit with the output impedance on the input signal supply side, a coupling capacitor 22 for holding a bias potential, and an inverter 23 for supplying a bias voltage. One end of the terminating resistor 21 is connected to the input node N1, and the other end is connected to the bias node N2. The bias node N2 is connected to a second power supply potential (for example, ground potential) VS via the coupling capacitor 22.
Connected to S. The input terminal and the output terminal of the inverter 23 are connected to the bias node N2. Also,
The drain of a current suppressing means (for example, a depletion-mode FET) 31 is connected to the input node N1. F
The gate and the source of the ET 31 are commonly connected, and are connected to the input terminal IN of the waveform shaping means (for example, an inverter) 32. An output terminal OUT of the inverter 32 that outputs the output signal Vo is connected to an internal circuit 40 in the semiconductor integrated circuit. The internal circuit 40 includes a plurality of inverters 4
1, 42 and the like.

Each inverter 23, 32, 41, 42 has
For example, they are composed of the same circuit, and this circuit diagram is shown in FIG.
Shown in FIG. 5 is a circuit diagram of the inverter 32 in FIG. The inverter 32 includes an enhancement type FET 32a for a switch and a depletion type FET for a load.
32b. The gate of the FET 32a is connected to the input terminal IN, the drain is connected to the output terminal OUT, and the source is connected to the ground potential VSS. Also, F
The gate and the source of the ET 32b are commonly connected to an output terminal OUT, and the drain is connected to a first power supply potential (for example, a power supply potential) VDD. An example of the specifications of the FETs 32a and 32b for constituting the FET 31 and the inverters 23 and 32 will be described below.

FET type: N-channel GaAs MESFET Substrate: GaAs semi-insulating substrate Process: Self-aligned process using ion implantation Gate type: W-Al heat resistant gate Gate length: 0.5 μm Gate width: 90 μm (enhancement type) 30 μm (Depletion type) FET threshold voltage Vte: 50 mV (enhancement type) Vtd: -750 mV (depression type) K value (per 10 μm gate width): 3.7 mS / V (enhancement type) 2.0 mS / V (depletion type) Here, the K value refers to a coefficient K when the drain-source saturation current Idss of the FET is approximated by the following equation, and is a numerical value that is a measure of the amount of current that can be turned on / off. Idss = K (Vgs−Vt) 2 where Vgs: gate-source voltage Vt: threshold voltage of FET Further, the terminating resistor 21 is manufactured on a GaAs semi-insulating substrate by an ion implantation method. It is 50Ω. The coupling capacitors 12 and 22 each have a capacity of 200
A ceramic capacitor having good high frequency characteristics of pF is connected outside the semiconductor chip.

Next, the operation of the input circuit shown in FIGS. 1 and 5 will be described. For example, an input signal Vi that changes according to the amount of received light and is biased with a constant DC voltage is applied to the input terminal 11 from an optical sensor or the like. This input signal V
i has a DC component removed by the coupling capacitor 12,
Only the AC component is transmitted to input node N1. Since the impedance matching means 20 is connected to the input node N1, the input impedance of this input circuit at the input node N1 matches the output impedance of the optical sensor viewed from the input node N1. For this reason, the waveform of the input signal Vi is accurately transmitted to the input node N1 without receiving reflection or distortion. The input signal Vi transmitted to the input node N <b> 1 is sent to the input terminal IN of the inverter 32 while its current is suppressed by the FET 31. The inverter 32 is configured such that the voltage Vin of the input terminal IN is equal to the threshold voltage V
When it becomes higher than th, the impedance of the FET 32a becomes smaller than that of the FET 32b, so that the FET 32a is pulled down. Thus, the output signal Vo from the output terminal OUT of the inverter 32 becomes an output signal of the first logic level (for example, a low level).

When the voltage Vin of the input terminal IN becomes lower than the threshold voltage Vth, the impedance of the FET 32a becomes larger than that of the FET 32b and is pulled up, so that the output signal Vo of the output terminal OUT becomes the second logical level. (For example, high level). The input side and the output side of the inverter 23 are commonly connected to the bias node N2. Therefore, the potential on the input / output side of the inverter 23 becomes substantially the threshold voltage Vth, and a DC voltage substantially equal to the threshold voltage Vth is applied to the bias node N2. This DC voltage is supplied as a bias voltage to the input side of the inverter 32 via the terminating resistor 21 and the FET 31. Since the vicinity of the threshold voltage Vth is the point where the voltage gain is the highest in the input / output characteristics, the inverter 32 biased at this point can operate at the operating point where the input sensitivity is almost maximum.

Next, the detailed operation of the FET 31 will be described with reference to FIG. FIG. 6 shows an FET having the above standard.
At 31, when the gate and the source are commonly connected,
FIG. 4 is a diagram illustrating voltage / current characteristics between a drain and a source,
The horizontal axis shows the drain-source voltage Vds, and the vertical axis shows the drain-source current Ids. As shown in FIG. 6, when the voltage Vds is equal to or less than the negative value of the threshold voltage Vtd, the current Ids is substantially proportional to the voltage Vds. When the voltage Vds exceeds the negative value of the threshold voltage Vtd, the current Ids becomes a constant value. It turns out that it saturates. The drain of the FET 31 is connected to the input node N 1, the gate and the source are commonly connected, and connected to the input side of the inverter 32. Input node N
1 and the DC potential on the input side of the inverter 32 are both equal to the threshold voltage Vth. Therefore, the voltage / current characteristics of the FET 31 are plotted in FIG.
31 can be considered as a current.

Here, a 5 GHz sine wave input signal V is input to the input terminal 11 from a signal generator having an output impedance of 50Ω.
Consider the case where i is applied. Since the impedance is matched by the terminating resistor 21 of 50Ω, the input signal Vi
Is applied to the terminating resistor 21 without reflection or distortion. When the amplitude of the input signal Vi is smaller than the negative value of the threshold voltage Vtd, the FET 31 operates as an almost linear resistor,
The resistance value is about 250Ω. This is usually sufficiently small in this region as compared with the input impedance of the inverter 32 of 1 MΩ or more, and can be ignored, and the input signal Vi is input to the inverter 32 without attenuation. When the amplitude of the input signal Vi becomes larger than the negative value of the threshold voltage Vtd, a Schottky current flows to the input of the inverter 32 through the FET 31. However, FET31
As shown in FIG. 6, the current enters a current saturation region when the current is about 3 mA, and the current Ids does not increase even if the drain-source voltage Vds increases. That is, the input signal V
Even if the amplitude of i becomes large, the current flowing into the gate of the FET 32 a in the inverter 32 is limited by the FET 31. As a result, the electric charge stored in the gate capacitance Cg also becomes equal to or less than a certain value, and the discharge time thereof is a value that does not matter. Therefore, when the polarity of the input signal Vi is inverted to the negative side, the inverter 32 can immediately follow, and the delay time at the rise and the fall of the input signal Vi can be made substantially equal.

Next, simulation results of the input circuit shown in FIG. 1 will be described with reference to FIGS. 7 (a), 7 (b) and 8. FIGS. 7A and 7B are output signal waveform diagrams in the input circuit of FIG. 1, in which the horizontal axis is the time axis, and the vertical axis is the instantaneous value of the output signal Vo. The waveform of the output signal Vo when a 5 GHz sine wave input signal Vi is applied to the input terminal 11 is obtained by circuit simulation using a computer. Here, the power supply potential VDD
Is 2V. FIG. 7A shows the waveform of the output signal Vo when the peak value Vp of the input signal Vi is 0.5 Vp-p, and FIG. 7B shows the peak value Vp of the input signal Vi of 8 Vp-p.
Is the waveform of the output signal Vo in the case of
It can be seen that an output having a% duty ratio is obtained. FIG. 8 shows a change in the duty ratio of the output signal Vo when the input level of the input signal Vi is changed, for the conventional input circuit and the input circuit of FIG. The horizontal axis in the figure indicates the input level of the input signal Vi from -6 dBm to 22.
dBm (corresponding to a peak value of 0.25 Vp-p to 8 Vp-p), and the vertical axis indicates the duty ratio of the output signal Vo corresponding to the input level. From FIG. 8, it can be seen that the change in the duty ratio is about 20% in the conventional input circuit.
On the other hand, it can be seen that in the input circuit of the first embodiment, the change is within 5%.

As described above, in the first embodiment,
There are the following advantages. When the potential difference is below a certain value,
An element which has a constant resistance characteristic and saturates the current flowing when the potential difference exceeds a certain value, for example, a depletion-type FET 31 having a source and a gate connected in common between the input node N1 and the input side of the inverter 32 Inserted.
Thus, even when the level of the input signal Vi increases, the current flowing into the gate of the FET 32a in the inverter 32 can be limited, so that the delay time of the rise and fall of the signal in the input circuit can be made substantially equal. When this is applied to an optical communication integrated circuit or a clock input circuit that requires a wide input dynamic range, there is an advantage that the timing margin of the internal circuit can be secured and the maximum operating frequency can be increased.

Second Embodiment FIG. 9 is a circuit diagram of an input circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 are denoted by the same reference numerals. This input circuit differs from the input circuit of the first embodiment in that an impedance matching means 20A composed of only a terminating resistor 21 is provided instead of the impedance matching means 20 of FIG. Instead of providing the inverter 32A. Other configurations are the same as those in FIG. FIG. 10 is a circuit diagram of the inverter 32A in FIG. This inverter 32A is different from the inverter 32 in FIG.
ET is changed from the enhancement type FET 32a to a depletion type FET 32c whose size and performance are equal to the load type depletion type FET 32d.

Next, the operation of the input circuit shown in FIGS. 9 and 10 will be described. Input signal V input from input terminal 11
The operation for i is almost the same as in the first embodiment, but differs in the following points. Inverter 32A
Is a depletion type FET 32c for the switch FET.
Is used, the input threshold voltage Vth becomes substantially 0 V. Further, since the depletion type FET 32d having the same size and performance as the switch FET 32c is used as the load FET, the voltage gain becomes maximum at this threshold voltage Vth. The input side of the inverter 32A is grounded through the depletion-type FET 31 and the terminating resistor 21, and is in a state of being biased to 0 V equal to the threshold voltage Vth. Therefore, the inverter 32A can operate at the operating point where the input sensitivity is almost maximum. As described above, the second embodiment has substantially the same advantages as the first embodiment, and furthermore, since there is no bias inverter, power consumption can be reduced and the circuit configuration is simplified. There is an advantage that high integration is facilitated.

The present invention is not limited to the above embodiment, but can be variously modified. For example, there are the following modifications. (A) In the above embodiment, the FET 31 and the inverter 2
Although N-channel MESFETs are used for the FETs 32a, 32b and the like in 3, 31, and 32, the P-channel MESFE
T may be used. When a P-channel MESFET is used, the polarity of the power supply may be changed. (B) In the above embodiment, the current suppressing means and the waveform shaping means are constituted by the Schottky gate FETs 31, 32a and 32b, but may be constituted by using other elements such as FETs, bipolar transistors or diodes. . In addition, these elements do not need to be single elements, and a plurality of elements can be combined in series or in parallel according to a required capacity to constitute a current suppressing unit. (C) In the above embodiment, the waveform shaping means is the inverter 3
However, it is also possible to use a comparator and other circuits. (D) In the above embodiment, the impedance matching means is constituted by the terminating resistor 21. However, according to the output impedance on the input signal supply side, elements such as resistance, capacitance or inductance are combined to constitute the impedance matching means. It is also possible.

(E) The input circuit shown in FIGS. 1 and 9 may be configured such that the influence of the reflected wave due to the impedance mismatch can be neglected or the input terminal 11
If the output impedance of the input signal supply side connected to the
May be omitted. As a result, the circuit scale becomes smaller and high integration becomes easier. (F) Although the coupling capacitors 12 and 22 are provided outside the semiconductor integrated circuit in FIG. 1, the coupling capacitors may be formed in the semiconductor integrated circuit. As a result, there is an advantage that the size of the input circuit can be reduced. (G) When a signal to which a DC bias voltage corresponding to the threshold voltage Vth of the internal inverter is added is used as the input signal Vi in FIGS. 1 and 9, the input coupling capacitor 12 may be omitted. As a result, the circuit scale becomes smaller, and high integration becomes easier.

[0023]

As described in detail above, the first and fourth embodiments are described.
According to the fifth aspect of the present invention, since the current suppressing means is provided,
When the amplitude of the input signal is smaller than a certain value, the input signal is transmitted to the waveform shaping means with little attenuation, and when the amplitude of the input signal becomes larger than the certain value, the current flowing into the waveform shaping means is kept constant. It can be limited to less than the value. For this reason, the amplitude of the signal transmitted to the waveform shaping means is suppressed to an appropriate range regardless of the magnitude of the amplitude of the input signal. As a result, the waveform shaping means can perform a high-speed and reliable waveform shaping operation in which the delay time of the output signal at the time of rising and falling of the signal is substantially equal with reference to the threshold of a certain level. In addition, since the input circuit has the minimum necessary configuration including the current suppressing means and the waveform shaping means, the circuit scale can be reduced, thereby facilitating low power consumption and high integration. Further, the signal propagation delay time is reduced and the speed can be increased. For example, F
When ET is constituted by a Schottky gate FET, several GH
High-speed operation of z or more is also possible.

According to the second, sixth, and seventh aspects, since the impedance matching means is provided, substantially the same effects as those of the first aspect can be obtained, and impedance matching with the input signal supply side is achieved. I can do it. Thereby, reflection and distortion of an input signal due to impedance mismatch can be avoided, and reliable operation can be performed. For example, if the impedance matching means is constituted by a terminating resistor, impedance matching can be achieved with a simple circuit configuration. When the impedance matching means is constituted by the terminating resistor, the coupling capacitor, and the bias means, the DC bias voltage generated by the bias means is applied to the input node via the terminating resistor. For this reason, this input circuit can always operate at the optimum operating point. According to the third aspect of the present invention, since the DC removing means is further provided, substantially the same effect as that of the first aspect is obtained, and even if the DC voltage is superimposed on the input signal, the DC current is supplied to the current suppressing means. No voltage is applied.
Therefore, even if a signal biased with a DC voltage is input to this input circuit, the operating point of the current suppressing means is always kept in an optimum state, and the intended operation can be reliably performed.
Therefore, connection can be made without considering the output of the input signal supply side, and a versatile input circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an input circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional input circuit.

FIG. 3 is a circuit diagram of the inverter in FIG. 2;

FIG. 4 is an input / output signal waveform diagram of the input circuit of FIG. 2;

FIG. 5 is a circuit diagram of the inverter in FIG. 1;

FIG. 6 is a voltage / current characteristic diagram of a depletion mode FET in FIG.

7 is an output signal waveform diagram of the input circuit of FIG.

FIG. 8 is a characteristic diagram illustrating a relationship between an input signal level and a duty ratio of an output signal.

FIG. 9 is a circuit diagram of an input circuit according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram of the inverter in FIG. 9;

[Explanation of symbols]

 12, 22 Coupling capacitor 20 Impedance matching means 21 Terminating resistor 23, 32, 32A Inverter 31 Depletion type FET 40 Internal circuit N1 Input node N2 Bias node Vi Input signal Vo Output signal VDD Power supply potential VSS Ground potential

Continuation of front page (58) Field surveyed (Int.Cl. 7 , DB name) H03K 19/0175

Claims (7)

    (57) [Claims]
  1. An input signal which changes in a positive direction and a negative direction with reference to a certain level is input from an input node. When the amplitude of the input signal is smaller than a certain value, the resistance value becomes small and the input signal becomes low. A current suppressing means for passing a current substantially as it is, and when the amplitude of the input signal increases by a certain value or more, the resistance value increases to output a substantially constant current; and Means for outputting an output signal of a first logic level when the output current is larger than the threshold value, and outputting a second logic level signal different from the first logic level when the output current is smaller than the threshold value An input circuit, comprising: a waveform shaping unit that outputs a signal.
  2. 2. An input signal which changes in a positive direction and a negative direction based on a certain level is input from an input node, and when the amplitude of the input signal is smaller than a certain value, the resistance value becomes small and the input signal becomes low. A current suppressing means for passing a current substantially as it is, and when the amplitude of the input signal increases by a certain value or more, the resistance value increases to output a substantially constant current; and Means for outputting an output signal of a first logic level when the output current is larger than the threshold value, and outputting a second logic level signal different from the first logic level when the output current is smaller than the threshold value A waveform shaping unit that outputs a signal, and an impedance when the current suppressing unit is viewed from the input node is matched with an impedance when the input signal supply side is viewed from the input node. Input circuit, characterized in that the impedance matching means comprises a.
  3. 3. A DC removing means for removing a DC component from an input signal which changes in a positive direction and a negative direction on the basis of a certain level and outputting only an AC component to an input node; When the amplitude is smaller than a certain value, the resistance value decreases and the current of the signal on the input node passes almost as it is. When the amplitude of the signal on the input node becomes larger than the certain value, the resistance value increases. A current suppressing means for outputting a substantially constant current; and a threshold of the constant level, wherein an output current of the current suppressing means is inputted, and when the output current is larger than the threshold, an output of a first logic level is outputted. A signal shaping means for outputting an output signal having a second logic level different from the first logic level when the signal is smaller than the threshold value; And an impedance matching means for matching the impedance with the impedance when the DC removing means is viewed from the input node.
  4. 4. The input circuit according to claim 1, wherein the current suppressing unit includes: a drain connected to the input node; and a source and a gate commonly connected to an input side of the waveform shaping unit. When the potential difference between the drain and the source is small, it exhibits a resistance characteristic lower than the input impedance of the waveform shaping means, and when the potential difference is large, the current between the drain and the source is large. Wherein the waveform shaping means is connected between the second power supply potential of the first and second power supply potentials at different levels and an output node. A second field-effect transistor whose gate is controlled by a potential of a source of the first field-effect transistor; a second field-effect transistor connected between the first power supply potential and the output node; In a load means for outputting an output signal corresponding to the conduction state of the second field effect transistor to the output node, an input circuit, characterized by being configured.
  5. 5. The input circuit according to claim 4, wherein said first and second field-effect transistors are Schottky gate field-effect transistors.
  6. 6. The input circuit according to claim 2, wherein the impedance matching means has an impedance as viewed from the input node toward the current suppressing means.
    An input circuit comprising a terminating resistor having a resistance value matching an impedance when the input signal supply side is viewed from the input node.
  7. 7. The input circuit according to claim 2, wherein the impedance matching unit is connected between the input node and a bias node, and the current matching unit is viewed from the input node. A terminating resistor having a resistance value whose impedance matches the impedance of the input signal supply side when viewed from the input node; a coupling capacitor connecting between the bias node and a second power supply potential; And bias means for applying a DC bias voltage to the input node via the terminating resistor.
JP07300820A 1995-11-20 1995-11-20 Input circuit Expired - Fee Related JP3105435B2 (en)

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JP07300820A JP3105435B2 (en) 1995-11-20 1995-11-20 Input circuit

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JPH09148911A JPH09148911A (en) 1997-06-06
JP3105435B2 true JP3105435B2 (en) 2000-10-30

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WO2012157031A1 (en) * 2011-05-13 2012-11-22 パナソニック株式会社 Signal potential conversion circuit
EP2849344B1 (en) * 2013-09-12 2019-11-06 Socionext Inc. Circuitry and methods for use in mixed-signal circuitry
US9311973B2 (en) 2013-12-26 2016-04-12 Samsung Electronics Co., Ltd. Input buffer for semiconductor memory device and flash memory device including the same

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