JPH06140608A - Wiring design for master slice semiconductor device - Google Patents

Abstract

PURPOSE:To automatize the mask forming process of a master slice semiconductor device which can be manufactured only by a single layer mask process and remarkably reduce the number of processes. CONSTITUTION:A master slice semiconductor device is provided with a first fixed layer wiring layer 3, and a fixed through hole 5 which has a greater width than the width of the wiring layer and is regularly arranged on the first layer wiring layer 3. The through hole 5 is permitted to be the connecting point, which connects the first layer wiring layer 3 with the second layer wiring layer 6, and the cutting point of the first layer wiring layer 3, and prescribed wiring connection is provided according to the presence or absence of the second layer wiring layer 6. Then, the structure of the second layer wiring layer 6 is automatically formed by combining the data on the fixed first layer wiring layer 3 and through hole 5 with data on the wiring laid out by a tool designed for general use.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring design method for a master slice semiconductor device using two or more layers of wiring.

[0002]

2. Description of the Related Art Currently, in ASIC development, a master slice method that can realize an LSI in a short period of time is often used. Master slice IC such as gate array
Then, generally, the steps up to the metal wiring step are standard steps, and basic elements such as transistors are formed in an array on a semiconductor substrate. After the design is completed, only the metal wiring process is performed so that an LSI having a desired function can be obtained. Since the metal wiring used in this master slice method is usually formed of two or more layers, it takes 1 to 2 months to obtain an LSI through the metal wiring process. There is a demand to further shorten the metal wiring process, and several methods have been proposed.

The first method is disclosed in, for example, Japanese Patent Laid-Open Nos. 1-17.
As disclosed in Japanese Patent No. 5241, a method of customizing a first layer metal wiring as a fixed wiring by a via hole connecting the first and second layer metal wirings and a second layer metal wiring pattern, The second method is, for example, Japanese Patent Laid-Open No.
As disclosed in JP-A-244640, it is a method in which a via hole for connecting the first-layer metal wiring and the first-layer and second-layer metal wirings is used as a fixed pattern and is customized only by the second-layer metal wiring. . A method of cutting and removing the first-layer metal wiring has also been proposed.

[0004]

However, in the first method of customizing via holes and the second layer of metal wiring, the mask process needs to be performed twice, and the development period is longer than that of the normal master slice method. Not much shortened. On the other hand, in the second method of customizing only the second-layer metal wiring, the mask process is performed only once and the development period is shortened, but there is a problem that the degree of freedom of wiring is limited. Further, in both of the above two methods, the metal wiring of the first layer is a fixed length wiring, and the utilization efficiency of the wiring is not good. In addition, for the wiring for customization, the design method is not possible with a general-purpose design tool, and some wiring must be performed manually.

The present invention has been made in order to solve the above problems in the conventional master slice semiconductor device, and enables the master slice semiconductor device to be manufactured only by a masking process of one layer, and the mask making process An object of the present invention is to provide a wiring design method for a master slice semiconductor device which is automated and can shorten the development period.

[0006]

In order to solve the above problems, a wiring design method for a master slice semiconductor device according to the present invention includes a master slice cell and a plurality of first lower wiring layers arranged as fixed lower wiring layers. A wiring layer; and a plurality of through holes that are wider than the first wiring layer width and are fixedly arranged on the first wiring layer, and the through holes are formed on the first wiring layer and the second wiring layer. A connection point with the wiring layer and a cutting point of the first wiring layer, and the master is configured to connect or disconnect the first wiring layer depending on the presence or absence of the second wiring layer to obtain a predetermined wiring connection. In the slice semiconductor device, the second wiring layer structure is automatically formed by synthesizing the fixed first wiring layer and through-hole data and wiring data laid out by a general-purpose design tool. Ah .

In a master slice semiconductor device to which such a wiring design method is applied, it is possible to fabricate a semiconductor device only by a masking process of one layer, and through holes are used as connection points or disconnection points of wiring. Therefore, the length of the first wiring layer can be freely set, and the degree of freedom in design can be increased. Further, according to the wiring designing method of the present invention, the mask forming process is automated, and a semiconductor device having a desired function can be obtained in a short period of time.

[0008]

EXAMPLES Next, examples will be described. First, the configuration of a master slice semiconductor device to which the wiring design according to the present invention is applied will be described. 1A is a plan view showing a basic configuration example of a master slice semiconductor device to which the wiring design method according to the present invention is applied, and FIG.
(C) and (D) are lines A-A 'and B- in FIG.
The cross-sectional views taken along the lines B'and CC 'are shown. In the figure, 1 is a semiconductor substrate on which transistors and the like are formed, 2 is a silicon oxide film, 3 is a fixed first metal wiring layer, and 4 is an interlayer insulating film. Further, along the first-layer metal wiring layer 3, fixed through holes 5 wider than the metal wiring layer 3 are regularly arranged and formed in the interlayer insulating film 4, and the interlayer insulating film 4 is further formed. A second metal wiring layer 6 is formed on top. Then, the through hole 5 forms a connection point (via) 5a between the first and second metal wiring layers 3 and 6, and covers the second metal wiring layer 6 in the through hole 5. In the unbroken portion 5b, the first metal wiring layer 3 is cut. In addition,
7 is a protective insulating film.

As described above, in the first-layer metal wiring layer 3, the second-layer metal wiring layer 6 is formed in the through hole (via) 5a in the area actually used as the signal wiring. , The connection as wiring is maintained. Therefore, depending on the presence or absence of the pattern of the second-layer metal wiring layer 6 in the through hole 5, the connection with the first-layer metal wiring layer 3 and the cutting of the first-layer metal wiring layer 3 are performed, and it is necessary. Wiring and connections can be obtained.

In the master slice semiconductor device in which the desired wiring connection is obtained only by the presence or absence of the pattern of the second metal wiring layer 6, the wiring design of the pattern of the second metal wiring layer 6 is performed. Method becomes especially important.

FIG. 2A is a plan view showing a modification of the master slice semiconductor device shown in FIG. 1A, and FIG. 2B is a sectional view taken along the line DD '. It is a figure. In this modification, the second metal wiring layer 6 is arranged so as to be connected to the first metal wiring layer 3 and is arranged so as to intersect with the first metal wiring layer 3. It is configured to have a portion 6a, and aa 'signal wiring layers are b, c.
It shows a mode in which it intersects with the signal wiring layer. In FIG. 2A, 8 is a connection point, 9 is a via hole for connection, and 10 is a second metal wiring layer for connection. Figure 2
For comparison with this wiring mode, (C) shows a structure in which a wiring similar to that of (A) of FIG. 2 is formed by a normal two-layer wiring, and 11 is the first wiring layer, Reference numeral 12 is a second wiring layer, and 13 is a via hole.

Next, a wiring design method for wiring in the master slice semiconductor device according to the present invention shown in FIG. 2A based on the ordinary two-layer wiring shown in FIG. 2C. Will be described.

First, as shown in the flowchart of FIG. 3, the data of the fixed first metal wiring layer 3 and the fixed through holes 5 and the layout of FIG. 2C laid out by a general-purpose design tool are shown. The data of the first wiring layer 11, the second wiring layer 12, and the via hole 13 is read into a storage device or the like. Next, in order to recognize the connection point 8, the data of the fixed through hole 5 and the data of the first wiring layer 11 are read from the above data, and the logical product of these data is obtained. Next, the data of the fixed through hole 5 including the data of the connection point 8 thus obtained is calculated to obtain the data of the connection via hole 9. Further, in order to satisfy the design rule, oversize is performed to obtain the data of the second wiring layer 10 for connection. Then, the second metal wiring layer 6 is automatically calculated from the logical sum of the data of the second connection wiring layer 10 and the data of the second wiring layer 12.

Next, an embodiment in which the present invention is applied to a channel type CMOS gate array will be described. First, a normal channel type CMOS gate array is shown in FIG. This gate array is composed of a cell region 21 in which basic cells (transistors) are regularly arranged, a wiring region 22 and an input / output region 23. FIG. 5 is a plan view showing the basic cell 31.
The basic cell 31 usually has two PMOS transistors and two
It is composed of a pair of NMOS transistors, P
A connection terminal 34 to the type diffusion layer 32 and the N-type diffusion layer 33 and a connection terminal 36 to the polysilicon gate electrode 35 are provided. Therefore, the basic cell 31 has five connection terminals for the upper and lower wiring regions, respectively. It has a connection terminal.

FIG. 6 shows a structure in which the basic structure shown in FIGS. 1 and 2 is applied to the wiring region 22 of the CMOS gate array having such a structure. In the figure, 40 is a basic cell, 41 is a cell region, 42 is a wiring region, 43 is a contact (connection point) from the cell region 41, 44 is a fixed first metal wiring layer, and 45 is a second layer.
A wiring track through which the second metal wiring layer can pass, and 46 are fixed through holes. 7 is a modification of the configuration shown in FIG. 6, in which wiring tracks 45 for the second metal wiring layer are provided between the basic cells 40 as shown.

In the wiring region thus constructed, the wiring design method according to the present invention is used, for example, as shown in FIG.
As shown in, the AA signal wiring layer, the BB signal wiring layer,
A case of forming the CC signal wiring layer will be described. First, as shown in the flowchart of FIG. 3, the data of the fixed first layer metal wiring layer 44 and the fixed through holes 46, and the wiring for wiring obtained by the general-purpose design tool shown in FIG. The layout data of the first wiring layer 51, the second wiring layer 52, and the via holes 53 is input to a storage device or the like. Fixed through hole 46 to find connection point 61
And the data of the first wiring layer 51 are obtained and output. Next, in order to obtain the connection via hole 62, the fixed through hole 46 including the data of the connection point 61 obtained in the previous step is obtained and output. An arrangement mode of the connection points 61 and the connection via holes 62 thus obtained on the wiring region shown in FIG. 8A is shown in FIG. 8C.

Then, in order to satisfy the design rule,
The connecting via hole 62 is oversized to obtain the connecting second wiring layer 63. FIG. 8D shows an arrangement mode of the second connection wiring layer 63. Finally, the logical sum of the data of the second wiring layer 63 for connection and the data of the second wiring layer 52 is obtained to obtain the necessary second wiring layer as shown in FIG. 8E. Data of the wiring layer 64 can be obtained. In FIG. 8 (E), the portions of the second wiring layer 64 for wiring, the second wiring layer 63 for connection, and the data, which are indicated by crosses, overlap the data of the second wiring layer design. If the data is increased so as to be thicker than the minimum line width in the rule, the data of the second wiring layer 64 for this wiring directly becomes the mask data for forming the semiconductor device having the desired wiring function. .

In the above description, the method of manually thickening the overlapped portion of the data indicated by X in FIG. 8E has been described, but the second layer output from the first general-purpose design tool is described. Even if a portion of the wiring layer 52 having a thicker line width for forming a via hole is made to have a larger margin and is then logically ORed with the second wiring layer 63 for connection to be combined, Set it so that it is thicker than the minimum line width.
As a result, a series of logic synthesis flows can be automated by a program.

[0019]

As described above on the basis of the embodiments,
According to the present invention, in a master slice semiconductor device which can be manufactured only by a masking process of one layer, a masking process can be automated, a man-hour can be significantly reduced, and a semiconductor device having a desired function can be obtained in a short time. Obtainable.

[Brief description of drawings]

FIG. 1 is a plan view and a cross-sectional view showing a basic configuration example of a master slice semiconductor device to which a wiring design method according to the present invention is applied.

FIG. 2 is a diagram showing a modified example of the configuration example shown in FIG. 1 and a wiring portion having a normal two-layer wiring configuration corresponding thereto.

FIG. 3 is a flowchart for explaining an embodiment of a wiring design method for a master slice semiconductor device according to the present invention.

FIG. 4 is a schematic diagram showing a channel type CMOS gate array.

FIG. 5 is a plan view showing a basic cell of a channel type CMOS gate array.

6 is a diagram showing a mode in which the wiring configuration shown in FIG. 1 or 2 is applied to the wiring region of the channel type CMOS gate array shown in FIG.

FIG. 7 is a diagram showing a modification of the wiring mode shown in FIG.

FIG. 8 is an explanatory diagram when the wiring design method according to the present invention is applied to the wiring region shown in FIG. 6 or FIG.

[Explanation of symbols]

 1 semiconductor substrate 2 silicon oxide film 3 fixed first layer metal wiring layer 4 interlayer insulating film 5 through hole 5 6 second layer metal wiring layer 7 protective insulating film 8 connection point 9 connection via hole 10 connection second layer Eye metal wiring layer

Claims (3)

[Claims] 1. A master slice cell, a plurality of first wiring layers arranged as fixed lower wiring layers, and a fixed arrangement which is wider than the first wiring layer width and is regularly arranged on the first wiring layer. A plurality of through holes, which are used as connection points between the first wiring layer and the second wiring layer and cutting points of the first wiring layer, depending on the presence or absence of the second wiring layer. In a master slice semiconductor device configured to connect or disconnect the first wiring layer to obtain a predetermined wiring connection, the second wiring layer structure is used as data of the fixed first wiring layer and through holes. A wiring design method for a master slice semiconductor device, which is automatically formed by combining with wiring data laid out by a general-purpose design tool. 2. A second connection for connection to the first wiring layer
2. The wiring design method for a master slice semiconductor device according to claim 1, wherein the wiring structure is obtained by oversizing the logical product of the wiring data and the data of the fixed through hole. 3. One between the fixed adjacent through holes.
3. The wiring design method for a master slice semiconductor device according to claim 1, wherein the second wiring layer track of the book is provided in a direction orthogonal to the first wiring layer.