JPH06139066A - Digital signal processor - Google Patents

Abstract

PURPOSE:To rewrite a RAM without interrupting audio signal output in audio signal processing. CONSTITUTION:Instruction RAMs 16, 17 are provided. Program counters 12, 13 are provided. Multiplexers 14, 15 to switch the outputs of the program counters 12, 13 and the inputs of the instruction RAMs 16, 17 are provided. The multiplexer 18 to switch the outputs of the instruction RAMs 16, 17 is provided. While the arithmetic processing of input data is executed in conformity with processing sequence by an instruction code stored in one of the instruction RAMs 16, 17, the rewriting of the instruction RAM of the other side is executed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to digital signal processors, and more particularly to digital signal processors for audio signal processing.

[0002]

2. Description of the Related Art A conventional digital signal processor 3 for audio signal processing is, as shown in FIG. 4, an interface for inputting a control signal input IC from an external control microprocessor 2 and for internally supplying control signals and data. A circuit 31, a program counter 32 for controlling a sequence of instructions, and an instruction RA for outputting an instruction code whose address is designated by the program counter 32
M16, an instruction decoder 19 for receiving the output CM from the instruction RAM 16 and converting it into a micro control signal, and an arithmetic circuit for processing the data from the data input ID by the output M of the instruction decoder 19 and outputting the arithmetic result to the data output OD. Two
It was configured with 0 and.

Next, the operation of the conventional digital signal processor will be described.

First, the control signal input IC from the microprocessor 2 receives an address signal A, an instruction code signal SM, a standby signal SS,
Digital signal processor 3 as write signal W
Is entered inside. Of these signals, the standby signal SS controls the operation stop of the arithmetic circuit 20. Also,
The address signal A indicates an address when rewriting the instruction RAM 16 is executed. Further, the instruction code signal SM becomes rewriting data to the instruction RAM 16. Further, the write signal W gives a write pulse to the instruction RAM 16.

FIG. 5 is a time chart showing the operation of the digital signal processor 3 of FIG. 4, and the operation will be described based on this.

First, in the conventional digital signal processor 3, there are two states, which are the standby signal S
Controlled by S.

In the first state, the standby signal SS is in the active state, the arithmetic circuit 20 is stopped because the output CM from the instruction decoder 19 is prohibited, and the instruction RAM
16 is rewritable from the external microprocessor 2 via the interface circuit 31. This state is shown as state 1 in FIG. More specifically, when the standby signal SS is "1", the program start signal SP becomes invalid, the program counter 32 and the instruction RAM 16 are controlled by the external microprocessor 2 via the interface circuit 31, and the control signal at this time is controlled. Control signals and data are given as address signal A, instruction code signal SM, and write signal W. At the same time, the decoding of the instruction decoder 19 is prohibited by the standby signal SS, so that the arithmetic circuit 20 is stopped. In this state, the external microprocessor 2 can write a desired instruction code into the instruction RAM 16 at an arbitrary address.

Next, in the second state, when the standby signal SS is inactive, the arithmetic circuit 20 changes from the data input ID according to the sequence controlled by the instruction code in the instruction RAM 16 written in the first state. Is executed, and a series of data processing of outputting the operation result to the data output OD is executed. This state is shown as state 2 in FIG.

When the standby signal SS becomes "0", the program counter 32 and the instruction RAM 16 are controlled by the outputs M and Mb of the instruction decoder 19. This execution sequence is started by the program start signal SP, and a series of processing is performed by the next program start signal S.
It ends before P pulses are applied. This cycle is 1
If it is called a processing cycle, an instruction RA is applied to the input data obtained in the data input ID in each processing cycle.
The data processing is repeated according to the same processing sequence created by the instruction code stored in M16.

As described above, the conventional digital signal processor 3 can perform desired data processing on the input data from the data input AD according to the instruction code stored in the instruction RAM 16.

[0011]

In this conventional digital signal processor, when an attempt is made to change the data processing sequence, the contents of the instruction RAM are always rewritten as the state 1, so that the arithmetic circuit can be operated until the rewriting is completed. However, when applied to audio signal processing, the sound is interrupted.

[0012]

SUMMARY OF THE INVENTION A digital signal processor of the present invention is a memory output selection that selects the rewritable first and second memories and the output of one of the first and second memories. Means, decoding means for decoding the output of the memory output selecting means and outputting a micro control signal, a first program counter controlled by the micro control signal, and a second program counter controlled by an external control signal. A program counter and one of the outputs of the first and second program counters are selected and applied to an address input of one of the first and second memories, and the output of the first and second program counters is selected. Address selecting means for selecting the other output and applying it to the other address input of the first and second memories; And a data input means for supplying data to the data input of the second memory, and a write pulse input means for selecting one of the first and second memories and inputting a write pulse. ing.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a digital signal processor of the present invention.

Digital signal processor 1 of the present invention
Is an interface circuit 11 that receives a control signal IC from an external microprocessor 2 as an input and outputs an address signal A, an instruction code signal SM, a switching signal SX, write signals W1 and W2, and a program start signal SP is connected to a reset input. Output Mb from the instruction decoder 19 described later.
And a program counter 13 controlled by the address signal A
, A multiplexer 14 which inputs the outputs P1 and P2 of the program counters 12 and 13 and selects one by the switching signal SX, and an output P of the program counters 12 and 13.
1 and P2 are input to select the other of the multiplexers 14 by the switching signal SX, and the output X1 of the multiplexer 14 is connected to the address input, the instruction code signal SM is connected to the data input, and the write signal is input. Instruction RAM with W1 connected to write pulse input
16 and an instruction RAM in which the output X2 of the multiplexer 15 is connected to the address input, the instruction code signal SM is connected to the data input, and the write signal W2 is connected to the write pulse input.
17 and the output CM1 of each of the instruction RAMs 16 and 17
A multiplexer 18 which inputs CM2 and selects one by a switching signal SX, and an output CM of the multiplexer 18.
An instruction decoder 19 for inputting X and an arithmetic circuit 20 for arithmetically processing the data controlled by the output M of the instruction decoder 19 and inputted from the data input ID and outputting the arithmetic result to the data output OD are configured. .

2 and 3 are time charts showing an example of the operation of the circuit of this embodiment shown in FIG. 1, and the operation will be described below based on this.

First, a method of controlling the program counters 12 and 13 will be described. The program counter 11 is controlled by the output Mb of the instruction decoder 19 and initialized by the program start signal SP, while the program counter 12 is controlled by the address signal A from the interface circuit 11. That is, the program counter 11 is controlled by instruction execution, and the program counter 14 is controlled by the multiprocessor 2 via the interface circuit 3.

First, FIG. 2 shows a case where the switching signal SX is set to "0". When the multiplexer 14 selects the output P1 of the program counter 12, the instruction RAM 1
The address of 6 is designated by the program counter 12,
The multiplexer 15 outputs the output P of the program counter 13.
By selecting 2, the address of the instruction RAM 17 is designated by the program counter 13. When the multiplexer 18 selects the output CM1 of the instruction RAM 16, the instruction decoder 19 decodes the output CM1, and the output M causes the arithmetic circuit 20 to perform arithmetic processing on the data input ID, and the output is used as the data output OD. Output. Further, the instruction decoder output Mb controls the program counter 12. That is, the processing sequence of instructions within one processing cycle is executed according to the control system of program counter 12 → first instruction RAM 1 → instruction decoder 19 → program counter 12.
That is, in this case, according to the processing sequence created by the instruction code stored in the instruction RAM 16, the data input AD
Is performed every time the program start signal SP is input. Here, the instruction RAM 17 is instructed by the program counter 13 at its address, and by applying the write signal W2, the instruction code signal S
It is possible to write the instruction code of M to a desired address. That is, the instruction code can be rewritten to the instruction RAM 17 from the external microprocessor 2 via the interface circuit 11.

Next, FIG. 3 shows a case where the switching signal SX is set to "1", and the multiplexer 14 causes the program counter 13 to operate.
The address of the instruction RAM 16 is instructed from the program counter 13 by selecting the output P2 of the program counter 16, and the address of the instruction RAM 17 is instructed from the program counter 12 by the multiplexer 15 selecting the output X1 of the program counter 16. Also multiplexer 1
8 selects the output CM2 of the instruction RAM 17, the instruction decoder 19 decodes the output CM2 of the instruction RAM 17, and the output M causes the arithmetic circuit 20 to perform arithmetic processing on the data input ID and output the output to the data output OD. Output as. Further, the program counter 12 is controlled by the instruction decoder output Mb, that is, the processing sequence of instructions within one processing cycle is as follows: program counter 12 → instruction RAM 17 → instruction decoder 19 →
It is executed according to a control system called a program counter 12. That is, in this case, according to the processing sequence created by the instruction code stored in the instruction RAM 17, the data input I
The process for D is executed every time the program start signal SP is input.

Here, the instruction RAM 16 can write the instruction code of the instruction code signal SM to a desired address by instructing the address by the program counter 13 and further applying the write signal W1. That is, the instruction code can be rewritten to the instruction RAM 16 from the external microprocessor 2 via the interface circuit 11.

[0021]

As described above, the digital signal processor of the present invention is provided with the first or second instruction RAM.
While executing the arithmetic processing of the input data according to the processing sequence created by the instruction code stored in one of the two, the other instruction RAM can be rewritten from the external microprocessor via the interface circuit. Since there is no need to temporarily stop the arithmetic circuit for rewriting the instruction code, there is an effect that the instruction code can be rewritten without interrupting the sound of the audio signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital signal processor of the present invention.

FIG. 2 is a time chart showing another example of the operation of the digital signal processor of this embodiment.

FIG. 3 is a time chart showing another example of the operation of the digital signal processor of this embodiment.

FIG. 4 is a block diagram showing an example of a conventional digital signal processor.

FIG. 5 is a time chart showing an example of operation in a conventional digital signal processor.

[Explanation of symbols]

 1,3 Digital signal processor 2 Microcomputer 11,31 Interface circuit 12,13,32 Program counter 14,15,18 Multiplexer 16,17 Instruction RAM 19 Instruction decoder 20 Operation circuit

Claims (1)

[Claims] 1. Rewritable first and second memories, memory output selection means for selecting one of the outputs of the first and second memories, and decoding the output of the memory output selection means. Decoding means for outputting a micro control signal, a first program counter controlled by the micro control signal, a second program counter controlled by an external control signal, the first and second programs The output of one of the counters is selected and applied to the address input of one of the first and second memories, and the output of the other one of the first and second program counters is selected. Address selection means for applying to the other one of the address inputs of the second memory, and a device for supplying data to the data inputs of the first and second memories. A digital signal processor, comprising: a data input means; and a write pulse input means for selecting one of the first and second memories and inputting a write pulse.