JPH0613260A - Multilayered ceramic porcelain element - Google Patents
Multilayered ceramic porcelain elementInfo
- Publication number
- JPH0613260A JPH0613260A JP4168841A JP16884192A JPH0613260A JP H0613260 A JPH0613260 A JP H0613260A JP 4168841 A JP4168841 A JP 4168841A JP 16884192 A JP16884192 A JP 16884192A JP H0613260 A JPH0613260 A JP H0613260A
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- Prior art keywords
- electrode
- porcelain element
- ceramic porcelain
- shape
- layer
- Prior art date
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- Thermistors And Varistors (AREA)
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、電子機器や電気機器で
発生するノイズ、パルス、静電気などの異常高電圧、高
周波ノイズからIC,LSIなどの半導体素子および電
子機器や電気機器の回路を保護する目的で使用される積
層セラミック磁器素子に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention protects semiconductor elements such as ICs and LSIs and circuits of electronic devices and electric devices from abnormal high voltage such as noise, pulse and static electricity generated in electronic devices and electric devices and high frequency noise. The present invention relates to a laminated ceramic porcelain element used for the purpose.
【0002】[0002]
【従来の技術】近年電子機器や電気機器は小型化、多機
能化を実現するためにIC,LSIなどの半導体素子が
広く用いられ、それに伴って電子機器や電気機器のノイ
ズ、パルス、静電気などの異常高電圧に対する耐力は低
下している。そこでこれら電子機器や電気機器のノイ
ズ、パルス、静電気などの異常高電圧に対する耐力を確
保するためにフィルムコンデンサ、電解コンデンサ、半
導体セラミックコンデンサ、積層セラミックコンデンサ
などが用いられているが、これらは電圧の比較的低いノ
イズや高周波ノイズの吸収、抑制には優れた特性を示す
が、高い電圧のパルスや静電気に対してはその効果を示
さず、半導体素子の誤動作や破壊を引き起こすことがあ
る。2. Description of the Related Art In recent years, semiconductor devices such as ICs and LSIs have been widely used for electronic devices and electric devices in order to realize miniaturization and multifunctional functions. The withstand voltage against abnormally high voltage is low. Therefore, film capacitors, electrolytic capacitors, semiconductor ceramic capacitors, monolithic ceramic capacitors, etc. are used to secure the resistance to abnormally high voltage such as noise, pulse, and static electricity of these electronic devices and electric devices. Although it exhibits excellent characteristics for absorbing and suppressing relatively low noise and high frequency noise, it does not show its effect for high voltage pulses and static electricity, and may cause malfunction or destruction of semiconductor elements.
【0003】また高い電圧のパルスや静電気を吸収、抑
制するためにはSiC,ZnO系バリスタが用いられて
いるが、これらは電圧の比較的低いノイズや高周波ノイ
ズの吸収、抑制には効果を示さず半導体素子の誤動作を
引き起こすことがあり、これら両者の欠点を補完するも
のとして特開昭57−27001号公報、特開昭57−
35303号公報に開示されているようなSrTiO3
系バリスタが開発され使用されている。Further, SiC and ZnO type varistors are used for absorbing and suppressing high voltage pulses and static electricity, but these are effective for absorbing and suppressing noise with relatively low voltage and high frequency noise. However, it may cause a malfunction of the semiconductor device, and as a complement to these two defects, JP-A-57-27001 and JP-A-57-57
SrTiO 3 as disclosed in Japanese Patent No. 35303
Varistors have been developed and are in use.
【0004】一方電子部品の分野においては、機器の小
型化に対応して軽薄短小化、高性能化がますます進み面
実装可能なチップ部品の開発が必要不可欠になってきて
いる。これらに対応して特開昭54−53248号公
報、特開昭54−53250号公報などに開示された内
容を応用した例や、特開昭59−215701号公報、
特開昭63−219115号公報に開示された例がある
が、これらの方法はプロセス的に複雑であったり、得ら
れた特性が目的を達成するのに不十分であったりして未
だに実用化の段階に達していない。そこで我々発明者は
特願平1−86243号公報に新しい組成及び新しい製
造方法により実用化可能な方法を開示した。On the other hand, in the field of electronic components, development of chip components which can be surface-mounted has become indispensable due to further progress in lightness, thinness, shortness and high performance in response to the miniaturization of equipment. Corresponding to these, examples in which the contents disclosed in JP-A-54-53248 and JP-A-54-53250 are applied, JP-A-59-215701,
There is an example disclosed in Japanese Patent Laid-Open No. 63-219115, but these methods are still in practical use because they are complicated in process and the obtained characteristics are insufficient for achieving the purpose. Has not reached the stage. Therefore, the inventors of the present invention disclosed in Japanese Patent Application No. 1-86243 a method that can be put to practical use by a new composition and a new manufacturing method.
【0005】[0005]
【発明が解決しようとする課題】従来、積層型SrTi
O3系バリスタに関しては前記従来例で示したように様
々な材料組成、製造方法が開発されてきたが、いずれの
場合もプロセス的に複雑であったりして実用化のレベル
に達していないという問題点を有していた。また得られ
た素子の特性は電源ラインに加わる高い電圧のパルスや
静電気を吸収、抑制するのにはその効果を示すが、信号
ラインの加わる高周波ノイズの吸収、抑制には効果を示
さないといった問題点を有していた。[Problems to be Solved by the Invention] Conventionally, laminated SrTi
As for the O 3 -based varistor, various material compositions and manufacturing methods have been developed as shown in the above-mentioned conventional example, but in any case, it is not reached the level of practical use due to the complicated process. I had a problem. Also, the characteristics of the obtained device show its effect in absorbing and suppressing high voltage pulses and static electricity applied to the power supply line, but not in absorbing and suppressing high frequency noise applied to the signal line. Had a point.
【0006】本発明は前記従来の問題点を解決するもの
で、信号ラインに加わる高周波ノイズの吸収、抑制が可
能で静電気パルスなどの異常電圧が加わっても壊れず、
耐環境特性、特に耐湿性に優れた積層セラミック磁器素
子を得ることを目的とするものである。The present invention solves the above-mentioned conventional problems and is capable of absorbing and suppressing high-frequency noise applied to a signal line, and does not break even when an abnormal voltage such as an electrostatic pulse is applied.
It is an object of the present invention to obtain a laminated ceramic porcelain element having excellent environment resistance characteristics, particularly moisture resistance.
【0007】[0007]
【課題を解決するための手段】本発明の積層セラミック
磁器素子はセラミック層と内部電極層が交互に積層され
るように2層の内部電極層を設け、この2層の内部電極
層のそれぞれの一端を対向する外部電極に接続し、最上
層と最下層のセラミック層の厚みの合計が前記内部電極
層によって挟まれるセラミック層の厚みより大きく構成
することにより前記の問題点を解決しようとするもので
ある。The laminated ceramic porcelain element of the present invention is provided with two internal electrode layers such that ceramic layers and internal electrode layers are alternately laminated, and each of the two internal electrode layers is provided. An object of the present invention is to solve the above-mentioned problems by connecting one end to an opposing external electrode and making the total thickness of the uppermost and lowermost ceramic layers larger than the thickness of the ceramic layers sandwiched by the internal electrode layers. Is.
【0008】[0008]
【作用】この構成によれば、積層セラミック磁器素子の
セラミック層と内部電極層が交互に積層され前記内部電
極層によって挟まれるセラミック層が1層だけであるた
め電極間距離を大きくでき静電容量を小さくすることが
できる。また、前記積層セラミック磁器素子の最上層と
最下層のセラミック層の厚みの合計が前記内部電極層に
よって挟まれるセラミック層の厚みより大きくすること
により電極の両端に加わる電圧は前記内部電極層によっ
て挟まれるセラミック層に加わり、前記積層セラミック
磁器素子の表面をリークすることはなく前記積層セラミ
ック磁器素子を機能させることができる。According to this structure, since the ceramic layers and the internal electrode layers of the laminated ceramic porcelain element are alternately laminated and only one ceramic layer is sandwiched between the internal electrode layers, the distance between the electrodes can be increased and the capacitance can be increased. Can be made smaller. The total thickness of the uppermost and lowermost ceramic layers of the multilayer ceramic porcelain element is made larger than the thickness of the ceramic layers sandwiched by the internal electrode layers, so that the voltage applied across the electrodes is sandwiched by the internal electrode layers. The laminated ceramic porcelain element can be made to function without leaking to the surface of the laminated ceramic porcelain element in addition to the ceramic layer.
【0009】また、内部電極層の形状を種々変えること
により有効電極面積を使用目的に応じて変えることがで
き、電極間距離を大きくし有効電極面積を小さくするこ
とにより静電容量を小さくすることができる。Further, the effective electrode area can be changed according to the purpose of use by variously changing the shape of the internal electrode layer, and the electrostatic capacitance can be reduced by increasing the distance between the electrodes and decreasing the effective electrode area. You can
【0010】これにより静電容量が小さくなるのに伴い
ノイズ減衰率が最大になる共振周波数を高くすることが
でき、信号ラインに乗ってくる高周波ノイズを吸収、抑
制することができる。また、有効電極面の形状を種々変
えることにより静電容量を変えることなく吸収できるノ
イズエネルギーの大きさを調節することができる。As a result, it is possible to increase the resonance frequency at which the noise attenuation rate is maximized as the electrostatic capacitance becomes smaller, and it is possible to absorb and suppress the high frequency noise riding on the signal line. Further, by varying the shape of the effective electrode surface, the amount of noise energy that can be absorbed can be adjusted without changing the electrostatic capacitance.
【0011】さらに、セラミック層の主成分をSrTi
O3または前記SrTiO3のSrの一部をCa,Mg,
Baのうちの少なくとも一つ以上の元素で置換したもの
を用いることにより、コンデンサとバリスタの両方の特
性を持たせることができる。これにより静電気パルスな
どの立ち上がりが急峻な異常高電圧が印加されても同素
子が破壊することがなくなる。Further, the main component of the ceramic layer is SrTi.
O 3 or part of Sr of the SrTiO 3 is replaced with Ca, Mg,
By using a material in which at least one element of Ba is substituted, both characteristics of the capacitor and the varistor can be provided. This prevents the element from being destroyed even when an abnormally high voltage such as an electrostatic pulse having a sharp rise is applied.
【0012】また、このようにして作られた積層セラミ
ック磁器素子の表面、内部のいずれかまたは両方に主成
分がSi,Al,Tiのうち少なくとも一つ以上からな
るコーティング剤で被膜を形成することにより均一で緻
密な被膜が得られることから耐環境特性、特に耐湿特性
を著しく改善することができる。Further, a coating film may be formed on the surface, inside or both of the thus-produced multilayer ceramic porcelain element with a coating agent whose main component is at least one of Si, Al and Ti. As a result, a uniform and dense coating film can be obtained, so that the environment resistance characteristics, especially the humidity resistance characteristics can be remarkably improved.
【0013】[0013]
【実施例】(実施例1)以下に実施例を挙げて具体的に
説明する。Embodiments (Embodiment 1) Hereinafter, embodiments will be specifically described.
【0014】まず、第1成分としてSrCO3、CaC
O3、TiO2を(Sr0.98Ca0.02)0.995TiO3の組
成比になるようにして99.2モル%、第2成分として
Nb 2O5を0.3モル%、第3成分としてMnCO3を
0.2モル%、Cr2O3を0.1モル%、第4成分とし
てSiO2を0.2モル%秤量し、ボールミルなどによ
り20Hr混合、粉砕し、乾燥した後空気中で800℃
で2Hr仮焼し、再びボールミルなどにより80Hr混
合、粉砕し平均粒径が1.0μm以下になるようにす
る。こうして得られた粉末にブチラール系樹脂などの有
機バインダーと有機溶剤を混合してスラリー状とし、ド
クター・ブレード法などのシート成形法により厚さ50
μm程度のグリーンシート1を得る。First, SrCO is used as the first component.3, CaC
O3, TiO2(Sr0.98Ca0.02)0.995TiO3Set of
99.2 mol% as a composition ratio, as the second component
Nb 2OFive0.3 mol% and MnCO as the third component3To
0.2 mol%, Cr2O30.1 mol% as the fourth component
SiO20.2 mol% is weighed and measured by a ball mill or the like.
20Hr mixed, crushed and dried, then 800 ℃ in air
Calcination for 2 hours with 80Hr mixing again with a ball mill etc.
If so, pulverize so that the average particle size is 1.0 μm or less.
It The powder thus obtained may contain butyral resin, etc.
Machine binder and organic solvent are mixed to form a slurry,
Thickness of 50 by sheet forming method such as K.Blade method
A green sheet 1 of about μm is obtained.
【0015】次に、前記シート1を所定の枚数積層して
図1ならびに図2に示す最下層の無効層1bを形成し、
その上にPdなどからなる一方の電極が長方形である形
状の内部電極3aをスクリーン印刷などにより印刷、乾
燥し、さらにその上に前記シート1を所定枚数積層した
後、Pdなどからなる他方の電極が外部電極4に接続さ
れる部分を底辺とする三角形である形状の内部電極3b
をスクリーン印刷などにより印刷、乾燥する。その際、
内部電極3aならびに3bは対向して相異なる端縁に至
るように印刷する。最後に前記シート1を所定枚数積層
して最上層の無効層1aを形成し、加熱しながら加圧、
圧着し、所定の形状に切断する。Next, a predetermined number of the sheets 1 are laminated to form the bottom invalid layer 1b shown in FIGS. 1 and 2.
The inner electrode 3a, which is made of Pd or the like and has a rectangular shape, is printed and dried by screen printing or the like, and a predetermined number of the sheets 1 are stacked on the inner electrode 3a. The inner electrode 3b in the shape of a triangle whose base is a portion connected to the outer electrode 4.
Is printed by screen printing and dried. that time,
The internal electrodes 3a and 3b are printed so as to face each other and reach different edges. Finally, a predetermined number of the sheets 1 are laminated to form the uppermost ineffective layer 1a, and pressure is applied while heating,
Crimping and cutting into a predetermined shape.
【0016】次に空気中で800℃で20Hr脱脂仮焼
し、例えばN2:H2=9:1の還元性雰囲気中で121
0℃で10Hr焼成した後、空気中で930℃で2Hr
再酸化する。その後、内部電極3a,3bを異なる端縁
に露出させた両端面にAgなどからなる外部電極ペース
トを塗布し、空気中で700℃で10分焼成する。次に
前記外部電極上にたとえば電解法でNiメッキさらに半
田メッキを施して外部電極4を形成する。[0016] Next, degreasing calcining is performed in air at 800 ° C for 20 hours, and for example 121 in a reducing atmosphere of N 2 : H 2 = 9: 1.
After baking for 10 hours at 0 ° C, 2 hours at 930 ° C in air
Reoxidize. After that, an external electrode paste made of Ag or the like is applied to both end surfaces of the internal electrodes 3a and 3b exposed at different edges, and the paste is baked in air at 700 ° C. for 10 minutes. Next, the external electrode 4 is formed on the external electrode by electroplating, for example, Ni plating and solder plating.
【0017】このようにして得られた積層セラミック磁
器素子の初期特性および信頼性試験の結果を(表1)に
示す。また図1,図2は本実施例のシートの積層構成を
示す図である。図1において1はシート、3は内部電
極、4は外部電極である。The initial characteristics and reliability test results of the thus-obtained monolithic ceramic porcelain element are shown in Table 1. 1 and 2 are views showing the laminated structure of the sheets of this embodiment. In FIG. 1, 1 is a sheet, 3 is an internal electrode, and 4 is an external electrode.
【0018】[0018]
【表1】 [Table 1]
【0019】(実施例2)以下、本発明の第2の実施例
を図3,図4を用いて説明する。(Second Embodiment) A second embodiment of the present invention will be described below with reference to FIGS.
【0020】前記実施例1と同様にして内部電極層3
a,3cの形状が一方の電極が長方形で、他方の電極が
外部電極に接続される部分を底辺とし他の二辺が内部に
湾曲した曲線からなる略三角形である積層セラミック磁
器素子を得た後、外部電極4の部分に有機物系のレジス
トを塗布した後乾燥し、Siを主成分とするアルコキシ
ド溶液からなるコーティング剤に前記積層セラミック磁
器素子をディップし、100℃で予備乾燥した後トルエ
ンなどの有機溶剤等に浸漬し前記レジストを溶解除去
し、その後450℃で20分焼き付けて被膜5a,5b
を形成する。次に前記外部電極上にたとえば電解法でN
iメッキさらに半田メッキを施す。The internal electrode layer 3 was formed in the same manner as in Example 1.
A monolithic ceramic porcelain element was obtained in which a and 3c had a substantially rectangular shape in which one electrode had a rectangular shape and the other electrode had a base portion where the other electrode was connected to the external electrode and the other two sides had a curved curve inward. After that, an organic-based resist is applied to the external electrodes 4 and then dried, and the laminated ceramic porcelain element is dipped in a coating agent composed of an alkoxide solution containing Si as a main component, pre-dried at 100 ° C., and then toluene or the like. The above resist is dissolved and removed by immersing in the organic solvent, etc., and then baked at 450 ° C. for 20 minutes to form the coatings 5a and 5b.
To form. Next, N is formed on the external electrode by, for example, an electrolytic method.
i plating and solder plating are applied.
【0021】このようにして得られた積層セラミック磁
器素子の初期特性および信頼性試験の結果を(表2)に
示す。また図3,図4は本実施例の積層セラミック磁器
素子の断面図である。図3において5a,5bはコーテ
ィング剤によって形成された被膜である。The results of the initial characteristics and reliability test of the thus-obtained monolithic ceramic porcelain element are shown in Table 2. 3 and 4 are sectional views of the laminated ceramic porcelain element of this embodiment. In FIG. 3, 5a and 5b are coating films formed by a coating agent.
【0022】[0022]
【表2】 [Table 2]
【0023】なお、本実施例ではセラミック粉体の組成
については一部の組合せについてのみ示したが、SrT
iO3を主成分としコンデンサとバリスタの両方の機能
を有するものであればどのような組成であってもかまわ
ない。また、無効層1a,1bおよび有効層2は薄いシ
ート1を積層して形成したが、厚いシート1枚で形成し
てもかまわない。In this example, the composition of the ceramic powder is shown only for some combinations, but SrT
Any composition may be used as long as it has a function of both a capacitor and a varistor and has iO 3 as a main component. Further, the ineffective layers 1a and 1b and the effective layer 2 are formed by laminating thin sheets 1, but one thick sheet may be formed.
【0024】また、本実施例で示した内部電極3a,3
b,3cおよび外部電極4はPdやAgといった貴金属
だけでなく、CuやNi,Crといった非金属および非
金属の酸化物やそれらの混合物であってもかまわない。Further, the internal electrodes 3a, 3 shown in this embodiment are
b, 3c and the external electrode 4 may be not only a noble metal such as Pd or Ag but also a non-metal or non-metal oxide such as Cu, Ni or Cr, or a mixture thereof.
【0025】また電気的特性については、前記積層セラ
ミック磁器素子に0.1mAの電流が流れた時に素子の
両端に加わる電圧をV0.1mAで示し、静電容量およびta
nδは1kHzで測定した値を示した。また、信頼性試験
については85℃、85RH%、課電率90%、500
時間後の変化率を示した。ここで課電率とは素子に印加
する電圧を素子の持つ初期のV0.1mAで割った値のこと
である。Regarding the electrical characteristics, the voltage applied across the element when a current of 0.1 mA flows through the monolithic ceramic porcelain element is represented by V 0.1 mA , and the capacitance and ta
nδ is a value measured at 1 kHz. Moreover, regarding the reliability test, 85 ° C., 85 RH%, charge rate 90%, 500
The change rate after time is shown. Here, the charge rate is a value obtained by dividing the voltage applied to the element by the initial V 0.1 mA of the element.
【0026】なお、本実施例で示した積層セラミック磁
器素子の形状はW3.20mm×D1.60mm×T2.0
0mmの大きさで形成された1×3タイプと呼ばれるもの
である。The shape of the laminated ceramic porcelain element shown in this embodiment is W3.20 mm × D1.60 mm × T2.0.
It is called a 1x3 type formed with a size of 0 mm.
【0027】[0027]
【発明の効果】以上に示したように本発明によれば積層
セラミック磁器素子のセラミック層と内部電極層が交互
に積層され前記内部電極層によって挟まれるセラミック
層が1層だけであるため電極間距離を大きくでき静電容
量を小さくすることができる。As described above, according to the present invention, since the ceramic layers and the internal electrode layers of the laminated ceramic porcelain element are alternately laminated and the ceramic layer sandwiched by the internal electrode layers is only one layer, the inter-electrode The distance can be increased and the capacitance can be decreased.
【0028】また、前記積層セラミック磁器素子の最上
層と最下層のセラミック層の厚みの合計を前記内部電極
層によって挟まれるセラミック層の厚みより大きくする
ことにより電極の両端に加わる電圧は前記内部電極層に
よって挟まれるセラミック層に加わり、前記積層セラミ
ック磁器素子の表面をリークすることなく前記積層セラ
ミック磁器素子を機能させることができる。Further, by making the total thickness of the uppermost and lowermost ceramic layers of the monolithic ceramic porcelain element larger than the thickness of the ceramic layers sandwiched by the internal electrode layers, the voltage applied to both ends of the electrodes is increased. In addition to the ceramic layers sandwiched between the layers, the laminated ceramic ceramic element can be made to function without leaking the surface of the laminated ceramic ceramic element.
【0029】また、内部電極層の形状を種々変えること
により有効電極面積を使用目的に応じて容易に変えるこ
とができ、電極間距離を大きくし有効電極面積を小さく
することにより静電容量をさらに小さくすることができ
る。Further, the effective electrode area can be easily changed according to the purpose of use by variously changing the shape of the internal electrode layer, and the electrostatic capacitance is further increased by increasing the distance between the electrodes and decreasing the effective electrode area. Can be made smaller.
【0030】これにより静電容量が小さくなるのに伴い
ノイズ減衰率が最大になる共振周波数を高くすることが
でき、信号ラインに乗ってくる高周波ノイズを吸収、抑
制することができる。また、有効電極面の形状を種々変
えることにより静電容量を変えることなく吸収できるノ
イズエネルギーの大きさを調節することができる。As a result, it is possible to increase the resonance frequency at which the noise attenuation rate is maximized as the electrostatic capacitance becomes smaller, and it is possible to absorb and suppress the high frequency noise riding on the signal line. Further, by varying the shape of the effective electrode surface, the amount of noise energy that can be absorbed can be adjusted without changing the electrostatic capacitance.
【0031】さらに、セラミック層の主成分をSrTi
O3または前記SrTiO3のSrの一部をCa,Mg,
Baのうちの少なくとも一つ以上の元素で置換したもの
を用いることにより、コンデンサとバリスタの両方の特
性を持たせることができる。これにより静電気パルスな
どの立ち上がりが急峻な異常高電圧が印加されても素子
が破壊することがなくなる。また、有効電極面積を小さ
くすることにより電流密度が高まるためαを大きくする
ことができ、tanδを小さくし制限電圧を低くするこ
とができるとともにサージ耐量、エネルギー耐量を大き
くすることができる。Further, the main component of the ceramic layer is SrTi.
O 3 or part of Sr of the SrTiO 3 is replaced with Ca, Mg,
By using a material in which at least one element of Ba is substituted, both characteristics of the capacitor and the varistor can be provided. As a result, the element will not be destroyed even if an abnormally high voltage such as an electrostatic pulse having a sharp rise is applied. Further, since the current density is increased by decreasing the effective electrode area, α can be increased, tan δ can be decreased to reduce the limiting voltage, and the surge resistance and energy resistance can be increased.
【0032】また、このようにして作られた積層セラミ
ック磁器素子の表面、内部のいずれかまたは両方に主成
分がSi,Al,Tiのうち少なくとも一つ以上からな
るコーティング剤で被膜を形成することにより、均一で
緻密な被膜が得られることから耐環境特性、特に耐湿特
性を著しく改善することができる。In addition, a film may be formed on the surface or inside or both of the thus-produced laminated ceramic porcelain element with a coating agent whose main component is at least one of Si, Al and Ti. As a result, a uniform and dense coating film can be obtained, so that the environment resistance characteristics, especially the humidity resistance characteristics can be remarkably improved.
【図1】本発明の第1の実施例における積層セラミック
磁器素子の構成を示す断面図FIG. 1 is a sectional view showing the structure of a laminated ceramic porcelain element according to a first embodiment of the present invention.
【図2】同実施例における内部電極の形状を示す積層セ
ラミック磁器素子の平面図FIG. 2 is a plan view of a laminated ceramic porcelain element showing the shape of internal electrodes in the same example.
【図3】本発明の第2の実施例における積層セラミック
磁器素子の構成を示す断面図FIG. 3 is a sectional view showing a structure of a laminated ceramic porcelain element according to a second embodiment of the present invention.
【図4】同実施例における内部電極の形状を示す積層セ
ラミック磁器素子の平面図FIG. 4 is a plan view of a laminated ceramic porcelain element showing the shape of internal electrodes in the same example.
1 シート 1a 最上層の無効層 1b 最下層の無効層 2 有効層 3a,3b 内部電極 5 コーティング剤で形成した被膜 1 sheet 1a uppermost ineffective layer 1b lowermost ineffective layer 2 effective layers 3a, 3b internal electrode 5 coating formed by coating agent
Claims (12)
れるように2層の内部電極層を設け、この2層の内部電
極層のそれぞれの一端を対向する外部電極に接続し、最
上層と最下層のセラミック層の厚みの合計が前記内部電
極層によって挟まれるセラミック層の厚みより大きくな
るように構成した積層セラミック磁器素子。1. A two-layer internal electrode layer is provided so that ceramic layers and internal electrode layers are alternately laminated, and one end of each of the two internal electrode layers is connected to an opposing external electrode, and the uppermost layer is formed. A multilayer ceramic porcelain element configured such that the total thickness of the lowermost ceramic layers is larger than the thickness of the ceramic layers sandwiched by the internal electrode layers.
部電極に接続された長方形であり、他方の電極が上記外
部電極と相対向する外部電極に接続された部分を底辺と
する三角形である請求項1記載の積層セラミック磁器素
子。2. The internal electrode layer has a shape of a rectangle in which one electrode is connected to an external electrode at one end and a triangle whose base is a portion where the other electrode is connected to the external electrode facing the external electrode. The multilayer ceramic porcelain element according to claim 1.
部電極に接続された長方形であり、他方の電極が上記外
部電極と相対向する外部電極に接続された部分を底辺と
し他の二辺が内部に湾曲した曲線からなる略三角形であ
る請求項1記載の積層セラミック磁器素子。3. The shape of the internal electrode layer is a rectangle in which one electrode is connected to an external electrode at one end, and the other electrode is connected to the external electrode opposite to the external electrode, with the base being the other portion. The laminated ceramic porcelain element according to claim 1, wherein the laminated ceramic porcelain element has a substantially triangular shape in which two sides are curved inward.
部電極に接続された長方形であり、他方の電極が上記外
部電極と相対向する外部電極に接続された部分を底辺と
し他の二辺が外部に湾曲した曲線からなる略三角形であ
る請求項1記載の積層セラミック磁器素子。4. The shape of the internal electrode layer is such that one electrode has a rectangular shape with one end connected to an external electrode, and the other electrode has a base connected to the external electrode opposite to the external electrode. The laminated ceramic porcelain element according to claim 1, wherein the laminated ceramic porcelain element has a substantially triangular shape whose two sides are curved outwardly.
向するそれぞれの外部電極に接続された部分を底辺とす
る三角形である請求項1記載の積層セラミック磁器素
子。5. The multilayer ceramic porcelain element according to claim 1, wherein the shape of the internal electrode layer is a triangle whose base is a portion where both internal electrodes are connected to respective external electrodes facing each other.
向するそれぞれの外部電極に接続された部分を底辺とし
他の二辺が内部に湾曲した曲線からなる略三角形である
請求項1記載の積層セラミック磁器素子。6. The shape of the internal electrode layer is a substantially triangular shape in which a portion where both internal electrodes are connected to respective external electrodes facing each other is the base and the other two sides are curved curves inward. The laminated ceramic porcelain element described.
向するそれぞれの外部電極に接続された部分を底辺とし
他の二辺が外部に湾曲した曲線からなる略三角形である
請求項1記載の積層セラミック磁器素子。7. The shape of the internal electrode layer is a substantially triangular shape in which a portion where both internal electrodes are connected to respective external electrodes facing each other is the base and the other two sides are curved curves to the outside. The laminated ceramic porcelain element described.
に接続された部分を底辺とする三角形であり、他方の電
極が外部電極に接続された部分を底辺とし他の二辺が内
部に湾曲した曲線からなる略三角形である請求項1記載
の積層セラミック磁器素子。8. The shape of the internal electrode layer is a triangle whose base is a part where one electrode is connected to the external electrode, and the other side is an internal part when the part where the other electrode is connected to the external electrode is the base. The monolithic ceramic porcelain element according to claim 1, wherein the monolithic ceramic porcelain element has a substantially triangular shape with a curved curve.
に接続された部分を底辺とする三角形であり、他方の電
極が外部電極に接続された部分を底辺とし他の二辺が外
部に湾曲した曲線からなる略三角形である請求項1記載
の積層セラミック磁器素子。9. The shape of the internal electrode layer is a triangle whose base is a portion where one electrode is connected to an external electrode, and the other side is an external portion where the base is a portion where the other electrode is connected to the external electrode. The monolithic ceramic porcelain element according to claim 1, wherein the monolithic ceramic porcelain element has a substantially triangular shape with a curved curve.
極に接続された部分を底辺とし他の二辺が内部に湾曲し
た曲線からなる略三角形であり、他方の電極が外部電極
に接続された部分を底辺とし他の二辺が外部に湾曲した
曲線からなる略三角形である請求項1記載の積層セラミ
ック磁器素子。10. The shape of the internal electrode layer is a substantially triangular shape having a curved line in which one electrode is connected to the external electrode at the base and the other two sides are curved inward, and the other electrode is connected to the external electrode. 2. The laminated ceramic porcelain element according to claim 1, wherein the formed portion is a base and the other two sides are substantially triangular with a curved line curved outward.
たはこのSrTiO3のSrの一部をCa,Mg,Ba
のうちの少なくとも一つ以上の元素で置換したものであ
り、かつコンデンサとバリスタの両方の特性を持つもの
である請求項1、請求項2、請求項3、請求項4、請求
項5、請求項6、請求項7、請求項8、請求項9または
請求項10記載の積層セラミック磁器素子。11. The main component of the ceramic layer is SrTiO 3 or a part of Sr of this SrTiO 3 is Ca, Mg, Ba.
3. A material obtained by substituting at least one of the above elements and having characteristics of both a capacitor and a varistor, claim 1, claim 2, claim 3, claim 4, claim 5, claim 5. The laminated ceramic porcelain element according to claim 6, claim 7, claim 8, claim 9, or claim 10.
かあるいは両方に、主成分がSi,Al,Tiのうち少
なくとも一つ以上からなるコーティング剤で被膜を形成
した請求項1または請求項11記載の積層セラミック磁
器素子。12. The coating according to claim 1 or 11, wherein a coating is formed on the surface or inside of the ceramic layer, or both, with a coating agent whose main component is at least one of Si, Al and Ti. Multilayer ceramic porcelain element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4168841A JP3064676B2 (en) | 1992-06-26 | 1992-06-26 | Multilayer ceramic porcelain element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4168841A JP3064676B2 (en) | 1992-06-26 | 1992-06-26 | Multilayer ceramic porcelain element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0613260A true JPH0613260A (en) | 1994-01-21 |
JP3064676B2 JP3064676B2 (en) | 2000-07-12 |
Family
ID=15875526
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4168841A Expired - Fee Related JP3064676B2 (en) | 1992-06-26 | 1992-06-26 | Multilayer ceramic porcelain element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3064676B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3641593A1 (en) * | 1985-12-06 | 1987-06-11 | Fuji Photo Film Co Ltd | DOUBLE PIPETTE DEVICE |
JP2003197406A (en) * | 2001-12-25 | 2003-07-11 | Maruwa Co Ltd | Method of manufacturing chip varistor |
JP2005277140A (en) * | 2004-03-25 | 2005-10-06 | Sanyo Electric Co Ltd | Electrolytic capacitor |
-
1992
- 1992-06-26 JP JP4168841A patent/JP3064676B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3641593A1 (en) * | 1985-12-06 | 1987-06-11 | Fuji Photo Film Co Ltd | DOUBLE PIPETTE DEVICE |
JP2003197406A (en) * | 2001-12-25 | 2003-07-11 | Maruwa Co Ltd | Method of manufacturing chip varistor |
JP2005277140A (en) * | 2004-03-25 | 2005-10-06 | Sanyo Electric Co Ltd | Electrolytic capacitor |
JP4565869B2 (en) * | 2004-03-25 | 2010-10-20 | 三洋電機株式会社 | Electrolytic capacitor |
Also Published As
Publication number | Publication date |
---|---|
JP3064676B2 (en) | 2000-07-12 |
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