JPH0612224A - Method and device for arithmetic processing for floating point binary number - Google Patents

Abstract

PURPOSE:To accelerate the denormalization of a floating point binary number. CONSTITUTION:Post-processing is performed to a mantissa M and an exponent E of the floating point binary numbers as the result of subtraction, for example, and a mantissa (m) and an exponent (e) are obtained as the result. Therefore, an output (E-1) of a decrementer 201 and an output (digit drop amount LSA of the mantissa) of a preceding '1' detection circuit 20 are inputted to a minimum value selection circuit 203. In the case of (E-1)<LSA (namely when denormalization is required,) the minimum value selection circuit 203 sets shift amount SH to the (E-1) and turns a level discrimination signal CR to '1.' In the case of (E-1)>=LSA (namely when normalization is required,) the SH is set to the LSA and the CR is turned to '0'. A left shirter 204 outputs a value performing the left shift processing of the shift amount SH to the mantissa M as the mantissa (m) of the result. A selection circuit 207 outputs '0' in the case of CR=1, and outputs the output (E-LSA) of a subtraction circuit 206 as the exponent (e) of the result in the case of CR=0.

Description

Detailed Description of the Invention

[0001]

The present invention relates to the IEEE (the Instit
ute of Electrical and Electronics Engineers) 75
The present invention relates to an arithmetic processing method and an arithmetic processing device using a binary number represented by the four standards or in compliance with the four standards.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for high-speed and accurate floating-point arithmetic with the increasing complexity of scientific and technological calculations and graphic processing. In many cases, a computer uses only a limited number of floating-point numbers for processing.
There is an error in the result obtained by the floating point arithmetic. The calculation accuracy depends largely on the hardware configuration of the computer,
By complying with the IEEE754 standard, it is possible to prevent the occurrence of an error depending on the hardware configuration.

In the IEEE754 standard, a representation format of a single-precision floating-point binary number having a total of 32 bits including a 1-bit code S, an 8-bit exponent E, and a 23-bit fractional part F is defined. . In addition, 1-bit code S and 1
6 total of 1-bit exponent E and 52-bit fractional part F
A representation format of a 4-bit double precision floating point binary number is also defined. Normally, the most significant bit (MSB) of the fractional part F
A floating point number subjected to normalization processing (normalization processing) so that the virtual non-zero value bit and the decimal point are located further above is used. However, the actual exponent is biased so that the exponent E becomes a positive number. For example, in the case of single precision, 127 is set as the bias for the actual index.
Let E be the number obtained by adding. In other words, real number R1 represented as single precision normalized number (normalized number) is, R1 = (- 1) a ^{S 2 E-127 (1.F)} (1). However, in the formula (1), 1. F is called the mantissa M.

Further, according to the IEEE754 standard, when a calculation result is a value near 0, this is expressed as a denormalized number. For example, in the case of single precision, the denormalization process (the denormalization process) that sets the exponent E to 0 and shifts the fractional part F so that the weight of the zero-value bit one above the decimal point becomes 2 ^-126 Is given. In this case, the real R2 expressed as the de normalized numbers are, R2 = - a ^{(1) S 2 -126 (0.F} ) (2). In this case, the mantissa M is 0. It is F.

Now, the absolute values are almost the same and the signs are different.
The phenomenon in which the number of significant figures decreases significantly when two numbers are added is called "digit loss". If the exponent of the minuend and the exponent of the subtraction are equal in the subtraction of the floating-point numbers with a small difference, then the subtraction of the mantissas is performed without a digit alignment operation. For example, the mantissa of the minuend is 1.100101.
, And when the mantissa of the subtraction is 1.100010 ..., The result of subtraction of the mantissa is 0.000011. In this way, when the value of the bit immediately above the decimal point becomes 0 in the operation result, it is said that "mantissa digit loss" occurred.
The number of consecutive zeros from the bit position one digit above the decimal point is called the mantissa cancellation amount. In this example, the mantissa digit cancellation amount is 5
Is.

In the floating-point number in which the mantissa digit cancellation has occurred, the exponent E is subjected to the left shift processing of a shift amount equal to the digit cancellation amount and the exponent E being subtracted from the exponent E. Is normalized by correcting In the following description, the left shift amount (Left Shift Amount) required when a mantissa digit loss occurs is referred to as a digit loss amount LSA.

By the way, the exponent E is the mantissa digit loss amount LSA.
When the value is less than or equal to the following, if the digit loss amount LSA is subtracted from the index E for normalization, the corrected index becomes 0 or less. If the calculation result cannot be represented as a normalized number as in this case, the denormalization process is required.

[0008]

In the conventional computer hardware, only the normalized number is processed. In other words, when it is found that this cannot be expressed as a normalized number when the operation result is normalized by hardware,
It was decided to interrupt the normalization process as if an exception had occurred, and then entrust the software with the denormalization process. Therefore, the denormalization process is executed after the normalization process, and there is a problem that a desired calculation result cannot be obtained at high speed.

An object of the present invention is to speed up the denormalization process of floating-point binary numbers as much as the normalization process.

[0010]

In order to achieve the above object, the present invention provides an index E before performing a normalizing process.
And a digit-rejection amount LSA of the mantissa are discriminated, and either one of the normalizing process and the denormalizing process is executed according to the result of the discrimination.

Specifically, in the arithmetic processing method according to the first aspect of the present invention, in the arithmetic processing unit for a floating point binary number having the mantissa M and the exponent E, the mantissa M is shifted and the exponent E is adjusted. In the method for calculating the mantissa M, the difference between the preceding bit position of 1 in the mantissa M and the bit position one digit above the decimal point is determined as the mantissa digit loss amount LSA, and the magnitude of the exponent E and the digit loss amount LSA is calculated. The step of comparing,
By performing a left shift process on the mantissa M, where the digit loss amount LSA is smaller than the index E, the digit loss amount LSA is set, and in other cases, the value obtained by subtracting 1 from the index E is set as the shift amount SH. The step of obtaining the mantissa m of the arithmetic processing result, and the value obtained by subtracting the digit cancellation amount LSA from the exponent E when the digit cancellation amount LSA is smaller than the exponent E, and 0 in other cases, respectively. This is a configuration including a step of setting the index e.

According to a second aspect of the present invention, there is provided an arithmetic processing device for shifting a mantissa M of a floating point binary number and adjusting an exponent E of the floating point binary number.
The following configuration is adopted, which includes a preceding 1 detection unit, a decrement unit, a comparison unit, a subtraction unit, a selection unit, and a shift unit. That is, the leading 1 detection means detects the leading 1 bit position in the mantissa M,
The difference between the bit position and the bit position one digit above the decimal point is output as the mantissa digit loss amount LSA. The decrement means outputs a value obtained by subtracting 1 from the index E. The comparison means outputs the output (E
-1) and leading loss amount LSA output from the preceding 1 detection means
And the smaller input data is output as a result of the size determination, and a size determination signal indicating which of the two input data is smaller is output. The subtracting means outputs a value obtained by subtracting the carry loss amount LSA output from the preceding 1 detecting means from the index E. The selecting means sets 0 if the magnitude discriminating signal from the comparing means indicates that the output (E-1) of the decrementing means is smaller among the two input data.
In other cases, the output (E-LSA) of the subtraction means is output as the exponent e of the calculation processing result. The shift means outputs a value obtained by subjecting the mantissa M to the left shift processing in which the magnitude determination result output from the comparison means is the shift amount SH, as the mantissa m of the arithmetic processing result.

According to a third aspect of the present invention, in the arithmetic processing unit according to the second aspect of the present invention, the comparing means propagates the magnitude relationship of each digit of the two input data from the upper digit to the lower digit. The shift means is provided with a minimum value selection circuit for sequentially outputting the magnitude discrimination result from the upper digit, and the shift means outputs 2 ^k left ( ^k) corresponding to the lower n bits of the magnitude discrimination result output from the minimum value selection circuit. k = 0,
1, 2, ..., N-1) bit shifters are connected in cascade.

An arithmetic processing device according to a fourth aspect of the present invention has a structure including the following leading 1 detection means, decrement means, comparison / selection means, subtraction means, selection means, and shift means. It was adopted. That is, the leading 1 detection means detects the leading bit position of 1 in the mantissa M and outputs the difference between the bit position and the bit position one digit above the decimal point as the mantissa digit loss amount LSA. is there. The decrement means outputs a value obtained by subtracting 1 from the index E. The comparison and selection means compares the magnitudes of the two input data of the digit loss amount LSA output from the preceding 1 detection means and the exponent E, and when the digit loss amount LSA is smaller, the digit loss amount LSA, In other cases, the output (E-1) of the decrement means is output as the magnitude determination result,
In addition, it outputs a magnitude determination signal indicating which of the two input data is smaller. The subtracting means outputs a value obtained by subtracting the carry loss amount LSA output from the preceding 1 detecting means from the index E. The selection means is the above 2
Digit loss amount L from the preceding 1 detection means of one input data
Output from the subtraction means (E-LSA) when the magnitude discrimination signal from the comparison and selection means indicates that SA is smaller.
In other cases, 0 is output as the exponent e of the arithmetic processing result. The shift means outputs a value obtained by subjecting the mantissa M to the left shift processing in which the magnitude determination result output from the comparison and selection means is the shift amount SH, as the mantissa m of the arithmetic processing result.

According to a fifth aspect of the invention, in the arithmetic processing unit according to the fourth aspect of the invention, the comparison / selection means propagates the magnitude relation of each digit of the two input data from the upper digit to the lower digit. Accordingly, a comparison and selection circuit for sequentially outputting the magnitude discrimination result from the upper digit is provided, and the shift means corresponds to the left 2 ^k (k) corresponding to the lower n bits of the magnitude discrimination result output from the comparison and selection circuit. = 0,
1, 2, ..., N-1) bit shifters are connected in cascade.

According to a sixth aspect of the present invention, there is provided an arithmetic processing device which comprises the following leading 1 detection means, decrement means, subtraction means, first selection means, second selection means and shift means. It adopts a configuration with. That is,
The leading 1 detection means detects the leading bit position of 1 in the mantissa M and outputs the difference between the bit position and the bit position one digit above the decimal point as the mantissa digit loss amount LSA. The decrement means outputs a value obtained by subtracting 1 from the index E. The subtraction means outputs a value obtained by subtracting the digit loss amount LSA output from the preceding 1 detection means from the index E as a subtraction result, and outputs a magnitude determination signal indicating whether the index E is less than or equal to the digit loss amount LSA. It is what is output. The first selecting means sets 0 if the magnitude discriminating signal from the subtracting means indicates that the exponent E is equal to or less than the digit cancellation amount LSA, and in other cases, the subtraction result (E-
LSA) is output as an exponent e of each calculation processing result. The second selection means is that the index E is the digit loss amount LSA.
The output (E-1) of the decrementing means when the magnitude discriminating signal from the subtracting means indicates that the following is true, and in other cases, the digit loss amount LSA output from the preceding 1 detecting means.
Are output respectively. The shift means performs a left shift process in which the output of the second selection means is the shift amount SH and the mantissa M.
Is output as the mantissa m of the arithmetic processing result.

An arithmetic processing unit according to a seventh aspect of the present invention comprises the following leading 1 detection means, subtraction means, first selection means, second selection means, and shift processing means. The configuration is adopted. That is, the leading 1 detection means detects the leading bit position of 1 in the mantissa M and outputs the difference between the bit position and the bit position one digit above the decimal point as the mantissa digit loss amount LSA. is there. The subtraction means outputs a value obtained by subtracting the digit loss amount LSA output from the preceding 1 detection means from the index E as a subtraction result, and outputs a magnitude determination signal indicating whether the index E is less than or equal to the digit loss amount LSA. It is what is output. The first selecting means sets 0 when the magnitude discriminating signal from the subtracting means indicates that the exponent E is equal to or less than the digit cancellation amount LSA, and in other cases, the subtraction result (E-LSA) from the subtracting means. ) Is output as the exponent e of the calculation processing result. The second selecting means outputs the exponent E when the magnitude discriminating signal from the subtracting means indicates that the exponent E is less than or equal to the digit cancellation amount LSA, and the digit output from the preceding 1 detecting means in other cases. The drop amount LSA is output respectively. The shift processing means subtracts 1 from the output of the second selecting means when the magnitude discriminating signal from the subtracting means indicates that the exponent E is less than or equal to the digit cancellation amount LSA, and in other cases. A value obtained by subjecting the mantissa M to the left shift processing in which the output itself of the second selecting means is the shift amount SH is output as the mantissa m of the calculation processing result.

According to an eighth aspect of the invention, in the arithmetic processing unit according to the seventh aspect of the invention, the shift processing means shifts the output (E or LSA) of the second selecting means by a shift amount SH.
And a left shifter for outputting a value obtained by subjecting the mantissa M to the left shift processing, and the exponent E having a digit loss amount LSA.
If the magnitude discrimination signal from the subtracting means indicates that the following is true, the value obtained by subjecting the output of the left shifter to the right 1-bit shift processing is used, and in other cases, the output of the left shifter itself is used. A right 1-bit shifter for outputting the mantissa m of the arithmetic processing result is provided.

According to a ninth aspect of the present invention, in the arithmetic processing unit according to the sixth or seventh aspect of the invention, the subtracting means outputs the exponent E and the carry loss amount L output from the leading 1 detecting means.
The subtraction result (E−L
SA) and for generating the magnitude discriminating signal based on the carry borrow generation signal and the carry borrow propagation signal in consideration of the borrow propagation from the least significant digit to the most significant digit in the subtraction of the two input data. A subtraction circuit was provided.

A subtraction circuit according to a tenth aspect of the present invention has a function of performing an X-Y operation on n-bit input data X and Y and outputting the result, and the 0th digit to the (n-th) digit in the operation. 1) A configuration having a function of generating and outputting a magnitude discriminating signal representing a magnitude relation X ≦ Y of the input data based on a borrow borrow generating signal and a borrow borrow propagating signal in consideration of borrow borrow propagation up to a digit is adopted. It is a thing.

[0021]

According to the first aspect of the present invention, it is determined whether the arithmetic processing result is a normalized number or a denormalized number by comparing the exponent E and the mantissa digit loss amount LSA. It When the arithmetic processing result is a normalized number (E> LSA), the digit loss amount LSA is selected as the shift amount SH of the mantissa M, and the value obtained by subtracting the digit loss amount LSA from the exponent E as the exponent e of the result. Is selected (normalization process). On the other hand, when the operation processing result is the denormalized number (E ≦ LS
In A), a value obtained by subtracting 1 from the index E is selected as the shift amount SH of the mantissa M, and 0 is selected as the resulting index e (denormalization processing).

According to the second aspect of the invention, there is provided hardware for efficiently executing the arithmetic processing method according to the first aspect of the invention. First data (E-1) to be selected as the shift amount SH in the case of denormalization processing
And the second data (LSA) to be selected as the shift amount SH in the case of the normalizing process are given to the comparison means as input data. The comparison means determines whether the arithmetic processing result is a normalized number or a denormalized number depending on whether the value obtained by subtracting the second data (LSA) from the first data (E-1) becomes negative. Is determined. The shift means adopts the smaller one of the first and second data as the shift amount SH of the left shift process to be applied to the mantissa M. That is, the shift means is shared by the normalizing process and the denormalizing process.

According to the third aspect of the invention, the first and second data (E-1, LS) are made by the minimum value selection circuit.
The magnitude determination result of A) is determined in order from the upper digit. Every time the digit of the magnitude discrimination result is determined, the shift means performs a left shift process on the mantissa M by a shift amount (2 ^k bits) according to the determined digit.

According to the invention of claim 4, the mantissa digit loss amount LSA and the exponent E are given to the comparison and selection means as the first and second input data, respectively. The comparison / selection means is the first
Whether the result of the arithmetic processing is a normalized number or a denormalized number is determined depending on whether the value obtained by subtracting the second input data (E) from the input data (LSA) is negative. . Further, the comparison / selection means uses the digit loss amount LSA when the calculation processing result is a normalized number (E> LSA), and when the calculation processing result is a denormalized number (E ≦ LS).
In (A), the output (E-1) of the decrement means as the third input data is output as the shift amount SH of the mantissa M, respectively. That is, the comparison / selection means can start the magnitude comparison of the first and second input data before the third input data is determined.

According to the fifth aspect of the present invention, the comparison / selection circuit sequentially determines the magnitude determination result of the first and second data (LSA, E) from the upper digit. Every time the digit of the magnitude discrimination result is determined, the shift means performs a left shift process on the mantissa M by a shift amount (2 ^k bits) according to the determined digit.

According to the sixth aspect of the present invention, the exponent E and the mantissa digit loss amount LSA are given to the subtraction means as the first and second input data, respectively. The subtraction means calculates the subtraction result (E
-LSA) is output, and the value obtained by subtracting the second input data (LSA) from the first input data (E) is 0.
Whether or not the calculation processing result is a normalized number or a denormalized number is determined depending on whether or not: Depending on the result of this determination, the output (E-1) of the decrement means or the digit loss amount LSA is selected as the shift amount SH of the mantissa M. That is, the subtraction means simultaneously executes the correction of the exponent E in the case of normalization processing and the determination of the calculation processing result.

According to the invention of claim 7, when the arithmetic processing result is a normalized number (E> LSA), the digit loss amount LSA is, and when the arithmetic processing result is a denormalized number (E> LSA). The index E is given to the shift processing means for ≤ LSA). When the index E is given to the shift processing means, the left shift amount is reduced by 1 in the shift processing means.

According to the eighth aspect of the present invention, the left shift processing of the required shift amount SH (LSA or E-1) is performed by the mantissa by the left shifter of variable shift amount and the right 1-bit shifter connected to the output side thereof. It is applied to M.

According to the invention of claim 9, the first input is made by using the borrow generation signal and the borrow propagation signal from the least significant digit to the most significant digit in the subtraction (E-LSA) of two input data. From the data (E) to the second input data (L
A magnitude determination signal indicating whether the value obtained by subtracting (SA) becomes 0 or less is generated.

According to the tenth aspect of the present invention, each bit of the n-bit input data X, Y is represented by Xi, Yi (i = 0 to n-).
In the case of 1), the carry borrow generation signal Igi and the carry borrow propagation signal Ipi are first generated for each digit in the calculation of XY. Next, based on the Igi and Ipi (i = 0 to n-1) and considering borrow propagation from the lower digit, the k-th
The digit borrow generation signal Igjk and the digit borrow propagation signal Ipjk from the digit to the j-th digit (k <j) are generated. Finally, the 0th
A borrow generation signal Ig (n-1) 0 and a borrow propagation signal Ip (n-1) 0 are created in consideration of the borrow propagation of all bits from the digit to the (n-1) th digit. If Ig (n-1) 0 = 1, X <Y, I
p (n-1) 0 = 1 represents X = Y. That is, Ig (n-
When either 1) 0 or Ip (n-1) 0 is 1,
X ≦ Y. In this way, the two input data X and Y
A magnitude discrimination signal representing the magnitude relation X ≦ Y of is generated.
The borrow generation signal and the borrow propagation signal are also used to calculate the calculation result (XY). Most of the hardware can be shared between the calculation of the calculation result and the generation of the magnitude discrimination signal.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An arithmetic processing method according to an embodiment of the present invention and an arithmetic processing device used for implementing the same will be described below with reference to the drawings.

FIG. 1 is a flow chart showing a processing flow of an arithmetic processing method according to an embodiment of the present invention for floating point binary numbers. By post-processing the input floating-point binary mantissa M and the exponent E as the result of the operation (eg subtraction) of the normalized numbers,
The mantissa M and the exponent E are output, and the mantissa m of the floating point binary number is
And a procedure for converting into an index e. Hereinafter, the case of single precision will be described step by step, but the arithmetic processing method of FIG. 1 can also be applied to the case of double precision.

First, the leading bit position of 1 in the mantissa M is detected in order to obtain the digit loss amount LSA of the mantissa. The digit loss amount LSA is obtained as a difference between the detected leading 1 bit position and the bit position one digit above the decimal point (step 101). Then, the exponent E is compared with the amount of digit loss LSA (step 102).

When E≤LSA, the denormalization process is executed so that the calculation process result is expressed as a denormalized number. Therefore, it is necessary to reduce the exponent E so that the exponent E becomes 0 and to perform the left shift processing of the shift amount corresponding to the reduction amount on the mantissa M. However, the bit above the decimal point in the normalized number has a weight of 2 ^-127 , but the weight of the bit in the ^denormalized number is 2 ^-126 as shown in the above equation (2). Therefore, it is necessary to reduce the shift amount by 1 bit in the left shift processing of the mantissa M. Therefore, the mantissa shift amount SH is set to E-1 (step 103). Further, the index e of the calculation processing result is set to 0 (step 104).

On the other hand, in the case of E> LSA, the mantissa shift amount SH is set to LSA so that the normalization process is executed.
(Step 105), the exponent e of the arithmetic processing result is E-
LSA (step 104). At this time, the index e (=
E-LSA) is positive.

In step 107, the mantissa M is left-shifted in accordance with the shift amount SH obtained in step 103 or step 105 to obtain the mantissa m of the arithmetic processing result.

According to the above arithmetic processing method, the arithmetic processing result is a denormalized number by controlling the processing flow according to the result of the comparison of the exponent E and the mantissa digit loss amount LSA. Even in the case, the processing can be executed at high speed as in the case of the normalized number. Note that the shift amount SH is set to E in step 103.
Change to set to E instead of -1, step 107
Before or after the mantissa M is left-shifted in
Only in the case of A, the mantissa M may be further subjected to right 1-bit shift processing.

The first to fourth arithmetic processing devices according to the embodiments of the present invention used for implementing the above arithmetic processing method will be sequentially described.

FIG. 2 shows the configuration of the first arithmetic processing unit.
This arithmetic processing device includes a decrementer 201, a preceding 1 detection circuit 202, a minimum value selection circuit 203, a left shifter 204,
Mantissa result register 205, subtraction circuit 206, selection circuit 2
07 and exponent result register 208.

The decrementer 201 outputs a value obtained by subtracting 1 from the index E. Leading 1 detection circuit 202
Is the first bit position in the mantissa M which is searched for in the direction of the least significant bit (LSB) from the bit immediately above the decimal point in the mantissa M, and detects the first bit position, and the detected bit position and one of the decimal points. The difference from the above bit position is output as the carry loss amount LSA. The minimum value selection circuit 203 compares the magnitude of two input data of the output (E-1) of the decrementer 201 and the output LSA of the preceding 1 detection circuit 202 and outputs the smaller input data as the shift amount SH, And the 2
A magnitude discrimination signal CR indicating which of the two input data is smaller is output. When (E-1) <LSA (that is, when E ≦ LSA), SH = E−
1 and CR = 1 and (E-1) ≧ LSA (that is, E> LSA), SH = LSA and C
R = 0. The left shifter 204 has a minimum value selection circuit 20.
The value obtained by subjecting the mantissa M to the left shift processing of the shift amount specified by the output SH of 3 is the mantissa m of the calculation processing result.
Is output as. Mantissa result register 205
Is for storing the output m of the left shifter 204.

The subtraction circuit 206 outputs a value obtained by subtracting the output LSA of the preceding 1 detection circuit 202 from the exponent E. The selection circuit 207 outputs 0 when CR = 1 and CR
When = 0, the output (E-LSA) of the subtraction circuit 206 is output as the exponent e of the calculation processing result.
The exponent result register 208 stores the output e of the selection circuit 207.

According to the configuration of FIG. 2, the minimum value selection circuit 20
3 is preceded by 1 from the output (E-1) of the decrementer 201
Depending on whether the value obtained by subtracting the output (LSA) of the detection circuit 202 becomes negative, it is determined whether the operation processing result is a normalized number or a denormalized number. The shift amount SH of the mantissa M and the exponent e of the arithmetic processing result are executed so that either one of the normalizing process and the denormalizing process is executed according to the result of this determination.
Are determined respectively. At this time, the left shifter 204 is used for both the normalizing process and the denormalizing process.

Now, the minimum value selection circuit 203 in FIG.
The size of two 8-bit input data X and Y is compared, the smaller input data is designated as output data Z, and X <
It has a function of setting the logical value of the magnitude discrimination signal output terminal B to 1 when Y. This minimum value selection circuit 203
Is an input circuit 311, an intermediate circuit 312, as shown in FIG.
And the output circuit 313, and the output data Z is determined in order from the most significant digit and at high speed by propagating the magnitude relationship of each digit of the two input data X and Y from the upper digit to the lower digit. Is configured to be
(See No. 12735).

Each bit of the input / output data X, Y, Z is set to Xi.
, Yi, Zi (i = 0 to 7), first, in the input circuit 311, a magnitude relation determining function gi and a magnitude relation holding function pi are created for each digit. gi = 1 is Xi <Yi
, Pi = 1 represents Xi = Yi, respectively.

Next, based on the outputs gi and pi of the input circuit 311, the middle stage circuit 312 determines the magnitude relation determining function gjk and the magnitude relation holding function pjk from the jth digit to the kth digit (j <k). Made For example, g67 = 1 represents a 2-bit magnitude relationship X7 X6 <Y7 Y6, and p67 = 1 represents a 2-bit equality relationship X7 X6 = Y7 Y6. Also, g47 = 1 is a 4-bit magnitude relationship X7 X6 X5 X4 <
Y7 Y6 Y5 Y4, p47 = 1 is a 4-bit equivalence relation X
7 X6 X5 X4 = Y7 Y6 Y5 Y4, respectively. The magnitude relation determining functions gi and gjk and the magnitude relation holding functions pi and pjk are propagated from the upper digit to the lower digit.

In this way, when the magnitude relation determining function gi7 from each digit (i-th digit) to the most significant digit (7th digit) is obtained, Xi is calculated at each digit when gi7 = 1. gi7 ＝
In the case of 0, Yi is selected and designated as Zi. As a result, 8-bit output data Z (minimum value) is sequentially obtained from the most significant digit. However, the output circuit 313 of FIG.
Then, Z7 depends on g7, Z6 responds to g67, and Z5
, Z4 are determined according to g47, and Z3 to Z0 are determined according to g07. The magnitude relationship determining function g07 from the 0th digit to the 7th digit, which is 1 when X <Y and 0 when X ≧ Y, is
It is output from the size determination signal output terminal B.

On the other hand, the left shifter 204, as shown in FIG. 2, has 16 bits, 8 bits, and 4 bits in order from the input side of the mantissa M.
The output Z7 of the minimum value selection circuit 203 is formed by connecting a total of five individual left shifters of 1 bit, 2 bits, and 1 bit.
The lower 5 bits of Z0 to Z0 are control signals for the individual left shifters. That is, when the output (shift amount SH) of the minimum value selection circuit 203 is sequentially determined from the most significant digit, the left shifter 204 is sequentially activated from the 16-bit shifter with the large shift amount. As a result, every time the digit of the output of the minimum value selection circuit 203 is determined in order from the higher order, the mantissa M is subjected to the left shift processing of the shift amount (2 ^k bits) according to the determined digit.

As described above, according to the configurations of FIGS. 2 and 3, the minimum value selection circuit 203 that determines the output data Z in order from the upper digit, and the multistage left shifter 204 that is activated in order from the shifter with the largest shift amount. Since the configuration including and is adopted, the left shift processing of the mantissa M can be speeded up. In consideration of the number of bits of each of the mantissa M and the exponent E in the case of single precision, the minimum value selection circuit 203 has an 8-bit configuration, and the left shifter 204 has five stages of left 2 ^k (k = 0 to 4) bit shifters. Although the configurations have been adopted, these configurations can be appropriately changed according to the number of bits of the mantissa M and the exponent E.

FIG. 4 shows the configuration of the second arithmetic processing unit.
In the arithmetic processing device of FIG. 4, the minimum value selection circuit 20 of FIG.
3 is replaced by the comparison / selection circuit 401. Also,
The selection circuit 402 in FIG. 4 outputs the output (E-LSA) of the subtraction circuit 206 when CR = 1 and outputs 0 (0) when CR = 0, respectively. Have different functions.

The comparison / selection circuit 401 is the leading 1 detection circuit 2
The output LSA of 02 and the index E are compared in magnitude, and when the LSA is smaller, the LSA is set, and in other cases, the output (E-1) of the decrementer 201 is set as the shift amount SH. It outputs a large / small discriminating signal CR indicating which of LSA and E is smaller. If LSA <E, then SH = LSA and CR
= 1 and LSA ≧ E, then SH = E−1 and CR = 0.

According to the configuration of FIG. 4, the comparison / selection circuit 401
Depending on whether or not the value obtained by subtracting the exponent E from the output LSA of the preceding 1 detection circuit 202 becomes negative, the operation processing result becomes a normalized number or a denormalized number.
Determine if it will be a number. At this time, the comparison / selection circuit 4
Unlike in the case of the minimum value selection circuit 203 in FIG. 2, 01 can start the size comparison of the two input data before the output of the decrementer 201 is fixed, so that the determination can be speeded up. Then, the shift amount SH of the mantissa M and the exponent e of the calculation processing result are executed so that either one of the normalization processing and the denormalization processing is executed according to the result of this determination.
Are determined respectively. At this time, the left shifter 204 is used for both the normalizing process and the denormalizing process.

The comparison / selection circuit 401 in FIG. 4 compares the magnitudes of the first and second 8-bit input data X and Y, respectively, and when X <Y, X is set, and X ≧ Y. In the case, similarly, the 8-bit third input data S is output data Z respectively.
And a function of setting the logical value of the magnitude discrimination signal output terminal B to 1 when X <Y. As shown in FIG. 5, the comparison / selection circuit 401 includes an input circuit 411, a middle-stage circuit 412, and an output circuit 413. As in the case of the minimum value selection circuit 203, each of the two input data X and Y is input. By propagating the magnitude relation for each digit from the upper digit to the lower digit, the output data Z is determined in order from the most significant digit and at high speed.

According to the configurations of FIGS. 4 and 5, a comparison / selection circuit 401 for determining the output data Z in order from the upper digit,
Since the configuration including the multi-stage left shifter 204 that is activated in order from the shifter with the largest shift amount is adopted, the left shift processing of the mantissa M can be speeded up. Note that the mantissa M for single precision
In consideration of the number of bits of each of E and E, the comparison / selection circuit 401 has an 8-bit configuration, and the left shifter 204 is left 2
^Although a 5-stage configuration of ^k (k = 0 to 4) bit shifters is used, these configurations can be appropriately changed according to the number of bits of the mantissa M and the exponent E.

FIG. 6 shows the configuration of the third arithmetic processing unit.
The decrementer 201, the leading 1 detection circuit 202, the mantissa result register 205, the first selection circuit 207, and the exponent result register 208 in this arithmetic processing device have the same functions as the components having the same reference numerals in FIG. . In FIG. 6, 601 is a subtraction circuit, 602 is a second selection circuit,
Reference numeral 603 is a left shifter.

The subtraction circuit 601 is a leading 1 detection circuit 202.
Is output as a subtraction result, and a magnitude discrimination signal Ib indicating whether or not E ≦ LSA is output. E ≦ LSA
If Ib = 1, and if E> LSA, then Ib = 0. The first selection circuit 207 has Ib =
When 1 is 0, when Ib = 0, the subtraction circuit 601
(E-LSA) is output as the exponent e of the arithmetic processing result. The second selection circuit 602 sets the output (E-1) of the decrementer 201 to Ib = 0 when Ib = 1.
In this case, the output LSA of the preceding 1 detection circuit 202 is output as each shift amount SH. Left shifter 603
Outputs the value obtained by subjecting the mantissa M to the left shift processing of the shift amount designated by the output SH of the second selection circuit 602, as the mantissa m of the arithmetic processing result. The internal configuration of the left shifter 603 is not limited to the multistage shifter (204 in FIG. 2).

The subtraction circuit 601 in FIG. 6 has the respective functions of the subtraction circuit 206 and the minimum value selection circuit 203 in FIG. 2, and the subtraction result (E- (LSA) is output, and at the same time, E to LS
Whether the arithmetic processing result is a normalized number or a denormalized number is determined depending on whether the value obtained by subtracting A becomes 0 or less. The shift amount SH of the mantissa M is set so that either one of the normalizing process and the denormalizing process is executed according to the result of this determination.
And the index e of the arithmetic processing result is determined. At this time, the left shifter 603 is used for both the normalize process and the denormalize process.

Now, the subtraction circuits 601 in FIG.
The subtraction result (X−Y) of the two bit input data X and Y is used as output data Z, and the logical value of the magnitude determination signal Ib is set to 1 when X ≦ Y. As shown in FIG. 7, the subtraction circuit 601 includes an input circuit 611, a middle circuit 612, and an output circuit 613, and the magnitude relationship of the two input data X and Y for each digit is changed from the lower digit to the upper digit. The output data Z is determined by propagating the output data Z.

Each bit of input / output data X, Y, Z is set to Xi.
, Yi, Zi (i = 0 to 7), first, the input circuit 611 generates the borrow generation signal Igi and the borrow propagation signal Ipi for each digit. Borrow generation signal Igi
Is, as is widely known, Xi-Y with respect to the i-th digit.
It is a signal for executing subtraction, which is created so that Ig i = 1 indicates that borrowing from the (i + 1) th digit has occurred in the operation of i. However, Igi = 1 also means that Xi <Yi. On the other hand, the borrow propagation signal Ip
i is the operation Xi-Yi, as is also widely known.
In I, if a borrow from the i-th digit to the (i-1) th digit occurs, if Ipi = 1, it can be determined that a borrow from the (i + 1) th digit occurs. It is another signal for performing the subtraction performed. However, the (i-1)
Since borrowing from a digit causes borrowing from the (i + 1) th digit, Ipi = 1 also indicates that Xi = Yi.

Next, based on the outputs Igi and Ipi of the input circuit 611, the intermediate circuit 612 generates the borrow generation signal Igjk and the borrow propagation signal Ipjk from the kth digit to the jth digit (k <j). Made For example, the borrow generation signal Ig32 from the second digit to the third digit is made so that Ig32 = 1 indicates that the borrow from the fourth digit has occurred in the 2-bit operation X3 X2-Y3 Y2. It is a signal for execution. However, Ig32 = 1 also represents a 2-bit magnitude relationship X3 X2 <Y3 Y2. on the other hand,
The borrow propagation signal Ip32 from the second digit to the third digit is Ip32 when the borrow from the second digit to the two bits of the first digit and the zeroth digit occurs in the operation X3X2-Y3Y2.
If = 1, it is another signal for execution of subtraction that is made so that it can be determined that borrowing from the fourth digit has occurred. However, because borrowing from the first digit or zeroth digit causes borrowing from the fourth digit, Ip
32 = 1 also represents the 2-bit equivalence relation X3 X2 = Y3 Y2. The borrow generation signals Igi and Igjk and the borrow propagation signals Ipi and Ipjk are propagated from the lower digit to the upper digit.

In this way, when the borrow borrow generation signal Igi0 from the least significant digit (0th digit) to each digit (ith digit) is obtained, Ipi and Ig (i in the output circuit 613 at each digit.
Zi is generated based on -1) 0. However, Z1 is I
It is generated based on p1 and Ig0. Since there is no borrow from the least significant digit, Z0 is determined only by Ip0.

The borrow generation signal I from the 0th digit to the 7th digit
The fact that at least one of g70 and the borrow propagation signal Ip70 is 1 represents X ≦ Y. That is, the magnitude discrimination signal Ib can be expressed as Ib = Ig70 + Ip70 (3). However, since Ig70 = Ig74 + Ip74 · Ig30 (4) Ip70 = Ip74 · Ip30 (5), Ib = Ig74 + Ip74 · Ig30 + Ip74 · Ip30 = Ig74 + Ip74 · (Ig30 + Ip30) (6). In the output circuit 613 of FIG. 7, the magnitude determination signal Ib is generated using the relationship of the equation (6).

In general, it is easy to determine whether or not the subtraction result is negative in the subtraction circuit for executing the X-Y subtraction. All you have to do is determine whether or not the highest digit will be borrowed. However, it is difficult to determine whether the subtraction result becomes 0 or less. This is because it is difficult to determine whether the subtraction result becomes 0. It is possible to add a circuit for confirming that all the bits of the subtraction result are 0, or confirming that XY is not negative and XY-1 is negative. , The amount of hardware of the subtraction circuit increases. However, according to the subtraction circuit 601 of FIG. 7, most of the hardware is shared between the calculation of the output data Z and the generation of the magnitude determination signal Ib representing X ≦ Y (X−Y ≦ 0). The amount of hardware can be reduced.

FIG. 8 shows the configuration of the fourth arithmetic processing unit.
In the arithmetic processing device of FIG. 8, the decrementer 201 of FIG.
Instead of removing, the right 1-bit shifter 604 is interposed between the left shifter 603 and the mantissa result register 205. The left shifter 603 and the right 1-bit shifter 604 form a bidirectional shifter 605.

The second selection circuit 602 uses the exponent E when Ib = 1 and the preceding 1 detection circuit 20 when Ib = 0.
The left shifter 60 sets the output LSA of 2 as the shift amount SH.
Output to 3. The right 1-bit shifter 604 calculates the value obtained by subjecting the output of the left shifter 603 to the right 1-bit shift processing when Ib = 1 and the output itself of the left shifter 603 when Ib = 0. It is output as the mantissa m of the processing result.

According to the configuration of FIG. 8, when it is determined by the subtraction circuit 601 (having the internal configuration of FIG. 7) that the calculation processing result becomes the denormalized number (Ib = 1). , The shift amount SH given to the left shifter 603 is set to E and at the same time the right 1-bit shifter 604
As a result of activating the shift operation by, the mantissa M is subjected to the left shift processing of the desired shift amount (E-1). On the other hand, when it is determined that the arithmetic processing result is the normalized number (Ib = 0), the left shifter 6
As the shift amount SH given to 03 is set to LSA and the shift operation of the right 1-bit shifter 604 is stopped at the same time, the mantissa M is subjected to the left shift process of a desired shift amount (LSA). That is, according to the configuration of FIG. 8, by providing the right 1-bit shifter 603, the decrementer 201 in FIG. 6 becomes unnecessary, and the configuration of the arithmetic processing device is simplified. The method of determining the index e of the calculation processing result is the same as in the case of FIG.

In the example shown in FIG. 8, the right 1-bit shifter 604 is provided on the output side of the left shifter 603, but it may be provided on the input side of the left shifter 603.

[0067]

As described above, according to the first aspect of the present invention, the magnitude relationship between the exponent E and the mantissa digit loss amount LSA is discriminated before the normalizing process is executed, and the result is discriminated according to the discrimination result. Since the shift amount of the mantissa M and the exponent of the arithmetic processing result are respectively decided so as to execute either one of the normalization processing and the denormalization processing, the arithmetic result of the floating point binary number can be obtained at high speed. It will be. That is, even when the arithmetic processing result is the denormalized number, the processing can be executed at high speed as in the case of the normalized number.

According to the second aspect of the present invention, the comparison means is provided for determining whether the arithmetic processing result is the normalized number or the denormalized number.
Since the shift amount of the mantissa M and the exponent of the arithmetic processing result are respectively determined according to the result of the judgment, the arithmetic processing device (hardware) for efficiently executing the arithmetic processing method according to the invention of claim 1. ) Can be provided. Therefore, the denormalization process can be speeded up as compared with the conventional case in which the denormalization process is entrusted to software. Moreover, since the shift means is used for both the normalizing process and the denormalizing process, the hardware is reduced.

According to the invention of claim 3, in the arithmetic processing device according to the invention of claim 2, a minimum value selection circuit for sequentially determining an output from a higher digit and a multi-stage shifter activated in order from a shifter with a large shift amount. Since the configuration including and is adopted, the left shift processing of the mantissa M can be speeded up.

According to the invention of claim 4, the third selection data (the output of the decrement means) different from the first and the second input data to be compared in magnitude is output as the shift amount SH. Since the configuration including the means is adopted, the comparison of the magnitudes of the first and second input data can be started before the third input data is determined, and as a result, the arithmetic processing is speeded up.

According to a fifth aspect of the present invention, in the arithmetic processing unit according to the fourth aspect of the invention, there is provided a comparison / selection circuit for sequentially determining an output from a higher digit, and a multi-stage shifter activated in order from a shifter with a larger shift amount. Since the configuration with is adopted,
The left shift processing of the mantissa M can be speeded up.

According to the sixth aspect of the present invention, the correction of the index E in the case of the normalizing process and the determination as to whether the calculation process result is the normalized number or the denormalized number can be executed at the same time. Since the configuration including the subtraction unit is adopted, the hardware is reduced.

According to the invention of claim 7, the correction of the exponent E in the case of the normalizing process and the judgment of whether the arithmetic processing result is the normalized number or the denormalized number can be simultaneously executed. Since the configuration including the subtraction unit is adopted, the hardware is reduced. Also,
Since the configuration including the shift processing means capable of adjusting the left shift amount when the calculation processing result becomes the denormalized number is adopted, the hardware is further reduced.

According to the invention of claim 8, in the arithmetic processing device according to the invention of claim 7, the shift processing means is provided with a left shifter with a variable shift amount and a right 1-bit shifter connected to the output side thereof. Since, the adjustment of the left shift amount can be easily realized.

According to the invention of claim 9 or 10, when the subtraction result is calculated and the magnitude discriminating signal indicating whether the subtraction result becomes 0 or less is generated, the least significant digit in the subtraction of the two input data. To the most significant digit, the structure using the borrow borrow generation signal and the borrow borrow propagation signal in consideration of the borrow propagation is adopted, so that the subtraction means (subtraction circuit) with reduced hardware amount can be realized.

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing flow of an arithmetic processing method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a first arithmetic processing unit according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing an internal configuration of a minimum value selection circuit in FIG.

FIG. 4 is a block diagram showing a configuration of a second arithmetic processing unit according to an embodiment of the present invention.

5 is a circuit diagram showing an internal configuration of a comparison / selection circuit in FIG.

FIG. 6 is a block diagram showing a configuration of a third arithmetic processing unit according to an embodiment of the present invention.

7 is a circuit diagram showing an internal configuration of a subtraction circuit in FIG.

FIG. 8 is a block diagram showing a configuration of a fourth arithmetic processing unit according to an embodiment of the present invention.

[Explanation of symbols]

 201 Decrementor (decrement means) 202 Leading 1 detection circuit (leading 1 detection means) 203 Minimum value selection circuit (comparison means) 204 Left shifter (shift means) 205 Mantissa result register 206 Subtraction circuit (subtraction means) 207 Selection circuit (selection means) , First selection means) 208 exponent result register 401 comparison selection circuit (comparison selection means) 402 selection circuit (selection means) 601 subtraction circuit (subtraction means) 602 second selection circuit (second selection means) 603 left shifter (Shift means) 604 Right 1-bit shifter 605 Bidirectional shifter (shift processing means)

Claims (10)

[Claims] 1. An arithmetic processing method for performing shift processing on the mantissa and adjusting the exponent in an arithmetic processing device for a floating point binary number having a mantissa and an exponent. Determining the difference between the bit position and the bit position one digit above the decimal point as the digit loss amount of the mantissa, comparing the magnitude of the exponent and the digit loss amount, and calculating the digit loss amount from the exponent. A step of obtaining a mantissa as a result of the arithmetic processing by subjecting the mantissa to a left shift process in which the digit cancellation amount is smaller when the one is smaller and the shift amount is a value obtained by subtracting 1 from the exponent in other cases. , A value obtained by subtracting the digit cancellation amount from the exponent when the digit cancellation amount is smaller than the exponent, and 0 being the exponent of the arithmetic processing result in other cases. Characteristic arithmetic processing Law. 2. An arithmetic processing unit for performing shift processing on a mantissa of a floating-point binary number and adjusting an exponent of the floating-point binary number, detecting a preceding bit position of 1 in the mantissa, And a leading 1 detection means for outputting the difference between the bit position and the bit position one place above the decimal point as the precision loss of the mantissa, and a decrement means for outputting a value obtained by subtracting 1 from the exponent. Comparing the magnitudes of the two input data, the output of the decrementing means and the digit cancellation amount output from the preceding 1 detecting means, and outputting the smaller input data as the magnitude determination result, and the two input data. Comparing means for outputting a magnitude discriminating signal indicating which of the two is smaller; subtracting means for outputting a value obtained by subtracting the digit loss amount output from the preceding 1 detection means from the exponent; Of the two input data, 0 is output if the magnitude discriminating signal from the comparing means indicates that the output of the decrementing means is smaller, and otherwise, the output of the subtracting means is output as the operation result. Selection means for outputting as an exponent, and shift for outputting a value obtained by subjecting the mantissa to left shift processing with the magnitude determination result output from the comparing means as a shift amount, as the mantissa of the arithmetic processing result. An arithmetic processing unit comprising: 3. The arithmetic processing unit according to claim 2, wherein the comparing means propagates the magnitude relationship of each digit of the two input data from a higher digit to a lower digit to obtain the magnitude discrimination result. The shift means is provided with a minimum value selection circuit for sequentially outputting from the upper digit, and the shift means outputs left 2 ^k (k = 0, 1) corresponding to the lower n bits of the magnitude discrimination result output from the minimum value selection circuit. , 2, ..., n-1)
An arithmetic processing unit comprising bit shifters connected in cascade. 4. An arithmetic processing unit for performing shift processing on a mantissa of a floating point binary number and adjusting an exponent of the floating point binary number, wherein a preceding bit position of 1 in the mantissa is detected, And a leading 1 detection means for outputting the difference between the bit position and the bit position one place above the decimal point as the precision loss of the mantissa, and a decrement means for outputting a value obtained by subtracting 1 from the exponent. Comparing the magnitudes of two input data of the leading loss detecting unit and the exponent and comparing the magnitudes of the two input data, if the leading loss is smaller, the leading loss is used. In other cases, the leading loss is used. A comparison / selection means for outputting the output of the decrement means as a magnitude discrimination result and for outputting a magnitude discrimination signal indicating which of the two input data is smaller, and a digit output from the preceding 1 detection means. Drop amount A subtraction unit for outputting a value subtracted from the exponent; and a magnitude discriminating signal from the comparison and selection unit indicating that the digit cancellation amount output from the preceding 1 detection unit out of the two input data is smaller. In the case shown, selection means for outputting the output of the subtraction means, and 0 in other cases as the exponent of the arithmetic processing result, and the left and the left which have the magnitude determination result output from the comparison selection means as the shift amount. An arithmetic processing unit, comprising: a shift means for outputting a value obtained by applying a shift process to the mantissa as a mantissa of an arithmetic processing result. 5. The arithmetic processing device according to claim 4, wherein the comparison / selection unit propagates the magnitude relation of each digit of the two input data from a higher digit to a lower digit, and the magnitude discrimination result. Is sequentially output from the upper digit, and the shift means includes left 2 ^k (k = 0, 1, 1) corresponding to the lower n bits of the magnitude discrimination result output from the comparison / select circuit. 2, ..., n-1)
An arithmetic processing unit comprising bit shifters connected in cascade. 6. An arithmetic processing unit for performing shift processing on a mantissa of a floating point binary number and adjusting an exponent of the floating point binary number, wherein a preceding bit position of 1 in the mantissa is detected, And a leading 1 detection means for outputting the difference between the bit position and the bit position one place above the decimal point as the precision loss of the mantissa, and a decrement means for outputting a value obtained by subtracting 1 from the exponent. In order to output a value obtained by subtracting the digit loss amount output from the preceding 1 detection means as the subtraction result, and to output a magnitude determination signal indicating whether the index is less than or equal to the digit loss amount. Of the subtraction means and 0 when the magnitude discrimination signal from the subtraction means indicates that the exponent is equal to or less than the digit cancellation amount, and in other cases, the subtraction result from the subtraction means is calculated. Output as an index of And a first selecting means for controlling the output of the decrementing means when the magnitude discriminating signal from the subtracting means indicates that the exponent is equal to or less than the digit cancellation amount. Second selection means for respectively outputting the digit cancellation amount output from the detection means, and a value obtained by subjecting the mantissa to a left shift process using the output of the second selection means as a shift amount An arithmetic processing unit, comprising: a shift means for outputting a mantissa of a processing result. 7. An arithmetic processing unit for performing shift processing on a mantissa of a floating point binary number and adjusting an exponent of the floating point binary number, which detects a leading bit position of 1 in the mantissa, Further, the leading 1 detection means for outputting the difference between the bit position and the bit position one digit above the decimal point as the digit loss amount of the mantissa, and the digit loss amount output from the leading 1 detection means from the exponent. Subtracting means for outputting the subtracted value as a subtraction result, and for outputting a magnitude discrimination signal indicating whether or not the exponent is equal to or less than the digit loss amount, and the exponent is equal to or less than the digit loss amount. When the magnitude discrimination signal from the subtracting means indicates 0, in other cases, the first selecting means for outputting the subtraction result from the subtracting means as an exponent of the arithmetic processing result, and the exponent It is less than the amount of cancellation Second selection means for outputting the exponent when the magnitude discrimination signal from the subtraction means indicates, and otherwise, the digit cancellation amount output from the preceding 1 detection means, and A value obtained by subtracting 1 from the output of the second selecting means when the magnitude discriminating signal from the subtracting means indicates that the exponent is equal to or less than the digit cancellation amount, and in other cases, the second selecting An arithmetic processing unit, comprising: a shift processing means for outputting a value obtained by subjecting the mantissa to a left shift processing in which the output itself of the means is used as a shift amount, respectively, as a mantissa of the arithmetic processing result. 8. The arithmetic processing unit according to claim 7, wherein the shift processing means outputs a value obtained by subjecting the mantissa to a left shift processing using the output of the second selecting means as a shift amount. And a value obtained by subjecting the output of the left shifter to the right 1-bit shift processing when the magnitude discriminating signal from the subtracting means indicates that the exponent is equal to or less than the digit cancellation amount. ,
In other cases, the arithmetic processing device is provided with a right 1-bit shifter for outputting the output itself of the left shifter as a mantissa of each arithmetic processing result. 9. The arithmetic processing device according to claim 6, wherein the subtraction unit obtains the subtraction result by using the exponent and the digit loss amount output from the preceding 1 detection unit as two input data. And a subtraction circuit for generating the magnitude discrimination signal based on the borrow borrow generation signal and the borrow borrow propagation signal in consideration of the borrow propagation from the least significant digit to the most significant digit in the subtraction of the two input data. An arithmetic processing unit characterized by the above. 10. A function of performing an X-Y operation on n-bit input data X, Y and outputting a result, and carrying out borrow propagation from the 0th digit to the (n-1) th digit in the operation. A subtraction circuit having a function of generating and outputting a magnitude discriminating signal representing a magnitude relation X≤Y of the input data based on a considered borrow generation signal and a borrow propagation signal.