JP3187824B2 - Normalization circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a normalization circuit that normalizes an operation result of floating-point display data.

[Conventional technology]

FIG. 4 shows a conventional floating point display data arithmetic unit AL.
It is a block diagram which shows the part regarding U (addition / subtraction) and the normalization and rounding circuit.

Exponent part data constituting the first floating point display data
EA (for example, 11 bits) and mantissa data MA (for example,
53 bits), the exponent part data EB (11 bits) and the mantissa data MB (53 bits) constituting the second floating point display data are composed of the first floating point display data and the second floating point display data. The exponent part data EA and EB are given to the digit matching circuit 1 for matching the digits of the mantissa part data MA and MB by obtaining the magnitude relation and difference between them.
The output of the digit aligning circuit 1 adds or subtracts between the mantissa data MA and MB, one of which is digit-aligned, and outputs the third floating-point display data composed of the exponent data EC and the mantissa data MC. Output the mantissa data MC of
The output of this ALU2 is obtained from the MSB of the mantissa data MC to the LSB.
, And the digit shifter 5 that shifts the mantissa data MC to the left by the shift amount obtained by the priority encoder 3 and the shift amount obtained by the priority encoder 3. The output of the priority encoder 3 is digit-aligned. It is given to the control input of the shifter 5.

Further, the output of the digit shifter 5 is provided to a rounding circuit 7 that performs rounding in accordance with a rounding mode such as rounding in the + infinity direction and rounding in the -infinity direction.

 Next, the operation of the block diagram of FIG. 4 will be described.

In this conventional circuit, in order to perform complete rounding including normalization, guard bits GB and round bits RB used for rounding control and lower bits of the 53 bits of the mantissa data MA and MB are used at the time of normalization. Sticky bits SB for storing the result of the logical sum of all the low-order bit data overflowing from 53 bits of the mantissa data are provided, and the total is 56 bits.

First, first floating point display data, for example, 1.0000
··· 00000 _BIN × 2 ¹⁰⁰ and the second floating-point representation data, for example in order to perform the addition and subtraction of 1.0000 ··· 00000 _BIN × 2 ⁴ is exponent data EA (100) and the exponent part data EB
(4) must be adjusted to the larger one, that is, (100).

Therefore, the digit matching circuit 1 receives the exponent part data EA and the exponent part data EB, and obtains the magnitude relation and the difference.

Next, of the exponent part data EA and EB, the mantissa data MB corresponding to the smaller value (exponent part data EB) is right-shifted by the difference (96 bits) of the exponent part data EA and EB to change the digit. Match.

Before this digit alignment, a guard bit GB and a round bit RB (both are initially set to “0”) are added to the lower bits of the 53 bits, so that the bits are adjusted to a total of 55 bits.

As a result, the mantissa data MA whose digits have been aligned is "10000
.. 00000 (55 bits) ", and the mantissa data MB whose digits have been aligned becomes" 000000 ... 00000 (55 bits) ".
The bit data “1” of the LSB of the mantissa data MB overflows from the 54th bit, which is the LSB of the digit-aligned mantissa data MB. Therefore, a sticky bit SB is added to the lower order of the guard bit GB and the round bit RB, and the value of all bits of data overflowing from the 55th bit of the aligned mantissa data MB is added to the sticky bit SB. That is, "1" is stored in this case.

As a result, the mantissa data MA whose digits have been aligned is “1000
0 ... 00000 (56 bits) ", and the mantissa data MB whose digits have been aligned is" 00000 ... 00001 (56 bits) ".

Next, ALU2 performs addition or subtraction between the mantissa data MA and MB.

Now, for example, when the mantissa data MA is a subtrahend and the mantissa data MB is a subtraction in ALU2, subtraction "10000 ... 00000 (56 bits)"-"00000 ... 00001 (56 bits)" is performed. Certain mantissa data MC is "01111 ... 111
11 (56 bits) ", and the subtraction result is given to the priority encoder 3.

In order to perform normalization, the priority encoder 3 searches the mantissa part data MC, which is the result of the subtraction, for the number of bits from the MSB to find the first bit data “1”.

FIG. 5 is a circuit diagram showing details of the priority encoder 3 shown in FIG.

The priority encoder 3 inputs the 0th bit data B0 to the 54th bit data B54 excluding the sticky bit SB in the mantissa data MC given from the ALU2, and first inputs the 0th bit data B0. Are supplied to the first input of the OR circuit 101 and the first input of the EXOR circuit 201.

The bit data B1 of the first bit to the bit data B54 of the 54th bit are respectively supplied to the second inputs of the OR circuits 101 to 154, and the outputs of the OR circuits 101 to 153 are output to the second input of the adjacent OR circuits 102 to 154. 1 input, EXOR circuit 201 to 25
3 and a first input of EXOR circuits 202 through 254, respectively.

Further, the output of the OR circuit 154 is provided to the second input of the EXOR circuit 254.

In this way, the bit data B0 of the 0th bit is
Output O0, the first from the EXOR circuits 201 to 254
The output O1 to the 54th output O54 are output.

 Next, the operation of the circuit of FIG. 5 will be described.

First, it is assumed that mantissa data MC whose bit data B0 of the 0th bit is “1” is input.

At this time, the 0th output O0 becomes “1”, and the bit data B0 (“1”) of the 0th bit is input to the first input of the EXOR circuit 201 and the first input of the OR circuit 101, and the OR circuit 101 To 153 are supplied to first inputs of OR circuits 102 to 154.

Therefore, the outputs of the OR circuits 101 to 154 are the bit data B1 of the first bit to the bit data of the 54th bit.
All become "1" regardless of the value of B54.

Therefore, both the first input and the second input of the EXOR circuits 201 to 254 become “1”, and the EXOR circuits 201 to 254
, Ie, the first output O1 to the 54th output O54 are all "0".

Next, it is assumed that mantissa data MC in which the bit data from the 0th bit to the (K-1) th bit are “0” and the bit data of the Kth bit is “1”.

At this time, the 0th bit data B0 to (K
Since the -1) bit data B (K-1) is "0", the 0th output O0 first becomes "0", and the 0th bit data B0 ("0") is The output of the OR circuits 101 to (100 + K-1) is supplied to one input and the first input of the OR circuits 102 to (100 + K).

Since the values of the bit data B1 to B (K-1) of the first to (K-1) th bits given to the second inputs of the OR circuits 101 to (100 + K-1) are "0", the OR circuit 101
The output of 101 to (100 + K-1) is "0".

Therefore, the first and second inputs of the EXOR circuits 201 to (200 + K-1) are both "0", and the first outputs O1 to (K-1) th outputs which are the outputs of the EXOR circuits 201 to (200 + K-1). O (K-1) becomes "0".

Next, since the bit data BK of the K-th bit is “1”, the second input of the OR circuit (100 + K) becomes “1”, and the output of the OR circuit (100 + K) becomes “1”. Therefore, the output of the above-mentioned OR circuit (100 + K-1) is the first input, and the OR circuit (1
The K-th output OK, which is the output of the EXOR circuit (200 + K) whose output of (00 + K) is given as the second input, is “1”.

Further, the outputs of the OR circuits (100 + K) to 153 are supplied to the first inputs of the OR circuits (100 + K + 1) to 154.

Therefore, the output of the OR circuit (100 + K + 1) to the OR circuit 154 is the bit data B (K + 1) of the (K + 1) th bit.
Or "1" regardless of the value of the bit data B54 of the 54th bit.

Therefore, the output ("1") of the above-described OR circuit (100 + K) is given as the first input, and the output ("1") of the OR circuit (100 + K + 1) is given as the second input.
(K + 1) th output O (K +
1) becomes "0".

Further, both the first input and the second input of the EXOR circuits (200 + K + 2) to 254 become "1", and the EXOR circuit (200 + K + 2)
+ K + 1) to (254) th output O
(K + 1) to the 54th output O54 are all "0".

As described above, the priority encoder 3 detects which bit from the 0th bit of the mantissa data MC starts with “1”, and this bit number is used as the control input of the digit shifter 5. Given.

The digit alignment shifter 5 is provided with mantissa data MC which is the result of addition and subtraction of ALU2.
Priority encoder 3 given to the control input
Is shifted left by the mantissa data MC (55 bits obtained by adding the guard bit GB and the round bit RB).
Note that the 0th output O0 of the priority encoder 3 is "1"
In this case, the digit alignment shifter 5 does not shift the mantissa data MC to the left.

In this case, since the left shift amount is “1”, a shift result “11111... 11110 (55 bits)” is obtained.

In this case, since the bit data of the 55th bit disappears due to the left shift, “0” is inserted by zero extension.

The sticky bit SB is again added to the digit-aligned mantissa data MC (55 bits) to add the mantissa data MC “11”.
111 ... 11101 (56 bits) "are obtained.

Next, the mantissa data MC whose digits have been aligned is input to the rounding circuit 7, and the rounding circuit 7 outputs the 52nd bit, which is the LSB of the mantissa data MC excluding the guard bit GB, the mound bit RB, and the sticky bit SB. Is determined by +1 or not by the rounding mode.

Assuming that the rounded-out mantissa data MC is rounded toward infinity, the 52nd bit is incremented by 1, and all the bit data from the 52nd bit to the 0th bit carry up, The upstream carry propagates for 53 bits from the 52nd bit to the 0th bit.

[Problems to be solved by the invention]

The conventional floating-point display data normalization / rounding circuit is configured as described above. The time until the output is generated from the priority encoder 3 for obtaining the shift amount for the normalized shift is determined by the bit pattern of the mantissa data MC input to the priority encoder 3. When mantissa data MC in which data B0 to bit data B53 of the 53rd bit are “0” and bit data B54 of the 54th bit is “1” is input,
The 54 OR circuits 101 to 54 are output before the 54th output O54 becomes “1”.
154 and one EXOR circuit 254.

Therefore, there is a problem that it takes a long time until the output of the priority encoder 3 is determined.

. The time until an output is generated from the rounding circuit 7 is mainly determined by the number at which carry propagation occurs when the LSB of the mantissa data, which has been digitized by rounding, is incremented by one. When the mantissa data MC is input as "1" and the value is incremented by 1 in the rounding mode, carry propagation occurs from the 52nd bit to the 0th bit, and the processing time in the rounding circuit 7 is long. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a normalization circuit capable of performing at least normalization at high speed.

[Means for solving the problem]

The normalization circuit according to the present invention comprises: first floating point display data comprising first exponent part data and N-bit first mantissa data; second exponent part data and N-bit second mantissa data. The second floating-point display data composed of the mantissa data is input, and addition or subtraction is performed between the first mantissa data and the second mantissa data by an adder / subtractor. Among the N-bit third mantissa data constituting the third floating-point data, bit data “1” is searched for the upper M bits in order from the 0th bit to the (M−1) th bit. If done,
A first detection means for outputting a detection output, detecting which bit of the bit data "1" retrieved first is counted from the 0th bit, and detecting the number of bits, and a third mantissa data of N bits. The lower (N-M) bit is the M-th bit.
Bit data “1” in the order of bit to (N−1) th bit
, And when the search is performed, the second detection means for detecting the bit number of the bit data "1" searched first from the 0th bit, and the output of the first detection means The first digit aligning means shifts the N-bit third mantissa data to the left by the value of N, and the second digit shifts the N-bit third mantissa data to the left by the value of the output of the second detecting means. The second digit matching means and the output of the first digit matching means are selected and output when the detection output is provided from the first detection means, and the second output is selected when the detection output is not provided from the first detection means. Selecting means for selecting and outputting the output of the digit aligning means.

[Action]

In the present invention, first floating point display data composed of first exponent part data and N-bit first mantissa data, second exponent part data and N-bit second mantissa data And input or subtract between the first mantissa data and the second mantissa data by an adder / subtractor,
Among the N-bit third mantissa data constituting the third floating-point data output from the adder / subtracter by the first detection means, the upper M bits of the 0th to (M−1) th bits The bit data “1” is searched in order, and when the bit data “1” is searched, a detection output is output, and the bit number of the bit data “1” searched first from the 0th bit is detected, The second detection means selects the lower (N-
For the M) bits, bit data “1” is searched in order from the M-th bit to the N-th bit. When the bit data “1” is searched, the bit data “1” searched first corresponds to the bit number counting from the 0-th bit. The first digit aligning means shifts the N-bit third mantissa data to the left by the value of the output of the first detecting means, and the second digit aligning means shifts the data of the second detecting means. The N-bit third mantissa data is shifted to the left by the value of the output, and when the detection output is supplied from the first detection means by the selection means, the output of the first digit alignment means is selected and output. When the detection output is not given from the first detection means, the output of the second digit matching means is selected and output, so that the time required for the normalization processing can be reduced.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a normalization / rounding circuit according to the present invention.

Exponent part data constituting the first floating point display data
EA (for example, 11 bits) and mantissa data MA (for example,
53 bits), the exponent part data EB (11 bits) and the mantissa data MB (53 bits) constituting the second floating point display data are composed of the first floating point display data and the second floating point display data. The exponent part data EA and EB are given to the digit matching circuit 1 for matching the digits of the mantissa part data MA and MB by obtaining the magnitude relation and difference between them.
The output of the digit aligning circuit 1 adds or subtracts between the mantissa data MA and MB, one of which is digit-aligned, and outputs the third floating-point display data composed of the exponent data EC and the mantissa data MC. Output the mantissa data MC of
The output of the ALU 2 is a priority encoder 4a that searches for bit data “1” in the order of the 0th bit and the 1st bit of the mantissa data MC, and the output of the mantissa data MC The priority encoder 4b that searches for bit data "1" in order from the second bit to the LSB, the digit shift shifter 5 that shifts the mantissa data MC left by the shift amount obtained by the priority encoder 4a, and the shift obtained by the priority encoder 4b The output of the priority encoder 4a is provided to the control input of the digit alignment shifter 5, and the output of the priority encoder 4b is provided to the control input of the digit alignment shifter 6, where the mantissa data MC is shifted left by the amount. Has been given.

Further, the outputs of the digit shifters 4a and 4b are respectively
The rounding circuit 7 and the rounding circuit 8 perform rounding in accordance with a rounding mode such as rounding in the + infinity direction and rounding in the -infinity direction.

The outputs of the rounding circuits 7 and 8 are connected to the selector 9.
The output of the priority encoder 4 is provided to a control input of a selector 9 for controlling which output of the rounding circuit 7 and the rounding circuit 8 is to be selected.

 Next, the operation of the block diagram of FIG. 1 will be described.

In this embodiment, in order to perform complete rounding including normalization, guard bits GB and round bits RB used for rounding control and lower bits of the mantissa data MA and MB at the lower level of all 53 bits are used for normalization. Sticky bit SB for storing the result of ORing all bit data of lower bits overflowing from 54 bits of mantissa part data is provided.
56 bits.

First, first floating point display data, for example, 1.0000
..00000 _BIN × 2 ¹⁰⁰ and second floating point display data,
For example in order to perform the addition and subtraction of 1.0000 ··· 00000 _BIN × 2 ⁴ is exponent data EA (100) and the exponent part data EB
(4) must be adjusted to the larger one, that is, (100).

For this reason, the digit matching circuit 1 receives the exponent part data EA and the exponent part data EB, and obtains the magnitude relation and the difference.

Next, the mantissa data MB corresponding to the smaller value (exponent data EB) of the exponent data EA and EB is right-shifted by the difference (96 bits) between the exponent data EA and the exponent data EB. Adjust the digits.

In addition, at the time of this digit alignment, a guard bit GB and a round bit RB (both are “0” in an initial state) are added to the lower bits of the 53 bits to make a total of 55 bits.

As a result, the mantissa data MA whose digits have been aligned is "10000
.. 00000 (55 bits) "and the digit-aligned mantissa data MB is" 00000... 00000 (55 bits) ", and the LSB bit data" 1 "of the mantissa data MB is the mantissa data MB. Overflows from the 54th bit, which is the LSB of Therefore, a sticky bit SB is added to the lower order of the guard bit GB and the round bit RB, and the logical sum of the numerical values of all bits of the data overflowing from the 45 bits of the mantissa data MB is added to the sticky bit SB. 1 "is stored.

As a result, the mantissa data MA whose digits have been aligned is “1000
0 ... 00000 (56 bits) ", and the mantissa data MB whose digits have been aligned is" 00000 ... 00001 (56 bits) ".

Next, the ALU 2 executes addition or subtraction between the mantissa data MA and MB whose digits have been aligned.

Now, for example, when the mantissa data MA is a subtrahend and the mantissa data MB is a subtraction in ALU2, subtraction "10000 ... 00000 (56 bits)"-"00000 ... 00001 (56 bits)" is performed. Certain mantissa data MC is "01111 ... 111
11 (56 bits) ", and the subtraction result is provided to the priority encoders 4a and 4b.

First, in order to perform normalization, the priority encoder 4a searches the mantissa data MC, which is the result of the subtraction, for bit data “1” in the order of the 0th bit and the 1st bit, and searches for the priority. The encoder 4b searches the mantissa data MC for "1" in the order of the second bit to the 54th bit.

FIG. 2 shows the priority encoder shown in FIG.
FIG. 4 is a circuit diagram showing details of a configuration example of 4a.

The priority encoder 4a inputs the bit data B0 of the 0th bit and the bit data B1 of the 1st bit of the mantissa data MC given from the ALU2, and first, the bit data B0 of the 0th bit is input to the first input of the OR circuit 101. And EXOR circuit 2
It is provided to the first input of 01 and output as the 0th output O0.

Further, the first bit data B1 is supplied to the second input of the OR circuit 101, the output of the OR circuit 101 is supplied to the second input of the EXR circuit 201, and the first output O1 is output from the EXOR circuit 202.

 Next, the operation of the circuit of FIG. 2 will be described.

First, when mantissa data MC such that the bit data B0 of the 0th bit is “1” is input, the 0th output becomes “1”.

Further, since the bit data B0 (“1”) of the 0th bit is given to the first input of the EXOR circuit 201 and the first input of the OR circuit 101, the output of the OR circuit 101 is the bit data B1 of the first bit.
Is "1" regardless of the value of.

Therefore, “1” is given to both the first input and the second input of the EXOR circuit 201, and the first output O1, which is the output of the EXOR circuit 201, becomes “0”.

Next, when the mantissa data MC whose bit data B0 of the 0th bit is “0” is input, the 0th output O0 becomes “0”.
Becomes

Also, bit data B0 (“0”) of the 0th bit is given to a first input of the EXOR circuit 201 and a first input of the OR circuit 101,
The output of the OR circuit 101 has the same value as the value of the first bit data B1.

Therefore, since the first input of the EXOR circuit 201 is “0”, the first output O1 which is the output of the EXOR circuit 201 has the same value as the bit data B1 of the first bit, and the bit data of the first bit If B1 is "0", the 0th output O0 and the first output O1 are both "0". If the bit data B1 of the first bit is "1", the 0th output O0 and the first output O1 are each "0". "
And “1”.

FIG. 3 shows the priority encoder shown in FIG.
FIG. 4 is a circuit diagram showing details of a configuration example of 4b.

The priority encoder 4b inputs the bit data B2 of the second bit to the bit data B54 of the 54th bit of the mantissa data MC given from the ALU2, and first, the bit data B2 of the second bit is input to the first input of the OR circuit 103. And EXOR
It is provided to a first input of a circuit 203.

The bit data B3 of the third bit to the bit data B54 of the 54th bit are supplied to the second inputs of the OR circuits 103 to 154, and the output of the OR circuits 103 to 153 is connected to the adjacent OR circuit.
104-154 first input, EXOR circuits 203-253 second input
An input and a first input of EXOR circuits 204-254.

Further, the output of the OR circuit 154 is provided to the second input of the EXOR circuit 254.

The bit data B2 of the second bit becomes the second output O2, and the third output O3 to the 54th output O54 are output from the EXOR circuits 203 to 254, respectively.

 Next, the operation of the circuit shown in FIG. 3 will be described.

First, it is assumed that mantissa data MC in which the bit data B2 of the second bit is “1” is input.

At this time, the second output O2 becomes "1", and the bit data B2 ("1") of the second bit is input to the first input of the EXOR circuit 203 and the first input of the OR circuit 103, and the OR circuit 103 To 153 are supplied to first inputs of OR circuits 104 to 154.

Therefore, the outputs of the OR circuits 103 to 154 are the bit data B3 of the third bit to the bit data of the 54th bit.
All become "1" regardless of the value of B54.

Therefore, both the first input and the second input of the EXOR circuits 203 to 254 become “1”, and the EXOR circuits 203 to 254
, Ie, the third output O3 to the 54th output O54 are all "0".

Next, it is assumed that the mantissa data MC in which the bit data from the second bit to the (K-1) th bit is “0” and the bit data of the Kth bit is “1”.

At this time, the bit data B2 to (K
Since the -1) -bit bit data B (K-1) is "0", the second output O2 first becomes "0", and the 2-bit bit data B2 ("0") is The output of the OR circuits 103 to (100 + K-1) is supplied to one input and the first input of the OR circuits 104 to (100 + K).

Since the values of the bit data B3 to B (K-1) of the third to (K-1) th bits given to the second inputs of the OR circuits 103 to (100 + K-1) are "0", the OR circuit 103
The output from 103 to (100 + K-1) is "0".

Accordingly, the first and second inputs of the EXOR circuits 203 to (200 + K-1) are both "0", and the third outputs O3 to (K-1) th outputs which are the outputs of the EXOR circuits 203 to (200 + K-1). O (K-1) becomes "0".

Next, since the bit data BK of the K-th bit is “1”, the second input of the OR circuit (100 + K) becomes “1”, and the output of the OR circuit (100 + K) becomes “1”. Therefore, the output of the above-mentioned OR circuit (100 + K-1) is the first input, and the OR circuit (1
The K-th output OK, which is the output of the EXOR circuit (200 + K) whose output of (00 + K) is given as the second input, is “1”.

Further, the outputs of the OR circuits (100 + K) to 153 are supplied to the first inputs of the OR circuits (100 + K + 1) to 154.

Therefore, the output of the OR circuit (100 + K + 1) to the OR circuit 154 is the bit data B (K + 1) of the (K + 1) th bit.
Or "1" regardless of the value of the bit data B54 of the 54th bit.

Therefore, the output ("1") of the above-described OR circuit (100 + K) is given as the first input, and the output ("1") of the OR circuit (100 + K + 1) is given as the second input.
(K + 1) th output O (K +
1) becomes "0".

Further, both the first input and the second input of the EXOR circuits (200 + K + 2) to 254 become "1", and the EXOR circuit (200 + K + 2)
+ K + 1) to (254) th output O
(K + 1) to the 54th output O54 are all "0".

As described above, from the second bit to the 54th bit of the mantissa part data MC, the priority encoder 4b detects the first bit of the mantissa data MC, counting from the 0th bit, and detecting the number of the first "1". Is given to the control input of the digit shifter 6.

The mantissa data MC, which is the result of the addition and subtraction of ALU2, is given to the digit shifters 5 and 6.
And 6, the mantissa data MC (with the addition of the guard bit GB and the round bit RB, the value of the output of the priority encoders 4a and 4b given to its control input, respectively).
Bits) to the left.

Note that the 0th output O0 of the priority encoder 4a is “1” and the 0th output O0 of the priority encoder 4a is
When O0 and the first output O1 or the second output O2 to the 54th output O54 of the priority encoder 4b are all "0", the digit shifters 4a and 4b do not perform digit alignment, respectively.

In the case of this embodiment, since "1" is present in the first bit, the left shift amount "1" is output from the priority encoder 4a, and the shift result "1111" is output by the digit shifter 5.
1 ... 11110 (55 bits) "is obtained.

In this case, since the 55-bit data disappears due to the left shift, “0” is inserted by zero extension.

The sticky bit SB is again added to the digit-aligned mantissa data MC (55 bits) to add the mantissa data MC “11”.
111 ... 11101 (56 bits) "are obtained.

Next, the mantissa data MC whose digits have been aligned is input to the rounding circuit 7, which rounds the 52nd bit which is the LSB of the mantissa data MC excluding the guard bit GB, the round bit RB, and the sticky bit SB. + Depending on the rounding mode
Decide whether to do 1 or +1.

If the rounded-out mantissa data MC is rounded toward infinity, the bit data from the 52nd bit to the 0th bit are all “1”. When the 52 bits are incremented by 1, a carry occurs in all the bit data from the 53rd bit to the 1st bit, and carry carry propagates for 53 bits from the 52nd bit to the 0th bit.

The output of the rounding circuit 7 and the output of the rounding circuit 8 are given to the selector 9, and the output of the priority encoder 4a is given to the control input of the selector 9. The selector 9 outputs the 0th bit or the 0th bit of the mantissa data MC by the priority encoder 4a. Bit data "1" is detected as the first bit, and the first output O0 or the first output O1 of the priority encoder 4a is detected.
Is "1", the output of the rounding circuit 7 is selected and output, and conversely, the 0th output output from the priority encoder 4a
When both O0 and the first output O1 are "0", the rounding circuit 8
Select the output and output. In this case, the mantissa data MC
Since the bit data "1" is present in the first bit of, the selector 9 selects the output of the rounding circuit 7 and outputs it.

Next, the first floating point display data is 1.0000.
00000 _BIN × 2 ¹⁰⁰ and the second floating point display data are 1.
Description will be given of a case of 0000 ··· 00001 _BIN × 2 ^99.

First, in order to perform addition and subtraction between the first floating point display data and the second floating point display data, the exponent part data EA (100) and the exponent part data EB (99) must be larger, that is, (100) Must be adjusted to

For this reason, the digit matching circuit 1 receives the exponent part data EA and the exponent part data EB, and obtains the magnitude relation and the difference.

Next, of the exponent part data EA and EB, the mantissa data MB corresponding to the smaller value (exponent part data EB) is right-shifted by the difference (1 bit) between the exponent part data EA and EB to change the digit. Match.

As a result, when the guard bit GB, round bit RB and sticky bit SB are added, the mantissa data
MA is "10000 ... 00000 (56 bits)", mantissa data
The MB is "01000 ... 00100 (56 bits)".

Next, ALU2 performs addition or subtraction between the mantissa data MA and MB.

Now, for example, when the mantissa data MA is the subtrahend and the mantissa data MB is the subtrahend, the subtraction “10000... 00000 (56 bits)” − “01000... 00100 (56 bits)” is performed by the ALU2. Certain mantissa data MC is "00111 ... 111
00 (56 bits) ", and the result of the subtraction is provided to the priority encoders 4a and 4b.

First, in order to perform normalization, the priority encoder 4a searches the mantissa data MC, which is the result of this subtraction, by searching for bit data “1” in the order of the 0th bit and the 1st bit. The bit data "1" counted from the 0th bit is detected as the bit number. However, since the bit data "1" does not exist in the 0th and 1st bits of the mantissa data MC, the digit alignment is performed. The output of the priority encoder 4a is not supplied to the shifter 5, and the digit shifter 5 does not perform digit matching on the mantissa data MC.

Also, the priority encoder 4b stores the mantissa data
Bit data "1" in the order from the 2nd bit to the 54th bit of MC
Is detected, and the bit number of the bit data "1" retrieved from the 0th bit is detected.

In this embodiment, since the bit data “1” is present in the second bit of the mantissa data, the priority encoder 4 b outputs the left shift amount 2 with respect to the control input of the digit shifter 6.

The digit alignment shifter 6 outputs the mantissa data MC (guard bit).
2 for 55 bits (GB plus round bit RB)
Bit shift is performed to the left. At this time, the bit data of the 53rd to 54th bits of the mantissa data MC disappears. Therefore, the bit data “0” is added to the 53rd to 54th bits of the mantissa data MC by zero extension. Is inserted, and as a result, mantissa data “11111... 10000 (56 bits)” is output.

The rounding circuit 8 determines whether the digit-aligned mantissa data MC is incremented by one or not by a rounding mode. If the rounding mode is rounding toward + infinity, the rounded mantissa is set. +1 is added to the 52nd bit of the data MC.

Since the bit data of the 52nd bit of the mantissa data MC input to the rounding circuit 8 is “0”, the rounding circuit 8 outputs mantissa data “11111... 11111” as a result of the rounding.
There is no carry due to rounding.

The output of the rounding circuit 7 and the rounding circuit 8 is given to the selector 9, and the priority encoder 4 a connected to the control input of the selector 9 outputs the 0th part of the mantissa data MC.
Since bit data “1” is not detected in the bit and the first bit, the selector 9 selects and outputs the output of the rounding circuit 8.

As described above, in this embodiment, the priority encoder 4a searches for the bit data "1" for the 0th and 1st bits of the mantissa data MC, and the priority encoder 4b searches for the second data of the mantissa data MC. Bit data “1” is searched for the 54th bit from the bit,
The mantissa data MC is output to the rounding circuit 7 and the rounding circuit 8, respectively.

The priority encoder 4a outputs the 0th mantissa data MC.
Since only the bit and the first bit are searched, even when the bit data of the 0th bit is “0” and the bit data of the first bit is “1”, the time required for the output of the priority encoder 4a to be determined is compared. The target is short.

On the other hand, in the case of the priority encoder 4b,
It is necessary to search the second bit to the 54th bit of the mantissa data MC. If the bit data from the 2nd bit to the 53rd bit is “0” and the 54th bit data is “1”, the priority encoder The time required to determine the output of 4b is longer than that of the priority encoder 4a.

Mantissa data MC by priority encoder 4a
When bit data "1" is detected in the 0th bit or the 1st bit, the digit alignment shifter 5 sets the mantissa data MC to 0.
The bit is shifted left by one bit (that is, no digit alignment is performed) or one bit, and bit data “0” is inserted into the disappeared bit of the 54th bit by zero extension.

At this time, the bit data of the 52nd bit of the mantissa data MC may be “0” or “1” depending on the values of the mantissa data MA and the mantissa data MB.

The rounding circuit 7 performs +1 in the rounding mode for the 52nd bit of the mantissa data MC. At this time, carry propagation for a maximum of 53 bits may occur, and the time required for the rounding process of the rounding circuit 7 May be relatively long.

On the other hand, in the case of the priority encoder 4b,
When bit data "1" is detected in the second to 54th bits of the mantissa data MC, the digit shifter 5 shifts the mantissa data MC left by 2 to 53 bits, and shifts the third to 54th bits. Bit data “0” is inserted into the bit where the bit disappeared by zero extension.

At this time, the bit data of the 52nd bit of the mantissa data MC always becomes “0” due to the bit extension.

The rounding circuit 8 adds +1 to the 52nd bit of the mantissa data MC in the rounding mode. At this time, only the bit data “0” of the 52nd bit of the mantissa data MC becomes “1”, and the rounding circuit 8 The time required for the processing in 8 can be shorter than in the case of the rounding circuit 7.

Therefore, in this embodiment, when the mantissa data MC for which the bit data “1” is searched by the priority encoder 4a is input, the time required for processing in the priority encoder 4a is short, and in this case, rounding is performed. The time required for the rounding process of the circuit 7 may take a long time. Conversely, the bit data "1" is not searched by the priority encoder 4a, and the bit data "1" is searched by the priority encoder 4b. When the mantissa data MC is input, the processing in the priority encoder 4b may take a long time. In this case, since the rounding process of the rounding circuit 8 is short, the unknown mantissa as a whole is The time when normalization and rounding is performed on the input data MC is shortened, and the normalization and rounding processing is performed at high speed. Can do it.

In terms of hardware, the priority encoders 4a and 4b do not increase the amount of hardware only by dividing the conventional priority encoder 3 into two parts. 1
Digit shifter 6 for bit shifting
Is simply added to the conventional circuit, and the circuit of the embodiment can be realized with a small increase in the amount of hardware as a whole.

〔The invention's effect〕

As described above, according to the present invention, the first exponent part data and the N-bit first mantissa data
, Floating-point display data, second exponent part data, and second floating-point display data composed of N-bit second mantissa data are input, and the first mantissa data and the second mantissa data are added and subtracted by an adder / subtracter. The addition or subtraction is performed between the two mantissa data, and among the N-bit third mantissa data constituting the third floating-point data output from the adder / subtractor,
For the upper M bits, bit data “1” is searched in the order of the 0th bit to the (M−1) th bit. When the bit data “1” is searched, a detection output is output and the bit data “1” searched first. Detection means for detecting the number of a bit counted from the 0th bit, and the third bit of the N bits
Bit data "1" is searched for the lower (NM) bits in order from the (M) th bit to the (N-1) th bit in the mantissa data, and when the bit data is searched, the bit data searched first Second detection means for detecting the number of bits "1" is counted from the 0th bit, and the N-bit third mantissa data is left-shifted by the output value of the first detection means. Detection outputs are provided from the first digitizing means, the second digitizing means for shifting the N-bit third mantissa data to the left by the output value of the second detecting means, and the first detecting means. And selecting means for selecting and outputting the output of the first digit matching means when the output is given, and selecting and outputting the output of the second digit matching means when no detection output is given from the first detecting means. Therefore, the normalization process can be performed simultaneously in two paths, There is an effect that normalization processing can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a normalization / rounding circuit according to the present invention, FIGS. 2 and 3 are circuit diagrams showing a configuration example of the priority encoder shown in FIG. 1, and FIG. And FIG. 5 is a circuit diagram showing the priority encoder shown in FIG. In the figure, 1 is a digit matching circuit, 2 is an ALU, 3, 4a and 4b.
Is a priority encoder, 5 and 6 are digit shifters, 7 and 8 are rounding circuits, 9 is a selector, 101 to 154
Is an OR circuit, and 201 through 254 are EXOR circuits. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. First floating-point display data comprising first exponent data and N-bit first mantissa data, second exponent data and N-bit second mantissa data And the second floating-point display data, and normalizes the output of the adder / subtractor that performs addition or subtraction between the first mantissa data and the second mantissa data. A normalizing circuit that performs an operation from the 0th bit to the (M−M−b) of the upper M bits of the N-bit third mantissa data constituting the third floating-point data output from the adder / subtractor. 1) Bit data "1" is searched in the order of bits, and if it is searched, a detection output is output, and the bit number of the first searched bit data "1" from the 0th bit First means for detecting Of the third mantissa data of N bits, the lower (N-
For the M) bits, bit data “1” is searched in order from the Mth bit to the (N−1) th bit.
Second detecting means for detecting the bit number of the bit data "1" retrieved first from the 0th bit and detecting the number of the bit, and the value of the output of the first detecting means, the value of the Nth bit First digit alignment means for shifting left the mantissa data of 3 to the left; second digit alignment means for shifting left of the N-bit third mantissa data by the value of the output of the second detection means; Selecting the output of the first digit alignment means when the detection output is provided from the first detection means, and outputting the output when the detection output is not provided from the first detection means; A selection means for selecting and outputting the output of the digit matching means.