JPH06120423A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a preferred capacitor insulating film by adopting a ferroelectric substance having a Curie point of -20 deg.C or lower and using it in a paraelectric phase thereby to prevent polarization and reversal. CONSTITUTION:A thin film of a solid solution (XBaZrO3.cl-X) containing BaZrO3 by 45% or more is adopted as a capacitor insulating film. After a ground electrode 15 of pt is formed, With a photoresist as a mask it is patterned by dry etching. On its surface a solid solution thin film 16 is formed by a high-frequency magnetron sputtering process. The thin film composition is X=0.47. Since it has a Curie point of -20 deg.C or lower it is paraelectric in the guaranteed working temperature range (-20 deg.C-150 deg.C) of DRAMs, no polarization and reversal occurs. With this, a sufficient amount of accumulated charge can be acquired by a capacitor with a simple structure and a small area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device equipped with a large-capacity capacitor having a small area suitable for a large-scale integrated circuit using a high dielectric.

[0002]

2. Description of the Related Art In recent years, with the high integration of semiconductor devices, individual elements have been miniaturized. For example, DRAM (Dynamic Random Access Memory) has been highly integrated at a rate of 4 times in 3 years.
Mass production of megabit memory has started. This high integration has been achieved by increasing the chip area (1.4 times for each generation) and the memory cell area (36% for each generation, about 1/3 times). The reduction of the memory cell area has been achieved by the miniaturization of elements. However, due to the decrease in storage capacity due to miniaturization, adverse effects such as a decrease in signal-to-noise (SN) ratio and signal inversion due to incidence of α-rays become apparent, and securing reliability is a major problem. That is, in order to reduce the capacitor area by 1 / k while keeping the capacitance constant, the film thickness of the insulating film must be reduced to 1 / k. Thinning of SiO ₂ and Si ₃ N ₄ has already progressed to the limit, and further thinning has become extremely difficult. In order to solve this problem, a memory cell having a large capacitor area in a small plane area has been developed by three-dimensionalization.
Even with such a method, there is a problem of economical efficiency that the miniaturization of the memory cell and the complexity of the structure progress, the manufacturing technique becomes very difficult, and the development / manufacturing cost remarkably increases.

Further, for example, an analog circuit used for mobile communication requires a capacitor having a large capacity, but if it is made using a conventional dielectric film for a capacitor, a large area is required. Therefore, it cannot be integrated into an LSI, and an external capacitor is used.
However, in order to realize a smaller and lighter mobile communication device, one-chip LSI is required. As described above, in order to make a circuit including a large-capacity capacitor into an LSI, a capacitor using a material having a large dielectric constant capable of accumulating large charges in a small area is required.

Ferroelectrics typified by lead zirconate titanate (PZT) are conventional dielectric films for capacitors such as SiO ₂ and
Since it has a dielectric constant 100 to 1000 times that of Si ₃ N ₄ , it can be used as a capacitor insulating film to realize a large-capacity capacitor with a small area. For example, if it is used for a DRAM, it is possible to store a sufficient charge for circuit operation in a minute (0.1 to 0.2 μm ² ) memory cell of the gigabit generation simply by combining it with a relatively simple capacitor structure. As a DRAM using a ferroelectric thin film as a capacitor insulating film, Japanese Patent Publication No. 3-16
5557 and Japanese Patent Publication No. 3-256356.

[0005]

A ferroelectric material has a strong interaction between permanent dipoles and causes an electric polarization called a spontaneous polarization even when an external electric field is not applied. The spontaneous polarization is inverted by the external electric field. It is a substance that can. Therefore, the relationship between the polarization P of the ferroelectric substance and the applied electric field E is as shown in FIG. This relationship is called a history curve, and the electric field when the polarization becomes zero is called the anti-electric field E _C. When a ferroelectric material with such characteristics is used for the capacitor insulating film, if the direction of the external electric field is reversed and an electric field larger than the mine field is applied in the opposite direction, a polarization reversal current will flow. become. Therefore, when used in an analog LSI, there is a problem that it causes a problem in circuit operation.

Further, there is a problem that characteristics are deteriorated due to fatigue of the thin film due to polarization reversal. Particularly in DRAM, in order to reduce the voltage applied to the capacitor insulating film and ensure the reliability of the capacitor insulating film, the plate voltage Vcp is set to 1/2 of the power supply voltage, and either "0" or "1" is set. by the even _{± (V DD -V SS) /} 2 voltage is applied as the case of recording information, half V _DD plate that by reducing the voltage applied to the capacitor insulating film to ensure the reliability of the capacitor insulation film
The scheme is used. However, in a DRAM using a ferroelectric thin film as a capacitor insulating film, when Ec · t> V _DD / 2, the polarization of the ferroelectric material is reversed every time information is read or written, and the characteristics deteriorate due to fatigue. There is a problem that it ends up.

FIG. 3 summarizes the relationship between the film thickness t of the PZT thin film and the coercive electric field Ec that have been reported so far. Ec increases as the film thickness decreases. When the half V _DD plate method is used, the electric field applied to the capacitor insulating film of each generation is calculated and shown in the figure. As can be seen from this figure, even if PZT thin film is used in 1G, 4G bit DRAM, halfV
There is a possibility that the _DD plate method can be adopted. However, if there are variations in the anti-electric field in the film, polarization reversal will occur in the portion where the anti-electric field is small, which is a problem from the aspect of reliability.

The most widely studied ferroelectric, PZT, has a dielectric constant that increases as it approaches the phase transition temperature called the Curie point, and reaches its maximum at the Curie point. Even in the temperature range in which a semiconductor device is usually used, the capacitance changes due to the temperature change of its dielectric constant, which is a serious problem when used in an analog LSI.

[0009]

[Means for Solving the Problems] Solid solution ( _x BaZrO ₃ · _(1-x)
PbTiO ₃ ), a solid solution thin film containing 45% or more of BaZrO ₃ is adopted as the capacitor insulating film.

[0010]

The operation guaranteed temperature range of the semiconductor device is −20 ° C. to 1
Since the temperature is 25 ° C., by using a ferroelectric material having a Curie point at −20 ° C. or lower and using it in the paraelectric phase, it is possible to avoid the reliability problem due to polarization reversal.

In solid solution ( _x BaZrO ₃ · _(1-x) PbTiO ₃ ), BaZrO
_The solid solution containing 45% or more of ₃ has a Curie point of -2.
When the temperature is 0 ° C. or less, it does not cause polarization reversal because it is paraelectric within the operation guarantee temperature range of DRAM. Especially, x = 0.45 ~
The composition of 0.5 has a large relative permittivity of 1500 to 2000 and a small change in the relative permittivity with temperature, and is suitable as a capacitor insulating film. Therefore, if this material is used as a capacitor insulating film, a highly integrated semiconductor device can be realized.

[0012]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows a DRAM using the capacitor of the present invention.
It is a sectional view of a memory cell. Except that a thin film of solid solution _{(x BaZrO 3 · (1-} x) PbTiO 3) in the capacitor insulating film is basically has the same structure as those described in KOKOKU No. 3-256356 . Here, 1 is a p-semiconductor substrate, 2 is an element isolation insulating film, 3 is a gate oxide film, 4 is a word line serving as a gate electrode, 5, 6, 7, 10, 12, 13 are interlayer insulating films, and 6 is n. -Type impurity diffusion layer (phosphorus), 9,14
Is a contact plug, 11 is a bit line, 15 is a lower electrode, 16 is a solid solution ( _x BaZrO _{3. (1-x)} PbTiO ₃ ) thin film, 1
7 is a plate electrode.

4 to 8 are sectional views showing the steps of manufacturing the memory cell according to this embodiment. First, as shown in FIG. 4, the switching transistor is a conventional MOSF.
It is formed by the ET forming process. SiO ₂ 7 with a thickness of 50 nm and Si with a thickness of 400 nm are formed on the entire surface by a known CVD method.
₃ N ₄ was deposited by the CVD method, respectively, and the Si ₃ N ₄
The insulating film 8 is embedded between the word lines by etching.

Next, as shown in FIG. 5, the portion where the bit line is in contact with the n-type diffusion layer on the substrate surface and the portion where the storage electrode is in contact with the n-type diffusion layer on the substrate surface are formed by a known photolithography method. Open using a dry etching method. CV
After depositing polycrystalline silicon containing an n-type impurity having a thickness of 400 nm by the D method, etching is performed by the film thickness, so that the polycrystalline silicon 51 is formed inside the hole formed by the above-described etching. 52 is embedded.

SiO ₂ 10 having a thickness of 50 nm is deposited by the CVD method, and only the portion where the bit line is in contact with the polycrystalline silicon 52 is opened by using the known photolithography method and dry etching method. Next, the bit line 11 is formed. A laminated film of metal silicide and polycrystalline silicon was used as the material of the bit line. On top of this, 200 nm thick SiO ₂ 1
2 is deposited. The SiO ₂ 12 and the bit line 11 are processed by the known photolithography method and dry etching method,
Make the bit line a desired pattern. Next, film thickness 150n
m of SiO ₂ is deposited by the CVD method and is etched by the dry etching method to form a sidewall spacer of SiO _{2 on} the side wall of the bit line to insulate the bit line (FIG. 6).

Only the portion where the storage electrode is in contact with the polycrystalline silicon 51 is opened by the known photolithography method and dry etching method. SiO ₂ 1 is formed on this by CVD method.
3 was deposited and flattened by the etch back method. BPS
A silicon oxide film type insulating film such as G may be deposited and planarized. In that case, the insulating film needs to have a film thickness sufficient to fill the step below and planarize it. A memory section contact hole for contacting the storage capacitor section with the polycrystalline silicon 51 is opened by using the known photolithography method and dry etching method, and the contact hole is formed by the polycrystalline silicon 14
Embed with (Fig. 7).

After forming the Pt base electrode 15, this was patterned by a dry etching method using a photoresist as a mask. Solid solution _(x BaZrO ₃ · on this surface _(1-x) PbTi
A thin film 16 of O ₃ ) is formed. In this example, a 100 nm-thick ( _x BaZrO _3
(1-x) PbTiO ₃₎ to form a solid solution thin film. The composition of the thin film is x =
It was set to 0.47. A 9: 1 mixed gas of argon and oxygen was used as the sputtering gas, and the gas pressure was 0.1 Torr. The substrate temperature during sputtering is about 200 ° C,
Heat treatment was performed at 550 ° C for 2 hours in an oxidizing atmosphere.

Although the sputtering method was used this time, ( _x BaZrO _{3
As a} method of forming the _(1-x) PbTiO ₃ ) solid solution thin film, a known sol-gel method, a CVD method, a MOCVD method or the like may be used. Next, the plate electrode 17 is deposited to complete the storage capacitor portion of the memory cell. Finally, an interlayer insulating film is formed, an Al wiring is formed thereon, and the memory cell is completed.

The present invention is not limited to the semiconductor device and the dynamic random access memory, but can be applied to all kinds of semiconductor devices. An example thereof will be described using the example of the high-speed bipolar memory shown in FIG. This semiconductor memory device is used, for example, as a cache memory of a super computer. This semiconductor memory device uses PtSi-Si as a capacitor to prevent soft error due to α-ray incidence.
The Schottky barrier diode (SBD) junction capacitance of is used. About 500f to prevent soft error
Capacitance of F is required, but capacitance density of SBD is 3.4f
Since it is not possible to exceed F / μm2, we could not use a large area SBD. Formed in parallel with a small area capacitor using a material with a large dielectric constant and a small area SBD,
The area of the memory cell can be reduced by using a diode equivalent circuit having a small area as a whole. A high-speed bipolar memory using a metal oxide such as tantalum or titanium as the dielectric material of the above small area capacitor is disclosed in JP-A-61-212053. In this embodiment, the semiconductor device of the present invention is used as this small area capacitor. FIG. 9 is a partial cross-sectional view of the high speed bipolar memory cell of this embodiment. In the figure, 90 is a p-type silicon substrate, 91 is an n + buried layer, 92 is an element isolation insulating film,
93 is an n-type epitaxial silicon layer, 94 is a heavily doped n-type epitaxial silicon layer, 95 is PtSi, 96
Is a silicon oxide film, 97 is a ( _x BaZrO ₃ · _(1-x) PbTiO ₃ ) solid solution thin film, 98 is a Ti wiring layer, and 99 is an Al wiring layer. PtSi on the n-type epitaxial silicon layer of 93 forms a Schottky contact, and a Schottky diode is formed between the Al / TiN wiring and the n + buried layer. On the other hand, PtSi on the heavily doped n-type epitaxial silicon layer of 94 is in ohmic contact. The PtSi in this portion is used as the base electrode of the capacitor. In this example, since the x = 0.47 ( _x BaZrO ₃ · _(1-x) PbTiO ₃ ) solid solution thin film was used as the capacitor insulating film, its relative dielectric constant was 1100 and a film thickness of 100 nm was about 100 fF / unit area. Capacitances as high as μm2 were obtained. This is about 10 times the capacitance density when Ta ₂ O ₅ is used, and the capacitor area that was conventionally required to be 50 μm ² was 5 μm.
Can be ² . As a result, the cell area could be significantly reduced.

FIG. 10 shows the temperature characteristic of the relative dielectric constant of the capacitor using the ( _x BaZrO _{3. (1-x)} PbTiO ₃ ) solid solution. x = 0.
It can be seen that in the composition of 45 to 0.5, the relative permittivity is as large as 1500 to 2000 in the temperature range of 0 ° C to 125 ° C, and the change of the relative permittivity with temperature is small. In addition, FIG. 11 shows ( _x BaZrO ₃ · _(1-x) PbT of x = 0.47 prepared by the RF magnetron sputtering method.
The change in the relative permittivity of the iO ₃ ) solid solution thin film with temperature was measured and compared with other ferroelectric thin films. ( _x BaZrO ₃・_(1-x) Pb
It was found that the change in relative permittivity of TiO ₃ ) solid solution thin film was very small and had excellent characteristics.

[0022]

According to the present invention, since a capacitor having a simple structure and a small area can secure a sufficient amount of accumulated charges, high integration of a semiconductor device having a capacitor can be easily realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a first embodiment of the present invention.

FIG. 2 is a polarization-electric field characteristic of a ferroelectric substance.

FIG. 3 is a relationship between a film thickness t of a PZT thin film and a coercive electric field Ec.

FIG. 4 is a first sectional view showing a step of the first embodiment of the present invention.

FIG. 5 is a second sectional view showing a step of the first embodiment of the present invention.

FIG. 6 is a third cross-sectional view showing the process of the first embodiment of the present invention.

FIG. 7 is a fourth cross-sectional view showing the process of the first embodiment of the present invention.

FIG. 8 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 9 is a sectional view of a second embodiment of the present invention.

FIG. 10 is a temperature characteristic of relative permittivity of x (BaZrO3) · 1-x (PbTiO3) solid solution.

FIG. 11 is a comparison of temperature changes in relative permittivity of x (BaZrO3) · 1-x (PbTiO3) solid solution thin films and other ferroelectric thin films.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Inter-element isolation oxide film, 3 ... Gate oxide film, 4 ... Word line, 5, 7, 8, 10, 12, 13 ... Interlayer insulating film, 6 ... Impurity diffusion layer, 9, 14, 51, 52 ... Contact plug, 11 ... Bit line, 15 ... Lower electrode, 16
_{... (x BaZrO 3 · (1} -x) PbTiO 3) solid solution thin film, 17 ... plate electrode, 90 ... p-type silicon substrate, 9 ... n + buried layer,
92 ... Element isolation insulating film, 93 ... N type epitaxial silicon layer, 94 ... Highly doped n type epitaxial silicon layer, 95 ... PtSi, 96 ... Silicon oxide film,
97 ... ( _x BaZrO ₃ · _(1-x) PbTiO ₃ ) solid solution thin film, 98 ... Ti
Wiring layer, 99 ... Al wiring layer.

Claims (6)

[Claims] 1. A perovskite type compound represented by the general chemical formula ABO ₃ which is a thin film of a solid solution containing barium and lead as A atoms and titanium and zirconium as B atoms, and is usually used in the temperature range of -20 ° C. to 150 ° C. A semiconductor device characterized by having a capacitor that uses a dielectric thin film as an insulating film. 2. A perovskite type compound represented by the chemical formula ( _x BaZrO _{3. (1-x)} PbTiO ₃ ), wherein the composition range is 0.45 ≦
A semiconductor device having a capacitor using a thin film having one composition selected from x ≦ 0.55 as an insulating film. 3. A semiconductor memory device including one switching transistor and a memory cell having one charge storage capacity, wherein the insulating film of the charge storage capacity is an insulating film. A semiconductor device using the thin film of. 4. A perovskite type compound represented by the general chemical formula ABO _3, which is a thin film of a solid solution containing barium and lead as A atoms and titanium and zirconium as B atoms and is usually used in the temperature range of -20 ° C. to 150 ° C. What is claimed is: 1. A method of manufacturing a semiconductor device, which has a capacitor using a thin film that is a dielectric as an insulating film. A method of manufacturing a semiconductor device, which is characterized in that the thin film is formed by a high frequency magnetron sputtering method. 5. A method of manufacturing a semiconductor device according to claim 4, wherein a sintered body having the same composition as a desired thin film is used as the target. 6. The method of manufacturing a semiconductor device according to claim 4, wherein an amorphous thin film having the same composition as a desired thin film is formed and then heat-treated in an oxidizing atmosphere to form a perovskite structure. A method for manufacturing a semiconductor device, characterized in that a crystallized thin film is obtained.