JPH06120313A - Tab-system semiconductor device and inspection method thereof - Google Patents

Tab-system semiconductor device and inspection method thereof

Info

Publication number
JPH06120313A
JPH06120313A JP26243292A JP26243292A JPH06120313A JP H06120313 A JPH06120313 A JP H06120313A JP 26243292 A JP26243292 A JP 26243292A JP 26243292 A JP26243292 A JP 26243292A JP H06120313 A JPH06120313 A JP H06120313A
Authority
JP
Japan
Prior art keywords
inspection
semiconductor device
probe
tab
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26243292A
Other languages
Japanese (ja)
Inventor
Koji Taniguchi
康治 谷口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP26243292A priority Critical patent/JPH06120313A/en
Publication of JPH06120313A publication Critical patent/JPH06120313A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To raise the accuracy and efficiency of property inspection by seeing that one can know whether a probe needle for performing the property inspection of a TAB-system semiconductor device is good or bad in every property inspection. CONSTITUTION:A dummy pattern (5c) exclusively used for inspection is made partially in advance in the conductive pattern (5) of a TAB-system semiconductor device (1) where the semiconductor pellet (6) arranged in the through hole (4) of an insulating film (3) and the conductive pattern (5) made in the insulating film (3) are connected with each other. Two probe needles (9) of the probe cards of are brought into contact with the dummy pattern (5c), and the contact resistance between these two pieces and the dummy pattern (5c) is measured, and from the result of that measurement, the contact resistance between other probe needle (9) and the conductive pattern (5) is estimated, thus it is judged whether the top of the probe needle (9), which changes the contact resistance with the conductive pattern (5), is polluted by oil or whether its spring property is good or bad.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、絶縁フィルムの片面に
形成された複数条の導電パターンと、絶縁フィルムに形
成された透孔内に配置された半導体ペレットの電極とを
熱圧着接続したTAB(Tape Automated Bonding)式半
導体装置とその検査方法で、液晶ディスプレイのドライ
バーなどの多ピン構造の半導体装置に適用される。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TAB in which a plurality of conductive patterns formed on one surface of an insulating film and electrodes of semiconductor pellets arranged in through holes formed in the insulating film are thermocompression bonded. (Tape Automated Bonding) type semiconductor device and its inspection method, applied to multi-pin structure semiconductor device such as driver of liquid crystal display.

【0002】[0002]

【従来の技術】液晶ディスプレイのドライバーなどに使
用されるTAB式半導体装置の従来例と、その検査装置
例を、図6乃至図9を参照して説明する。
2. Description of the Related Art A conventional example of a TAB type semiconductor device used for a driver of a liquid crystal display and an example of its inspection device will be described with reference to FIGS.

【0003】図6及び図7に示されるTAB式半導体装
置(1')は、絶縁フィルム(3)の片面に導電パターン
(5)を形成したTABテープ(2')と、絶縁フィルム
(3)に形成された透孔(4)内に配置された半導体ペレ
ット(6)を備える。絶縁フィルム(3)の導電パターン
(5)は、絶縁フィルム(3)に被着した銅箔をエッチン
グして形成される。導電パターン(5)は、絶縁フィル
ム(3)の透孔(4)の周辺部に小ピッチで複数条が形成
され、それぞれに透孔(4)内に延在するインナーリー
ド部(5a)を有する。また、各導電パターン(5)は、
透孔(4)に近い所定の箇所に幅広の検査パッド部(5
b)を有する。
The TAB type semiconductor device (1 ') shown in FIGS. 6 and 7 includes a TAB tape (2') having a conductive pattern (5) formed on one surface of an insulating film (3) and an insulating film (3). The semiconductor pellet (6) is arranged in the through hole (4) formed in the. The conductive pattern (5) of the insulating film (3) is formed by etching the copper foil adhered to the insulating film (3). The conductive pattern (5) has a plurality of stripes formed at a small pitch around the through hole (4) of the insulating film (3), and each has an inner lead portion (5a) extending inside the through hole (4). Have. In addition, each conductive pattern (5)
Wide test pad (5) at a specified location near the through hole (4)
b).

【0004】半導体ペレット(6)の上面周辺部には、
小ピッチで複数のバンプ電極(7)が形成される。この
複数のバンプ電極(7)に、対応する導電パターン(5)
のインナーリード部(5a)の先端部が熱圧着で接続さ
れる。
In the peripheral portion of the upper surface of the semiconductor pellet (6),
A plurality of bump electrodes (7) are formed with a small pitch. A conductive pattern (5) corresponding to the plurality of bump electrodes (7)
The tips of the inner lead portions (5a) are connected by thermocompression bonding.

【0005】上記TAB式半導体装置(1')の特性検査
装置を図8に示すと、これはプローブカード(8)と押
圧プレート(15)を備える。プローブカード(8)は、
平坦な上面に複数のプローブニードル(9)を斜め上方
に突設している。各プローブニードル(9)の先端は、
TABテープ(2')の導電パターン(5)の検査パッド
部(5b)に対応する位置にあり、この各先端はプロー
ブカード(8)から同一高さにある。
FIG. 8 shows a characteristic inspection apparatus for the TAB type semiconductor device (1 '), which comprises a probe card (8) and a pressing plate (15). The probe card (8)
A plurality of probe needles (9) are provided obliquely upward on a flat upper surface. The tip of each probe needle (9)
It is located at a position corresponding to the inspection pad portion (5b) of the conductive pattern (5) of the TAB tape (2 '), and the respective tips are at the same height from the probe card (8).

【0006】プローブカード(8)の真上に押圧プレー
ト(15)が平行に位置決めされて配置され、この押圧プ
レート(15)の下に上下逆にしたTAB式半導体装置
(1')が位置決め保持される。
A pressing plate (15) is positioned and arranged in parallel directly above the probe card (8), and an upside down TAB semiconductor device (1 ') is positioned and held under the pressing plate (15). To be done.

【0007】図8の状態で押圧プレート(15)を下げ
て、図9に示すように、まずTABテープ(2')の下面
の導電パターン(5)の検査パッド(5b)を、対応する
プローブニードル(9)の先端に接触させてから、更に
200μm程度押し下げる。この押し下げで、プローブ
ニードル(9)が弾性変形して、、その先端が検査パッ
ド部(5b)に所望の弾圧力で確実に接触する。図9の
状態が維持されて、TAB式半導体装置(1')の特性検
査が行われる。
In the state of FIG. 8, the pressing plate (15) is lowered, and as shown in FIG. 9, first, the inspection pad (5b) of the conductive pattern (5) on the lower surface of the TAB tape (2 ') is connected to the corresponding probe. After touching the tip of the needle (9), push it down further by about 200 μm. By this pushing down, the probe needle (9) is elastically deformed, and the tip thereof surely comes into contact with the inspection pad portion (5b) with a desired elastic force. With the state of FIG. 9 maintained, the TAB semiconductor device (1 ′) is inspected for characteristics.

【0008】ところで、プローブカード(8)で多数の
半導体装置(1')の特性検査を繰り返し行うと、プロー
ブニードル(9)の先端に油や、導電パターン(5)の表
面に形成された金メッキなどのメッキ金属が付着して、
プローブニードル(9)の先端と検査パッド部(5b)の
接触抵抗が変化する。また、特性検査回数が増える程、
プローブニードル(9)のバネ性が劣化して、検査パッ
ド部(5b)との接触圧が弱くなり、検査パッド部(5
b)との接触抵抗が増大する。
By the way, when a large number of semiconductor devices (1 ') are repeatedly inspected with the probe card (8), oil is applied to the tip of the probe needle (9) or gold plating formed on the surface of the conductive pattern (5). Plating metal such as
The contact resistance between the tip of the probe needle (9) and the inspection pad (5b) changes. Also, as the number of characteristic tests increases,
The spring property of the probe needle (9) deteriorates, the contact pressure with the inspection pad (5b) becomes weak, and the inspection pad (5)
The contact resistance with b) increases.

【0009】このような特性検査時のプローブニードル
(9)の先端と検査パッド部(5b)の接触抵抗の変化
は、微少電流で検査される半導体装置(1')の特性検査
結果を不正確なものにする。そこで、従来は図10に示
すような検査プレート(16)でプローブニードル(9)
の先端の汚れ、バネ性の悪化程度を定期的に、或いは、
所定の特性検査回数毎にチェックするようにしている。
The change in the contact resistance between the tip of the probe needle (9) and the inspection pad portion (5b) at the time of the characteristic inspection causes an inaccurate characteristic inspection result of the semiconductor device (1 ') to be inspected with a minute current. Make something Therefore, conventionally, the probe needle (9) is provided by the inspection plate (16) as shown in FIG.
Periodically, the degree of deterioration of the elasticity of the tip of the
The check is performed every predetermined number of characteristic tests.

【0010】図10の検査プレート(16)は、平坦な下
面に金メッキパターン(17)を有する。金メッキパター
ン(17)は、プローブカード(8)のプローブニードル
(9)と対応する数で、プローブニードル(9)の先端と
接触する位置に形成される。
The inspection plate (16) of FIG. 10 has a gold plating pattern (17) on a flat lower surface. The gold plating patterns (17) are formed in positions corresponding to the number of probe needles (9) of the probe card (8) and in contact with the tips of the probe needles (9).

【0011】検査プレート(16)は、図8の押圧プレー
ト(15)と交換して使用される。つまり、押圧プレート
(15)に代わり検査プレート(16)を、プローブカード
(8)の上方に平行に位置決め配置する。この検査プレ
ート(16)を降下させて、図10に示すように、検査プ
レート(16)の金メッキパターン(17)を対応するプロ
ーブニードル(9)の先端に押圧する。図10の状態
で、金メッキパターン(17)と対応するプローブニード
ル(9)の接触抵抗が測定される。
The inspection plate (16) is used by replacing it with the pressing plate (15) shown in FIG. That is, instead of the pressing plate (15), the inspection plate (16) is positioned in parallel above the probe card (8). The inspection plate (16) is lowered and, as shown in FIG. 10, the gold plating pattern (17) of the inspection plate (16) is pressed against the tip of the corresponding probe needle (9). In the state of FIG. 10, the contact resistance of the probe needle (9) corresponding to the gold plating pattern (17) is measured.

【0012】このように測定された金メッキパターン
(17)とプローブニードル(9)の接触抵抗値から、プ
ローブニードル(9)の先端の汚れ程度、バネ性の劣化
程度が推測される。検査プレート(16)で測定された接
触抵抗値が許容レベル範囲内であれば、プローブカード
(8)は再び半導体装置(1')の検査に使用され、許容
レベルを超えているとプローブカード(8)は再使用不
適当と判断されて、新しいものと交換される。
From the contact resistance value between the gold plating pattern (17) and the probe needle (9) thus measured, the degree of contamination of the tip of the probe needle (9) and the degree of deterioration of spring property can be estimated. If the contact resistance value measured by the inspection plate (16) is within the allowable level range, the probe card (8) is used again for the inspection of the semiconductor device (1 ′), and if it exceeds the allowable level, the probe card ( 8) is judged to be inappropriate for reuse and is replaced with a new one.

【0013】[0013]

【発明が解決しようとする課題】ところで、検査プレー
ト(16)でプローブニードル(9)の先端を検査する度
に、半導体装置(1')の特性検査を中断して、プローブ
カード(8)の上方から押圧プレート(15)を外し、代
わりに検査プレート(16)をセットしなければならな
い。しかも、このセットは、検査プレート(16)をプロ
ーブカード(8)と平行になるよう高精度で位置決めし
て行う必要がある。そのため、プローブニードル(9)
の1回の検査に時間を要して作業性が悪く、これが特性
検査設備全体の稼働率を悪くしていた。
By the way, every time the tip of the probe needle (9) is inspected by the inspection plate (16), the characteristic inspection of the semiconductor device (1 ') is interrupted and the probe card (8) is inspected. The pressing plate (15) must be removed from above and the inspection plate (16) must be set instead. Moreover, this set needs to be performed by positioning the inspection plate (16) in parallel with the probe card (8) with high precision. Therefore, the probe needle (9)
It took a long time to perform one inspection, and the workability was poor, which deteriorated the operation rate of the entire characteristic inspection equipment.

【0014】また、検査プレート(16)によるプローブ
ニードル(9)の検査は、作業性が悪いことから定期的
に、或いは、所定の特性検査回数毎に行うしかなった。
そのため、プローブニードル(9)の1回の検査から次
の検査までに、プローブニードル(9)の先端の汚れが
進行して、この間に行われる半導体装置(1')の特性検
査結果が不正確になる場合がある。
Further, the inspection of the probe needle (9) by the inspection plate (16) has to be performed periodically or every predetermined number of characteristic inspections due to poor workability.
Therefore, the contamination of the tip of the probe needle (9) progresses from one inspection of the probe needle (9) to the next inspection, and the characteristic inspection result of the semiconductor device (1 ′) performed during this period is inaccurate. May be.

【0015】また、検査プレート(16)でプローブニー
ドル(9)を検査しても、その結果からプローブニード
ル(9)による半導体装置(1')の検査結果における不
良内容は分析できない。つまり、プローブニードル
(9)で半導体装置(1')を検査した結果、半導体装置
(1')が不良と判定されても、その不良内容がプローブ
ニードル(9)と導電パターン(5)の接触抵抗不良が原
因なのか、半導体ペレット(6)自体の不良が原因なの
か分からない場合がある。このような場合、半導体装置
(1')の特性検査を再度行うようにしているが、時間的
な無駄が多く、結果的に特性検査設備全体の稼働率を悪
くしている。
Further, even if the probe needle (9) is inspected by the inspection plate (16), the content of defects in the inspection result of the semiconductor device (1 ') by the probe needle (9) cannot be analyzed from the result. In other words, as a result of inspecting the semiconductor device (1 ') with the probe needle (9) and determining that the semiconductor device (1') is defective, the content of the defect is the contact between the probe needle (9) and the conductive pattern (5). In some cases, it may not be clear whether the cause is a defective resistance or the defective semiconductor pellet (6) itself. In such a case, the characteristic inspection of the semiconductor device (1 ′) is performed again, but there is much waste of time, and as a result, the operating rate of the entire characteristic inspection equipment is deteriorated.

【0016】また、検査プレート(16)は、半導体装置
(1')の特性検査装置であるプローブカード(8)や押
圧プレート(15)と別の検査専用部材であり、かつ、半
導体装置(1')の特性検査時には使用されない別部材で
あって、その保守管理が面倒である問題もあった。
Further, the inspection plate (16) is a member exclusively for inspection different from the probe card (8) and the pressing plate (15) which are characteristic inspection devices of the semiconductor device (1 '), and the semiconductor device (1). There is also a problem that the maintenance management is troublesome because it is a separate member that is not used during the characteristic inspection of ').

【0017】本発明の目的は、プローブカードで迅速、
正確に特性検査されるTAB式半導体装置とその検査方
法を提供することにある。
The object of the present invention is to quickly use a probe card,
It is an object of the present invention to provide a TAB type semiconductor device which is accurately inspected for characteristics and an inspection method thereof.

【0018】[0018]

【課題を解決するための手段】本発明は、部分的に透孔
を有する絶縁フィルムの片面に複数条の導電パターンを
形成したTABテープの前記透孔内に配置された半導体
ペレットの電極と、対応する前記導電パターンを接続し
たTAB式半導体装置において、絶縁フィルムの導電パ
ターン形成面の透孔周辺部に、前記導電パターンと同質
の検査専用ダミーパターンを追加形成したことにより、
上記目的を達成するものである。
DISCLOSURE OF THE INVENTION The present invention provides an electrode of a semiconductor pellet arranged in the through hole of a TAB tape having a plurality of conductive patterns formed on one surface of an insulating film partially having the through hole, In the TAB type semiconductor device in which the corresponding conductive patterns are connected, by additionally forming an inspection dummy pattern of the same quality as the conductive patterns in the periphery of the through hole of the conductive pattern forming surface of the insulating film,
The above object is achieved.

【0019】また、本発明は、上記TAB式半導体装置
の各導電パターンと検査専用ダミーパターンの各々に、
平坦なプローブカードに同一高さで突設させた複数のプ
ローブニードルの先端を弾圧接触させて、半導体装置の
電気的特性を検査するに際して、前記検査専用ダミーパ
ターンと、これにに弾圧接触させたダミーのプローブニ
ードルとの接触抵抗を必要に応じて検査する検査方法を
提供する。
According to the present invention, each of the conductive patterns and the inspection dummy pattern of the TAB type semiconductor device is provided with
When inspecting the electrical characteristics of the semiconductor device by elastically contacting the tips of a plurality of probe needles projecting at the same height on a flat probe card, the dummy pattern for exclusive use of the inspection was elastically contacted with the dummy pattern. Provided is an inspection method for inspecting the contact resistance with a dummy probe needle as necessary.

【0020】[0020]

【作用】TAB式半導体装置の絶縁フィルムに導電パタ
ーンと共に形成された検査専用ダミーパターンと、これ
に接触するプローブカードのプローブニードルとの接触
抵抗の測定値から、導電パターンとこれに接触するプロ
ーブニードルの接触抵抗が正確に推測でき、この推測か
らTAB式半導体装置の特性検査精度が分かる。また、
ダミーパターンとプローブニードルの接触抵抗測定は、
TAB式半導体装置の特性検査毎に、TAB式半導体装
置の特性検査の1項目として実行できて、毎回のTAB
式半導体装置の特性検査が高精度で行える。
The conductive pattern and the probe needle that comes into contact therewith are determined from the contact resistance between the dummy pattern for inspection formed on the insulating film of the TAB semiconductor device together with the conductive pattern and the probe needle of the probe card that comes into contact with the dummy pattern. The contact resistance can be accurately estimated, and the accuracy of the characteristic inspection of the TAB semiconductor device can be known from this estimation. Also,
To measure the contact resistance between the dummy pattern and the probe needle,
It can be performed as one item of the characteristic inspection of the TAB type semiconductor device every time the characteristic inspection of the TAB type semiconductor device is performed.
Type semiconductor device characteristics inspection can be performed with high accuracy.

【0021】[0021]

【実施例】図1及び図2に示される一実施例のTAB式
半導体装置(1)は、図6のTAB式半導体装置(1')
に適用したもので、図6と同一、または、相当部分には
同一符号を付して説明は省略する。
EXAMPLE A TAB type semiconductor device (1) of one embodiment shown in FIGS. 1 and 2 is a TAB type semiconductor device (1 ′) of FIG.
The same reference numerals are given to the same or corresponding portions as in FIG. 6 and the description thereof will be omitted.

【0022】図1及び図2のTAB式半導体装置(1)
の従来と相違する特徴は、絶縁フィルム(3)に複数条
の導電パターン(5)と共に、導電パターン(5)と同質
の検査専用ダミーパターン(5c)を形成したことのみ
である。ダミーパターン(5c)は、導電パターン(5)
と同様に銅箔をエッチングして、導電パターン(5)と
同材料、同厚で形成される。
The TAB type semiconductor device (1) shown in FIGS. 1 and 2.
2 is different from the conventional one only in that a plurality of conductive patterns (5) and an inspection-use dummy pattern (5c) of the same quality as the conductive pattern (5) are formed on the insulating film (3). The dummy pattern (5c) is a conductive pattern (5)
The copper foil is etched in the same manner as in, and is formed of the same material and the same thickness as the conductive pattern (5).

【0023】ダミーパターン(5c)は、例えば図1に
示すように、絶縁フィルム(3)の矩形の透孔(4)の4
コーナ部分にある計4条の導電パターン(5')に一体に
形成される。このダミーパターン(5c)は、4コーナ
部分の導電パターン(5')の検査パッド部(5b)を横
に延在させたものに相当する。
As shown in FIG. 1, for example, the dummy pattern (5c) has four rectangular through holes (4) in the insulating film (3).
It is formed integrally with a total of four conductive patterns (5 ') in the corner portion. The dummy pattern (5c) corresponds to a pattern in which the inspection pad portion (5b) of the conductive pattern (5 ') at the four corners is laterally extended.

【0024】ダミーパターン(5c)は、図2の鎖線に
示されるように、少なくとも2本の後述する特性検査用
プローブニードル(9')(10)が所定の間隔をもって接
触できるサイズで形成される。例えば、ダミーパターン
(5c)は、導電パターン(5)の隣接する2条の配列ピ
ッチの2倍強の幅で形成される。
As shown by the chain line in FIG. 2, the dummy pattern (5c) is formed in such a size that at least two probe needles (9 ') (10) for characteristic inspection described later can come into contact with each other at a predetermined interval. . For example, the dummy pattern (5c) is formed with a width slightly larger than twice the arrangement pitch of two adjacent conductive patterns (5).

【0025】図3及び図4に上記実施例のTAB式半導
体装置(1)の特性検査をするプローブカード(8)の要
部を示すと、これは図8のプローブカード(8)のプロ
ーブニードル(9)に、次のダミーのプローブニードル
(以下、ダミーニードルと称する)(10)を追加設置し
たものである。ダミーニードル(10)は、他のプローブ
ニードル(9)と同質、同一形状であり、TABテープ
(2)の4つのダミーパターン(5c)と対応する4本が
設置される。
FIGS. 3 and 4 show the essential parts of the probe card (8) for inspecting the characteristics of the TAB type semiconductor device (1) of the above embodiment. This is the probe needle of the probe card (8) of FIG. The following dummy probe needle (hereinafter referred to as dummy needle) (10) is additionally installed in (9). The dummy needles (10) have the same quality and the same shape as the other probe needles (9), and four pieces corresponding to the four dummy patterns (5c) of the TAB tape (2) are installed.

【0026】プローブカード(8)で半導体装置(1)
は、次のように特性検査される。従来同様にして、上下
逆のTAB式半導体装置(1)をプローブカード(8)の
真上から降下させて、TABテープ(2)の導電パター
ン(5)の検査パッド(5b)を、プローブカード(8)
の対応するプローブニードル(9)の上端に押し当て
る。このとき、ダミーニードル(10)の上端を、対応す
るダミーパターン(5c)の片端部に弾圧接触させて、
各1つのダミーパターン(5c)の両端部の所定間隔の
2箇所にダミーニードル(10)と特性検査用プローブニ
ードル(9')を弾圧接触させる。
Semiconductor device (1) with probe card (8)
Is characterized as follows. In the same manner as in the past, the TAB type semiconductor device (1) which is turned upside down is dropped from directly above the probe card (8), and the inspection pad (5b) of the conductive pattern (5) of the TAB tape (2) is attached to the probe card. (8)
Press on the upper end of the corresponding probe needle (9). At this time, the upper end of the dummy needle (10) is elastically contacted with one end of the corresponding dummy pattern (5c),
The dummy needle (10) and the probe needle (9 ′) for characteristic inspection are elastically contacted at two positions at predetermined intervals on both ends of each dummy pattern (5c).

【0027】そして、導電パターン(5)に弾圧接触さ
せたプローブニードル(9)で半導体装置(1)の特性検
査をする前に、各ダミーパターン(5c)と一対のダミ
ーニードル(10)及びプローブニードル(9')間の接触
抵抗を測定する。例えば図5に示すように、ダミーニー
ドル(10)とプローブニードル(9')を特性検査回路
(11)の定電流源(12)と電圧計(13)に接続しておい
て、両者間の電圧値を測定することで、両者間の接触抵
抗が測定される。この測定接触抵抗値から、ダミーパタ
ーン(5c)と一体の導電パターン(5')と、これに弾
圧接触するプローブニードル(9)間の接触抵抗値が、
更に他の導電パターン(5)とプローブニードル(9)の
接触抵抗値がほぼ正確に推定される。
Before inspecting the characteristics of the semiconductor device (1) with the probe needle (9) that is elastically contacted with the conductive pattern (5), each dummy pattern (5c), a pair of dummy needles (10) and the probe Measure the contact resistance between the needles (9 '). For example, as shown in FIG. 5, the dummy needle (10) and the probe needle (9 ') are connected to the constant current source (12) and the voltmeter (13) of the characteristic inspection circuit (11), and they are connected to each other. By measuring the voltage value, the contact resistance between the two is measured. From this measured contact resistance value, the contact resistance value between the conductive pattern (5 ') integrated with the dummy pattern (5c) and the probe needle (9) which is elastically contacted with this,
Further, the contact resistance value between the other conductive pattern (5) and the probe needle (9) can be estimated almost accurately.

【0028】したがって、ダミーパターン(5c)での
測定接触抵抗値が許容範囲にあれば、引き続きプローブ
ニードル(9)で半導体装置(1)の特性検査を行う。ま
た、ダミーパターン(5c)での測定接触抵抗値が許容
範囲を超えていると、プローブニードル(9)が不良に
なっていると判定されて、半導体装置(1)の特性検査
が行われず、プローブカード(8)の交換が行われる。
Therefore, if the measured contact resistance value of the dummy pattern (5c) is within the allowable range, the characteristic inspection of the semiconductor device (1) is continued with the probe needle (9). Further, if the measured contact resistance value of the dummy pattern (5c) exceeds the allowable range, it is determined that the probe needle (9) is defective, and the characteristic inspection of the semiconductor device (1) is not performed. The probe card (8) is replaced.

【0029】上記プローブニードル(9)による半導体
装置(1)の特性検査は、ダミーパターン(5c)での測
定接触抵抗値を補正値として行うことができる。また、
同特性検査で半導体装置(1)の特性が不良と判定され
た場合、その特性検査結果の内容とダミーパターン(5
c)での測定接触抵抗の内容を比べることで、特性不良
の原因がプローブニードル(9)の不良か、半導体ペレ
ット(6)の不良かが分かる。プローブニードル(9)の
不良が原因の場合は、プローブカード(8)を交換して
再検査され、半導体ペレット(6)の不良が原因の場合
は、再検査無しに半導体装置(1)が不良と最終判定さ
れる。
The characteristic inspection of the semiconductor device (1) using the probe needle (9) can be performed by using the measured contact resistance value of the dummy pattern (5c) as a correction value. Also,
If the characteristics of the semiconductor device (1) are determined to be defective in the characteristics inspection, the contents of the characteristics inspection result and the dummy pattern (5
By comparing the contents of the measured contact resistance in c), it is possible to know whether the cause of the characteristic failure is the defect of the probe needle (9) or the defect of the semiconductor pellet (6). If the probe needle (9) is defective, the probe card (8) is replaced and re-inspected. If the semiconductor pellet (6) is defective, the semiconductor device (1) is defective without re-inspection. Is finally determined.

【0030】ダミーパターン(5c)での接触抵抗の測
定は、1つの半導体装置(1)の特性検査項目の1つに
して、毎回行うことも可能である。このようにすること
で、個々の半導体装置(1)の特性検査が時間的ロス無
くして能率的に、しかも、毎回高精度に行えるようにな
る。また、半導体装置(1)の特性検査毎に、プローブ
ニードル(9)のバネ性や上端の汚れ程度がチェックさ
れることになるので、プローブカード(8)の交換時期
が適切に分かるようになる。
The contact resistance of the dummy pattern (5c) can be measured every time as one of the characteristic inspection items of one semiconductor device (1). By doing so, the characteristic inspection of the individual semiconductor devices (1) can be performed efficiently with no time loss, and with high accuracy every time. In addition, the spring property of the probe needle (9) and the degree of dirt on the upper end are checked every time the semiconductor device (1) is inspected, so that it is possible to properly know when to replace the probe card (8). .

【0031】TABテープ(2)におけるダミーパター
ン(5c)は、導電パターン(5)の1箇所だけに設ける
ことも可能であるが、導電パターン(5)が多数の場合
は、その単位本数毎に1つと複数設けることが、各導電
パターン(5)とプローブニードル(9)の接触抵抗の変
動をより正確に推定する上で望ましい。
The dummy pattern (5c) on the TAB tape (2) can be provided only at one location of the conductive pattern (5). However, when the conductive pattern (5) is large in number, the dummy pattern (5c) is provided for each unit number. It is desirable to provide one or more in order to more accurately estimate the variation in the contact resistance between each conductive pattern (5) and the probe needle (9).

【0032】また、図3に示す実施例のように、半導体
ペレット(6)に接続される導電パターン(5')の一部
にダミーパターン(5c)を一体に形成する場合、ダミ
ーパターン(5c)と一体の導電パターン(5')は半導
体ペレット(6)の電源線かグランド線であることが、
半導体ペレット(6)の特性を安定させる上で望まし
い。
When the dummy pattern (5c) is integrally formed on a part of the conductive pattern (5 ') connected to the semiconductor pellet (6) as in the embodiment shown in FIG. 3, the dummy pattern (5c) is formed. ) And the conductive pattern (5 ') integrated with the semiconductor pellet (6) are power lines or ground lines,
It is desirable for stabilizing the characteristics of the semiconductor pellet (6).

【0033】また、ダミーパターン(5c)は、導電パ
ターン(5')に一体に設けたが、導電パターン(5')と
分離独立したパターンであってもよい。この場合、図示
しないが独立したダミーパターンには、2本以上のダミ
ーニードルを接触させて、各ダミーニードル間の接触抵
抗を検査する。
Although the dummy pattern (5c) is provided integrally with the conductive pattern (5 '), the dummy pattern (5c) may be a pattern separate from and independent of the conductive pattern (5'). In this case, although not shown, two or more dummy needles are brought into contact with an independent dummy pattern, and the contact resistance between the dummy needles is inspected.

【0034】[0034]

【発明の効果】本発明によれば、TAB式半導体装置の
絶縁フィルムに導電パターンと共に形成されたダミーパ
ターンと、プローブカードのプローブニードルの接触抵
抗の測定値から、他のプローブニードルと導電パターン
の接触抵抗が良好な範囲にあるか否かが判定され、しか
も、この判定はTAB式半導体装置の特性検査毎に行う
ことが容易であるので、常に高精度なTAB式半導体装
置の特性検査が連続的、能率的に実行できる。
According to the present invention, the dummy pattern formed on the insulating film of the TAB type semiconductor device together with the conductive pattern and the measured contact resistance of the probe needle of the probe card are used to determine the other probe needle and the conductive pattern. It is determined whether or not the contact resistance is within a good range, and this determination can be easily performed for each characteristic inspection of the TAB type semiconductor device. Therefore, highly accurate characteristic inspection of the TAB type semiconductor device is continuously performed. Can be executed efficiently and efficiently.

【0035】また、プローブカードのプローブニードル
の汚れなどによる不良チェックが、検査プレートなど特
別な別部材を使用することなく、TAB式半導体装置の
特性検査回路で簡単、迅速にできるので、特性検査設備
の簡略化、コストダウン、稼動率改善が図れる効果もあ
る。
In addition, a characteristic check circuit of the TAB type semiconductor device can easily and quickly perform a defect check due to stains on the probe needle of the probe card without using a special separate member such as an inspection plate. There is also an effect that simplification, cost reduction, and improvement of operating rate can be achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るTAB式半導体装置の一実施例を
示す部分平面図。
FIG. 1 is a partial plan view showing an embodiment of a TAB type semiconductor device according to the present invention.

【図2】図1A−A線に沿う拡大断面図。FIG. 2 is an enlarged sectional view taken along the line AA of FIG.

【図3】図1半導体装置を本発明の検査方法で特性検査
するときの半導体装置の部分下面図。
FIG. 3 is a partial bottom view of the semiconductor device when the semiconductor device is characteristic-inspected by the inspection method of the present invention.

【図4】図3B−B線に沿う拡大断面図。FIG. 4 is an enlarged cross-sectional view taken along the line BB of FIG.

【図5】図4の特性検査部分の接触抵抗検査回路図。5 is a contact resistance inspection circuit diagram of the characteristic inspection portion of FIG.

【図6】従来のTAB式半導体装置の部分平面図。FIG. 6 is a partial plan view of a conventional TAB semiconductor device.

【図7】図6C−C線に沿う断面図。FIG. 7 is a sectional view taken along the line CC of FIG.

【図8】図6半導体装置の特性測定装置の断面図。FIG. 8 is a cross-sectional view of a semiconductor device characteristic measuring apparatus.

【図9】図8特性測定装置の特性測定時での断面図。FIG. 9 is a cross-sectional view of the characteristic measuring device during characteristic measurement.

【図10】図8特性測定装置におけるプローブニードル
検査装置の断面図。
FIG. 10 is a cross-sectional view of a probe needle inspection device in the characteristic measurement device of FIG.

【符号の説明】[Explanation of symbols]

1 TAB式半導体装置 2 TABテープ 3 絶縁フィルム 4 透孔 5 導電パターン 5' 導電パターン 5c ダミーパターン 6 半導体ペレット 7 電極 8 プローブカード 9 プローブニードル 9' プローブニードル 10 ダミーのプローブニードル 1 TAB semiconductor device 2 TAB tape 3 Insulating film 4 Through hole 5 Conductive pattern 5'Conductive pattern 5c Dummy pattern 6 Semiconductor pellet 7 Electrode 8 Probe card 9 Probe needle 9'Probe needle 10 Dummy probe needle

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 部分的に透孔を有する絶縁フィルムの片
面に複数条の導電パターンを形成したTABテープの前
記透孔内に配置された半導体ペレットの電極と、対応す
る前記導電パターンを接続したTAB式半導体装置にお
いて、 絶縁フィルムの導電パターン形成面の透孔周辺部に、導
電パターンと同質の検査専用ダミーパターンを追加形成
したことを特徴とするTAB式半導体装置。
1. An electrode of a semiconductor pellet arranged in the through hole of a TAB tape in which a plurality of conductive patterns are formed on one surface of an insulating film partially having through holes, and the corresponding conductive pattern is connected. The TAB type semiconductor device is characterized in that a dummy pattern for inspection, which is of the same quality as the conductive pattern, is additionally formed around the through hole on the conductive pattern forming surface of the insulating film.
【請求項2】 請求項1記載のTAB式半導体装置の各
導電パターンと検査専用ダミーパターンの各々に、平坦
なプローブカードに同一高さで突設させた複数のプロー
ブニードルの先端を弾圧接触させて、半導体装置の電気
的特性を検査するに際して、前記検査専用ダミーパター
ンと、これにに弾圧接触させたダミーのプローブニード
ルとの接触抵抗を検査する工程を含むことを特徴とする
TAB式半導体装置の検査方法。
2. The tip of a plurality of probe needles projecting at the same height on a flat probe card is brought into elastic contact with each of the conductive patterns and the inspection dummy pattern of the TAB semiconductor device according to claim 1. In addition, when inspecting the electrical characteristics of the semiconductor device, a TAB type semiconductor device including a step of inspecting the contact resistance between the inspection-dedicated dummy pattern and the dummy probe needle that is elastically contacted with the dummy pattern. Inspection method.
JP26243292A 1992-09-30 1992-09-30 Tab-system semiconductor device and inspection method thereof Pending JPH06120313A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26243292A JPH06120313A (en) 1992-09-30 1992-09-30 Tab-system semiconductor device and inspection method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26243292A JPH06120313A (en) 1992-09-30 1992-09-30 Tab-system semiconductor device and inspection method thereof

Publications (1)

Publication Number Publication Date
JPH06120313A true JPH06120313A (en) 1994-04-28

Family

ID=17375710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26243292A Pending JPH06120313A (en) 1992-09-30 1992-09-30 Tab-system semiconductor device and inspection method thereof

Country Status (1)

Country Link
JP (1) JPH06120313A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6788082B2 (en) 2002-08-23 2004-09-07 Mitsubishi Denki Kabushiki Kaisha Probe card
US7238962B2 (en) 2003-03-13 2007-07-03 Samsung Electronics Co., Ltd. Semiconductor chip with test pads and tape carrier package using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6788082B2 (en) 2002-08-23 2004-09-07 Mitsubishi Denki Kabushiki Kaisha Probe card
US7238962B2 (en) 2003-03-13 2007-07-03 Samsung Electronics Co., Ltd. Semiconductor chip with test pads and tape carrier package using the same

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