JPH0611110B2 - Output buffer circuit - Google Patents

Description

The present invention relates to an output buffer circuit composed of a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOS FET).

[Conventional technology]

FIG. 3 shows a conventional type of complementary metal oxide semiconductor (hereinafter referred to as C
FIG. 4 shows an operation waveform diagram in this case, which is an output buffer circuit diagram used in an integrated circuit (referred to as -MOS).

In FIG. 3, (1) is the first MOS FET of p-channel,
(2) is the n-channel second MOS FET, (3) is the p-channel third MOS FET, and (4) is the n-channel fourth MOS FE.
T, (5) a positive voltage source (hereinafter, referred to as V _DD) terminal, (6) is grounded (hereinafter, referred to as G _ND) terminal, (7) the input terminal (8) is an output terminal.

Here, the substrate of the p-channel MOS FETs (1) and (3) is V _DD
The terminal (5), the substrate of the n channel of the MOS FET (2) and (4) are respectively connected to the G _ND terminal (6), and MOS FET (1)
(2) and MOS FETs (3) and (4) are the first and second C-MO, respectively.
It constitutes an S inverter.

However, the input terminal (7) has a semiconductor integrated circuit (not shown).
An internal signal is applied to the output terminal (8), and the output terminal (8) is wire-bonded to a package for connection to an external input terminal and taken out to the pin (neither is shown).

The conventional output buffer circuit is configured as above, and now
To the input terminal (7) with the potential of the power supply V _DD , for example, (+) 5 V and the potential of the ground G _ND , for example, 0 V, applied to the V _DD terminal (5) and the _GND terminal (6), respectively. When a "H" level potential, for example (+) 5V, is applied, the MOS FET (1) is cut off and the MOS FET (2) is turned on. Therefore, the drains of the MOS FETs (1) and (2) are short-circuited to the _GND terminal (6) through the MOS FET (2), and become the “L” level potential ( _GND potential).

On the contrary, when the input terminal (7) "L" level potential, for example, 0V is applied, the MOS FET (1) is turned on,
MOS SFET (2) is cut off. For this reason, MOS F
The drains of ET (1) and (2) are connected to V _DD pin through MOS FET (1).
It is short-circuited to (5), and becomes "H" level potential (V _DD ).

The "H" level potential of the drain is the second C of the next stage.
-As an input signal to the gate of the MOS inverter,
As ET (3) and (4) operate in the same manner as the above MOS FETs (1) and (2), the output terminal (8) has the output buffer circuit as shown in the waveform diagram of FIG. A signal having the same polarity as that at the input terminal (7) is output after a delay of the delay time.

In FIG. 4, the vertical axis represents voltage, the horizontal axis represents time, and IN
Shows an input signal waveform at the input terminal (7), and OUT shows an output signal waveform at the output terminal (8).

[Problems to be solved by the invention]

The propagation delay time of the C-MOS inverter in the conventional output buffer circuit as described above depends on the output capacitance (not shown; it is mainly formed by the stray capacitance of the circuit, the input capacitance of the gate at the next stage, etc.). It is determined by the charging / discharging time.The charging / discharging time depends on the output capacitance value and the MOS FET (3) or MOS FE.
It is proportional to the product of the on resistance of T (4). Therefore, if the output capacitance is kept constant, the delay time of the second C-MOS inverter is determined by the ON resistance value of the MOS FET (3) or MOS FET (4).

However, the mobility of the p-channel MOS FET (3) (Mobi
lity) is lower than the mobility of n-channel MOS FET (4), the on-resistance of the former is high if the transistor size is the same, and the charging time of the output capacitance of the C-MOS circuit, that is, the rise time of the output voltage is affected by this effect. Therefore, the fall time becomes a steep waveform.

Therefore, in addition to the output capacitance, the output terminal (8) is added with the inductance of the package and the external wiring, and the impedance of the output buffer circuit and the external impedance may not be matched. The output waveform of the undershoot (under shoot, the fourth broken line a
Part) and its ringing, which causes a malfunction of an external device.

Due to the recent progress in microfabrication technology, semiconductor devices have become highly integrated, and the operating speed of the output buffer circuit has also increased as the operating speed of the gate inside the integrated circuit has increased, so the above problems are being increasingly closed up. There is.

The present invention has been made to solve the above problems, and an object thereof is to obtain an output buffer circuit in which the fall operation time of the output buffer circuit does not depend only on the performance of the transistor and can be freely determined. .

[Means for solving problems]

In the output buffer circuit according to the present invention, a first C-MOS inverter and a second C-MOS inverter are connected in series between an input terminal and an output terminal, and an output node of the first C-MOS inverter and a second C-MOS inverter are connected. In which the gate of the p-channel transistor of the C-MOS inverter is connected, a resistive element is provided between the gates of the transistors for the second C-MOS inverter,
An n-channel transistor having a gate connected to the input terminal and a drain connected to the gate of the n-channel transistor is formed by connecting a capacitance between the gate of the channel transistor and the ground terminal, respectively.

[Action]

According to the present invention, the signal transmission between the first and second C-MOS inverters is made straight to the gates of both transistors constituting the second C-MOS inverter when the output signal of the output buffer circuit rises. The second C- when going down
The gate of the p-channel transistor of the MOS inverter is made straight, but the second
The gate of the n-channel transistor of the C-MOS inverter is made to follow the time constant determined by the resistive element R ₁ and the capacitance C ₁ .

Therefore, the falling operation time of the output signal of the output buffer circuit can be freely determined without affecting the rising operation time,
It prevents the ringing of the output waveform undershoot.

〔Example〕

FIG. 1 is an output buffer circuit diagram showing an embodiment of the present invention, and FIG. 2 shows an operation waveform diagram in this case.
The points indicate the input signal waveforms at the respective connection points.

In FIG. 1, (1) to (8) are exactly the same as the above conventional circuit. (9) is the 5th MOS FE of n-channel
T, (10) are resistors, and (11) are capacitors. The MOS FET (9) is a shunt transistor for removing the influence of the resistance (10) and the capacitance (11) when the output signal of the output buffer circuit rises, and the fall time is equal to the value R ₁ of the resistance (10). It will be determined by the time constant of the value C ₁ of the capacity (11).

In the output buffer circuit configured as above,
Now, it is assumed that the input signal to the input terminal (7) rises from the "L" level potential to the "H" level potential.

When the input signal rises to the “H” level potential, the MOSFET (1)
Is cut off, and MOSFETs (2) and (9) are on, so that the points become "L" at almost the same time, and the capacitance (11)
The charge that has been charged to the battery is discharged. In addition,
At this time, since the MOS FET (3) is on and the MOS FET (4) is cut off, the output terminal signal rises to the potential because it is at "H" level.
The path to T (3) is through the MOS FET (2) and (9) ON state.
The FET (3) is turned on and the MOS FET (4) is turned off, which is the same as the conventional one.

Next, consider the case where the input signal falls from the “H” level potential to the “L” level potential.

As the input signal changes, the MOS FET (1) turns on and the MOS FE
T (2) and (9) are in the cut-off state, the point quickly rises to the "H" level, and the MOS FET (3) is in the cut-off state. However, the current of the MOS FET (1) passes through the resistor (10)
Because of chart-up in (11), the rise of point B is delayed from the point. That is, as the point rises to the “H” level
Even if the MOS FET (3) is in the cut-off state, the voltage applied to the gate of the MOS FET (4) is the value R ₁ of the resistor (10) and the capacitance (11).
Rises after changing with a time constant determined by the value C ₁ of
Is gradually turned on, so that the output signal falls more gently than before as shown in the operation waveform diagram of FIG.

〔The invention's effect〕

As described above, according to the present invention, the signal transmission time between the first and second C-MOS inverters when the output signal of the output buffer circuit falls is determined by the inserted resistance R ₁ and capacitance C ₁
Since it can be freely determined by the time constant, the fall time can be relaxed, the under waveform of the operating waveform and its ringing can be eliminated, and the malfunction of the semiconductor integrated circuit and external equipment can be prevented. .

[Brief description of drawings]

FIG. 1 shows an output buffer circuit diagram according to an embodiment of the present invention, FIG. 2 shows its operation waveform diagram, FIG. 3 shows a conventional output buffer circuit diagram, and FIG. 4 shows its operation waveform diagram. Show. In the figure, (1) is the MOS FET (p channel) of FIG.
(2) is the second MOS FET (n channel), (3) is the third M FET
OS FET (p channel), (4) is the fourth MOS FET (n channel), (5) is the positive voltage power supply (V _DD ) terminal, (6) is the ground (G _ND ) terminal, (7 ) Is an input terminal, (8) is an output terminal, (9) is a fifth MOS FET (n channel), (10) is a resistance resistance, (11)
Is the capacity. In each figure, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location H03K 19/0185 19/0948 8941-5J H03K 19/00 101 D

Claims (1)

[Claims] 1. A first C-MOS inverter having a p-channel transistor and an n-channel transistor connected in series between a power supply terminal and a ground terminal and connected to an input terminal, the power supply terminal and ground. It has a p-channel transistor and an n-channel transistor connected in series with the terminal and is connected to the output terminal, and the gate of the p-channel transistor is connected to the output node of the first C-MOS transistor. A second C-MOS inverter, the p-channel and n of the second C-MOS inverter
A resistive element connected between the gates of the channel transistors, n of the second C-MOS inverter, a capacitance connected between the gate of the channel transistors and the ground terminal, n of the second C-MOS inverter. An output buffer circuit comprising an n-channel transistor connected between the gate of a channel transistor and the ground terminal and having its gate connected to the input terminal.