JPS63136823A - Cmos integrated circuit - Google Patents
Cmos integrated circuitInfo
- Publication number
- JPS63136823A JPS63136823A JP61284763A JP28476386A JPS63136823A JP S63136823 A JPS63136823 A JP S63136823A JP 61284763 A JP61284763 A JP 61284763A JP 28476386 A JP28476386 A JP 28476386A JP S63136823 A JPS63136823 A JP S63136823A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- drain
- channel mosfet
- stage
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007257 malfunction Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 4
- 101100081489 Drosophila melanogaster Obp83a gene Proteins 0.000 description 2
- 101150073536 FET3 gene Proteins 0.000 description 2
- 101150015217 FET4 gene Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ＣＭＯＳ−ＩＣ（集積回路〉に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a CMOS-IC (integrated circuit).
従来、ＣＭＯＳ−ＩＣのロジック部の構造は、例えば第
５図のバッファ回路では、直流電源１と並列にＰチャネ
ルＭＯＳ Ｆ ＥＴ ２とＮチャネルＭＯＳＦＥＴ３と
の直列接続体およびＰチャネルＭＯＳＦＥＴ４とＮチャ
ネルＭＯＳＦＥＴ５との直列接続体（接続点を出力端子
６とする）を接続し、ＰチャネルＭＯＳＦＥＴ２とＮチ
ャネルＭＯＳＦＥＴ３との接続点７とＰチャネルＭＯＳ
ＦＥＴ４のゲートとＮチャネルＭＯＳＦＥＴ５のゲート
とを接続するものである。Conventionally, the structure of the logic section of a CMOS-IC is such that, for example, in the buffer circuit shown in FIG. (The connection point is output terminal 6) is connected to the connection point 7 of P-channel MOSFET 2 and N-channel MOSFET 3, and the P-channel MOS
It connects the gate of FET4 and the gate of N-channel MOSFET5.
第５図に示す回路の動作は、ＰチャネルＭＯＳＦＥＴ２
（７）ゲートとＮチャネルＭＯＳＦＥＴ３のゲートとを
接続した入力端子８がロウレベルの時、ＰチャネルＭＯ
ＳＦＥＴ２がオン状態であるため接続点７の電位が直流
電源（電圧値Ｅ）１の正極の電位と等しくなっており、
ＮチャネルＭＯＳＦＥＴ５がオン状態で出力端子６がロ
ウレベルとなっている。The operation of the circuit shown in FIG.
(7) When the input terminal 8, which connects the gate to the gate of the N-channel MOSFET 3, is at low level, the P-channel MOSFET
Since SFET 2 is in the on state, the potential of the connection point 7 is equal to the potential of the positive electrode of the DC power supply (voltage value E) 1,
The N-channel MOSFET 5 is in an on state and the output terminal 6 is at a low level.
次に、入力端子８がハイレベルとなった時（第６図に入
力端子８の電圧■１の波形を示す）、ＰチャネルＭ Ｏ
Ｓ Ｆ Ｅ ’！’ ２がオフとなり、ＮチャネルＭ
ＯＳ Ｆ Ｅ Ｔ３がオンとなるためＰチャネルＭＯＳ
Ｆ Ｅ Ｔ ４のゲーＩ・・ドレイン間およびＮチャ
ネルＭＯＳＦＥＴ５のゲート・ドレイン間とゲート・ソ
ース間に蓄えられていた電荷が接続点７およびＮチャネ
ルＭＯＳＦＥＴ３のドレイン・・ソース間（オン抵抗Ｒ
ＮＯ）を通り放電し、次にＰチャネルＭＯＳＦＥＴ４の
ドレイン・ゲート間とソース・ゲー）・間およびＮチャ
ネルＭＯＳＦＥＴ５のドレイン・ソース間に充電される
ため接続点７の電圧、すなわちＰチャネルＭＯＳＦＥＴ
４とＮチャネルＭＯＳＦＥＴ５のゲート電圧ＶＧの波形
が第６図に示すように変化するため、ＰチャネルＭＯＳ
ＦＥＴ４およびＮチャネルＭＯＳＦＥＴ５のオン抵抗（
第２図参照）の変化により、電源配線に■ＤＤ＝
なる電流が第６図のようにＲＮ ＋ＲＰ
流れるものである（ ＲＮはＮチャネルＭＯＳＦＥＴ５
のオン抵抗、ＲＰはＰチャネルＭＯＳＦＥＴ４のオン抵
抗）。Next, when the input terminal 8 becomes high level (Figure 6 shows the waveform of the voltage ■1 of the input terminal 8), the P channel M O
SFE'! ' 2 is turned off, N channel M
Since OS F E T3 is turned on, P channel MOS
Charges stored between the gate I and drain of FET 4 and between the gate and drain and gate and source of N-channel MOSFET 5 are transferred to the connection point 7 and between the drain and source of N-channel MOSFET 3 (on-resistance R
NO), and then charged between the drain and gate of P-channel MOSFET 4 and between the source and gate of P-channel MOSFET 4, and between the drain and source of N-channel MOSFET 5, so that the voltage at connection point 7, that is, P-channel MOSFET
Since the waveforms of gate voltage VG of 4 and N-channel MOSFET 5 change as shown in FIG.
On-resistance of FET4 and N-channel MOSFET5 (
(See Figure 2) due to changes in the power supply wiring ■DD=
The current RN +RP flows as shown in Figure 6 (RN is the N-channel MOSFET5
RP is the on-resistance of P-channel MOSFET 4).
上述したように従来のＣＭＯＳ−ＩＣは、特に出力段部
分において、出力が無負荷の状態でさえ瞬時的なサージ
電流（例えばｒＤｎピーク値２０ｍＡ、パルス幅１０ｎ
ｓ程度）が流れるため、ＩＣを多数使用する装置あるい
は電源からＩＣまでの配線の長い装置などでは、他のＩ
Ｃをきめて誤動作や電磁波源となるなどの問題があり、
これを防止するための容量の大きなデカップリングコン
デンサやバイパスコンデンサなどが多数必要となるとい
う欠点があった。As mentioned above, conventional CMOS-ICs, especially in the output stage, are subject to instantaneous surge currents (for example, rDn peak value of 20 mA, pulse width of 10 nm) even when the output is under no load.
s), so in devices that use many ICs or devices with long wiring from the power supply to the IC, other
There are problems such as malfunction or becoming a source of electromagnetic waves due to C.
A drawback is that a large number of decoupling capacitors and bypass capacitors with large capacitances are required to prevent this.
本発明のｃＭＯ３−ＩＣは、Ｐチャネル間Ｏ８ＦＥＴか
らなる前段Ｐチャネル回路と、ＮチャネルＭＯＳＦＥＴ
からなる前段Ｎチャネル回路と、この前段Ｎチャネル回
路のＮチャネルドレイン側端子に一端を前記前段Ｐチャ
ネル回路のＰチャネルドレイン側端子に他端が接続され
た抵抗と、ソースが前記前段Ｐチャネル回路のＰチャネ
ルソース側端子にゲートが前記Ｐチャネルドレイン側端
子に接続された後段ＰチャネルＭ ＯＳ Ｆ Ｅ Ｔと
、ソースが前記前段Ｎチャネル回路のＮチャネルソース
側端子にゲートが前記Ｎチャネルドレ、イン側端子にド
レインが前記後段ＰチャネルＭＯＳＦＥＴのドレインに
接続された後段ＮチャネルＭＯ９ＦＥＴとを含んで構成
される。The cMO3-IC of the present invention has a front-stage P-channel circuit consisting of an O8FET between P-channels, and an N-channel MOSFET.
a resistor having one end connected to the N-channel drain terminal of the preceding N-channel circuit and the other end connected to the P-channel drain terminal of the preceding P-channel circuit; and a resistor having a source connected to the preceding P-channel circuit. a rear-stage P-channel MOSFET whose gate is connected to the P-channel source-side terminal of the P-channel drain-side terminal of the former-stage N-channel circuit; The in-side terminal includes a rear-stage N-channel MOSFET whose drain is connected to the drain of the latter-stage P-channel MOSFET.
本発明のＣＭＯＳ−ＩＣは、前段Ｐチャネル回路はドレ
インをＰチャネルドレイン側端子としソースをＰチャネ
ルソース側端子とする１のＰチャネル間Ｏ８ＦＥＴがら
なり、前段Ｎチャネル回路はドレインをＮチャネルドレ
イン側端子としソースをＮチャネルソース側端子とする
１のＮチャネルＭＯＳＦＥＴからなるように構成される
こともできる。In the CMOS-IC of the present invention, the front-stage P-channel circuit consists of one P-channel O8FET with the drain as the P-channel drain side terminal and the source as the P-channel source-side terminal, and the front-stage N-channel circuit has the drain as the N-channel drain side terminal. It is also possible to configure one N-channel MOSFET with a terminal and a source as an N-channel source side terminal.
本発明のＣＭＯＳ−ＩＣは、前段Ｐチャネル回路はそれ
ぞれのドレインを共通接続してＰチャネルドレイン側端
子としそれぞれのソースを共通接続してＰチャネルソー
ス側端子とする並列接続された複数のＰチャネルＭ Ｏ
Ｓ Ｆ Ｅ Ｔからなり、前段Ｎチャネル回路は互いの
ドレインとソースを接続し一端のＮチャネルＭＯＳＦＥ
ＴのドレインをＮチャネル側ドレイン端子とし他端のＮ
チャネルＭＯＳＦＥＴのソースをＮチャネル側ソース端
子とする直列接続された複数のＮチャネルＭＯＳＦＥＴ
からなるように構成されることもできる。The CMOS-IC of the present invention has a plurality of parallel-connected P-channel circuits in which the drains of the preceding stage P-channel circuits are commonly connected to serve as P-channel drain-side terminals, and the respective sources are commonly connected to serve as P-channel source-side terminals. M.O.
The front stage N-channel circuit connects the drain and source of each other and connects the N-channel MOSFE at one end.
The drain of T is the N channel side drain terminal, and the other end of N
Multiple N-channel MOSFETs connected in series with the source of the channel MOSFET serving as the N-channel side source terminal
It can also be configured to consist of
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の回路図で、直流電源１と、
ＰチャネルＭＯＳＦＥＴ２と抵抗９とＮチャネルＭＯＳ
ＦＥＴ３との直列接続体と、ＰチャネルＭＯＳＦＥＴ４
とＮチャネルＭＯＳＦＥＴ５との直列抵抗体（接続点は
出力端子６）とを並列接続し、ＰチャネルＭＯＳ Ｆ
ＥＴ ２のドレイン１０と、ＰチャネルＭＯＳＦＥＴ４
のゲートとを接続し、ＮチャネルＭＯＳＦＥＴ３のドレ
イン１１と、ＮチャネルＭＯＳＦＥＴ５のゲートとを接
続し、ＰチャネルＭＯＳＦＥＴ２のゲートとＮチャネル
Ｍ ＯＳ Ｆ Ｅ ’ｒ’ ３のゲートとを入力端子８
に接続したものである。FIG. 1 is a circuit diagram of an embodiment of the present invention, in which a DC power supply 1,
P channel MOSFET 2, resistor 9 and N channel MOS
Series connection body with FET3 and P channel MOSFET4
and the series resistor of N-channel MOSFET 5 (the connection point is output terminal 6) are connected in parallel, and P-channel MOSFET F
Drain 10 of ET 2 and P-channel MOSFET 4
The drain 11 of the N-channel MOSFET 3 is connected to the gate of the N-channel MOSFET 5, and the gate of the P-channel MOSFET 2 and the gate of the N-channel MOSFET 3 are connected to the input terminal 8.
It is connected to.
本実施例の動作は、入力端子８の電圧Ｖ、がロウしベル
からハイレベルに変わる（第３図参照）と、Ｐチャネル
Ｍ ＯＳ Ｆ Ｅ Ｔ２はオンからオフへ、またＮチャ
ネルＭＯＳＦＥＴ３はオフからオンへ状態が変わるなめ
、ＰチャネルＭＯＳＦＥＴ４のゲーＩ・・ドレイン間に
蓄えられていた電荷が抵抗９とＮチャネルＭＯＳＦＥＴ
３のドレイン・ソース間（オン抵抗ＲＮＯ）を通して放
電され、次にＰチャネルＭ ＯＳ Ｆ Ｅ Ｔ４のソー
ス・ゲート間およびドレイン・ゲート間に抵抗９とＮチ
ャネルＭＯＳＦＥＴ３のドレイン・ソース間を通して電
荷が充電されることにより、ＰチャネルＭＯＳＦＥＴ４
のゲート電圧ＶＧｐは第３図に示す波形のようになり、
またＮチャネルＭＯＳＦＥＴ５のゲート・ドレイン間お
よびゲート・ソース間に蓄えられてぃた電荷がＮチャネ
ルＭＯＳＦＥＴ３のドレイン・ソース間（オン抵抗ＲＮ
Ｏ）を通して放電され、次にＮチャネルＭＯＳ Ｆ Ｅ
Ｔ ５のドレイン・ソース間にＮチャネルＭＯＳＦＥＴ
３のドレイン・ソース間を通して電荷が充電されること
により、ＮチャネルＭＯＳＦＥＴ５のゲート電圧■ＱＮ
は第３図に示す波形のようになる。The operation of this embodiment is such that when the voltage V at the input terminal 8 changes from a low level to a high level (see Figure 3), the P-channel MOSFET2 changes from on to off, and the N-channel MOSFET3 turns off. As the state changes from to on, the charge stored between the gate I and drain of P-channel MOSFET 4 is transferred to resistor 9 and N-channel MOSFET.
The charge is discharged through the drain-source (on-resistance RNO) of P-channel MOSFET 3, and then charged through the resistor 9 between the source-gate and drain-gate of P-channel MOSFET 3 and the drain-source of N-channel MOSFET 3. By doing so, P-channel MOSFET4
The gate voltage VGp has a waveform as shown in Fig. 3,
In addition, the charges accumulated between the gate and drain of N-channel MOSFET 5 and between the gate and source of N-channel MOSFET 5 are transferred between the drain and source of N-channel MOSFET 3 (on-resistance RN
O) and then N-channel MOS F E
N-channel MOSFET between the drain and source of T5
By charging the electric charge between the drain and source of MOSFET 3, the gate voltage of N-channel MOSFET 5 QN
The waveform becomes as shown in FIG.
したがって、ＰチャネルＭＯ９ＦＥＴ４のオン抵抗Ｒ１
，のゲーＩ・電圧特性およびＮチャネルＭＯＳＦＥＴ５
のオン抵抗ＲＮのゲート電圧特性（第２図参照）より、
無負荷時の出力端子６の電圧■ｏは第３図に示す波形と
なり、ＰチャネルＭＯＳＦＥＴ４のソースとＮチャネル
ＭＯＳＦＥＴ５のソースとの間の抵抗値は常に無限大と
なるため、電源配線を流れる電流は（出力段のＣＭＯＳ
部分については）零となる。また、使用上出力端子６に
は、他のＭＯ５ＩＣの入力等が接続される場きが多く、
その場合の出力端子６の電圧■。Therefore, on-resistance R1 of P-channel MO9FET4
, gate I/voltage characteristics and N-channel MOSFET5
From the gate voltage characteristics of the on-resistance RN (see Figure 2),
The voltage o at the output terminal 6 during no-load has the waveform shown in Figure 3, and the resistance value between the source of the P-channel MOSFET 4 and the source of the N-channel MOSFET 5 is always infinite, so the current flowing through the power supply wiring (Output stage CMOS
part) becomes zero. In addition, in use, the output terminal 6 is often connected to the input of other MO5ICs,
In that case, the voltage of output terminal 6 ■.
（Ｃ負荷）は第３図に示す波形とｂる。(C load) has the waveform shown in FIG.
第４図はＡＮＤ （一点鎖線で囲んだ部分を追加すれば
ＮＡＮＤ）回路に本発明を実施した一例で、入力端子８
’、８”を有し、ＰチャネルＭＯＳＦＥＴ２′、２”の
並列接続からなるＰチャネル回路１２と、ＮチャネルＭ
ＯＳＦＥＴ３′。Figure 4 shows an example of the present invention implemented in an AND (NAND if you add the part surrounded by the dashed-dotted line) circuit, where the input terminal 8
', 8'', and a P-channel circuit 12 consisting of parallel connection of P-channel MOSFETs 2', 2'', and an N-channel MOSFET 12,
OSFET3'.
３″の直列接続からなるＮチャネル回路１３との間に抵
抗９を接続するもので、入力端子８′がＰチャオ、ルＭ
ＯＳＦＥＴ２’およびＮチャネルＭＯＳＦＥＴ３’のゲ
ートに接続され入力端子８″がＰチャネルＭ ＯＳ Ｆ
Ｅ Ｔ ２ ”およびＮチャネルＭＱ Ｓ Ｆ Ｅ
Ｔ ３ ”のゲートに接続され、ＰチャネルＭＯＳＦＥ
Ｔ２’ 、２”のドレインがＰチャネルＭＯＳＦＥＴ４
のゲートに接続され、ＮチャネルＭＯＳＦＥＴ３′のド
レインがＮチャネルＭＯＳＦＥＴ５のゲートに接続され
る。A resistor 9 is connected between the N-channel circuit 13 consisting of a series connection of 3", and the input terminal 8' is
The input terminal 8'' is connected to the gates of OSFET2' and N-channel MOSFET3'.
E T 2 ” and N-channel MQ S F E
T 3 ” is connected to the gate of P-channel MOSFE.
T2', 2'' drain is P channel MOSFET4
The drain of N-channel MOSFET 3' is connected to the gate of N-channel MOSFET 5.
第４図においてＮＡＮＤ回路を構成する場合は、Ｐチャ
ネルＭ ＯＳ Ｆ Ｅ Ｔ ２ ’、抵抗９′およびＮ
チャネルＭ ＯＳ Ｆ Ｅ Ｔ ３ ’の直列接続体１
４が加えられ、ＰチャネルＭＯ８ＦＥＴと抵抗とＮチャ
ネルＭＯＳＦＥＴの直列接続が２段設けられ、Ｐチャネ
ルＭＯ８ＦＥＴ２′のドレインおよびＮチャネルＭＯＳ
ＦＥＴ３’のドレインそれぞれがＰチャネルＭ ＯＳ
Ｆ Ｅ Ｔ ２ ”のゲートおよびＮチャネルＭ ＯＳ
Ｆ Ｅ Ｔ ３ ″のゲートそれぞれに接続され、Ｐ
チャネルＭ ＯＳ Ｆ Ｅ Ｔ ２ ”’のドレインお
よびＮチャネルＭ ＯＳ Ｆ Ｅ Ｔ ３ ’のドレイ
ンそれぞれがＰチャネルＭＯＳＦＥＴ４のゲートおよび
ＮチャネルＭＯＳＦＥＴ５のゲートそれぞれに接続され
る。When configuring a NAND circuit in FIG. 4, P channel MOSFET 2', resistor 9' and N
Series connection 1 of channels M OS F E T 3'
4 is added, two stages of series connection of a P-channel MO8FET, a resistor, and an N-channel MOSFET are provided, and the drain of the P-channel MO8FET2' and the N-channel MOSFET are connected in series.
Each drain of FET3' is P channel MOS
FET2” gate and N-channel MOS
connected to each gate of F E T 3 ″, P
The drain of the channel MOSFET 2'' and the drain of the N-channel MOSFET 3' are respectively connected to the gate of the P-channel MOSFET4 and the gate of the N-channel MOSFET5.
以上説明したように本発明は、出力段のＣＭＯ８部に流
れる不要な電流をなくすことにより、他のＩＣを含めて
の誤動作や電磁波源となるなどの問題を低減することが
できるため、従来使用していたデカップリングコンデン
サやバイパスコンデンサの容量を小さくしたり、数量を
低減でき、装置の小形軽量化が図れる等の効果がある。As explained above, the present invention eliminates unnecessary current flowing through the CMO8 section of the output stage, thereby reducing problems such as malfunctions including other ICs and becoming a source of electromagnetic waves. This has the effect of reducing the capacitance and quantity of decoupling capacitors and bypass capacitors, which were previously used, and making the device smaller and lighter.
第１図は本発明の一実施例の回路図、第２図はＮチャネ
ルＭＯＳＦＥＴおよびＰチャネルＭＯ８ＦＥＴのオン抵
抗〜ゲート電圧特性を示すグラフ、第３図は第１図に示
す実施例の各部の電圧波形を示す波形図、第４図は本発
明の他の実施例の回路図、第５図および第６図はそれぞ
れ従来の０ＭＯ８・ＩＣの回路図および波形図である。
■・・・直流電源、２．２’ 、２” 、２”’、４・
・・ＰチャネルＭＯＳ Ｆ ＥＴ、３．３′、３” 、
３”’ 。
５・・・ＮチャネルＭＯＳＦＥＴ、６・・・出力端子、
７・・・接続点、８．８’、８”・・・入力端子、９，
９′・・・抵抗、１０．１１・・・ドレイン端子、１２
・・・Ｐチャネル回路、１３・・・Ｎチャネル回路、１
４・・・ＰチャネルＭＯＳＦＥＴと抵抗とＮチャネルＭ
ＯＳＦＥＴとの直列接続体。FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a graph showing the on-resistance to gate voltage characteristics of an N-channel MOSFET and a P-channel MO8FET, and FIG. 3 is a diagram showing each part of the embodiment shown in FIG. FIG. 4 is a waveform diagram showing voltage waveforms, FIG. 4 is a circuit diagram of another embodiment of the present invention, and FIGS. 5 and 6 are a circuit diagram and waveform diagram of a conventional 0MO8 IC, respectively. ■・・・DC power supply, 2.2', 2", 2"', 4.
...P channel MOS FET, 3.3', 3",
3"'. 5...N channel MOSFET, 6... Output terminal,
7... Connection point, 8.8', 8"... Input terminal, 9,
9'...Resistor, 10.11...Drain terminal, 12
...P channel circuit, 13...N channel circuit, 1
4...P-channel MOSFET, resistor, and N-channel M
Series connection body with OSFET.
Claims (3)
回路と、ＮチャネルＭＯＳＦＥＴからなる前段Ｎチャネ
ル回路と、この前段Ｎチャネル回路のＮチャネルドレイ
ン側端子に一端を前記前段Ｐチャネル回路のＰチャネル
ドレイン側端子に他端が接続された抵抗と、ソースが前
記前段Ｐチャネル回路のＰチャネルソース側端子にゲー
トが前記Ｐチャネルドレイン側端子に接続された後段Ｐ
チャネルＭＯＳＦＥＴと、ソースが前記前段Ｎチャネル
回路のＮチャネルソース側端子にゲートが前記Ｎチャネ
ルドレイン側端子にドレインが前記後段ＰチャネルＭＯ
ＳＦＥＴのドレインに接続された後段ＮチャネルＭＯＳ
ＦＥＴとを含むことを特徴とするＣＭＯＳ集積回路。(1) A pre-stage P-channel circuit consisting of a P-channel MOSFET, a pre-stage N-channel circuit consisting of an N-channel MOSFET, and one end connected to the N-channel drain side terminal of the pre-stage P-channel circuit; a resistor whose other end is connected to the P-channel circuit, and a rear-stage P whose source is connected to the P-channel source terminal of the preceding stage P-channel circuit and whose gate is connected to the P-channel drain terminal of the preceding stage P-channel circuit.
channel MOSFET, the source of which is connected to the N-channel source terminal of the preceding N-channel circuit, the gate of which is connected to the N-channel drain terminal of the N-channel MOSFET, and the drain of which is connected to the subsequent P-channel MOSFET.
Post-stage N-channel MOS connected to the drain of SFET
A CMOS integrated circuit characterized by including a FET.
イン側端子としソースをＰチャネルソース側端子とする
１のＰチャネルＭＯＳＦＥＴからなり、前段Ｎチャネル
回路はドレインをＮチャネルドレイン側端子としソース
をＮチャネルソース側端子とする１のＮチャネルＭＯＳ
ＦＥＴからなる特許請求の範囲第１項記載のＣＭＯＳ集
積回路。(2) The front-stage P-channel circuit consists of one P-channel MOSFET whose drain is the P-channel drain side terminal and the source is the P-channel source-side terminal, and the front-stage N-channel circuit has the drain as the N-channel drain side terminal and the source is the N-channel MOSFET. 1 N-channel MOS as source side terminal
A CMOS integrated circuit according to claim 1, comprising a FET.
接続してＰチャネルドレイン側端子としそれぞれのソー
スを共通接続してＰチャネルソース側端子とする並列接
続された複数のＰチャネルＭＯＳＦＥＴからなり、前段
Ｎチャネル回路は互いのドレインとソースを接続し一端
のＮチャネルＭＯＳＦＥＴのドレインをＮチャネル側ド
レイン端子とし他端のＮチャネルＭＯＳＦＥＴのソース
をＮチャネル側ソース端子とする直列接続された複数の
ＮチャネルＭＯＳＦＥＴからなる特許請求の範囲第１項
記載のＣＭＯＳ集積回路。(3) The front-stage P-channel circuit consists of a plurality of parallel-connected P-channel MOSFETs whose respective drains are commonly connected to serve as P-channel drain-side terminals, and whose respective sources are commonly connected to serve as P-channel source-side terminals. An N-channel circuit has a plurality of N-channels connected in series, with their drains and sources connected to each other, with the drain of the N-channel MOSFET at one end serving as the N-channel side drain terminal, and the source of the N-channel MOSFET at the other end serving as the N-channel side source terminal. A CMOS integrated circuit according to claim 1, comprising a MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61284763A JPS63136823A (en) | 1986-11-28 | 1986-11-28 | Cmos integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61284763A JPS63136823A (en) | 1986-11-28 | 1986-11-28 | Cmos integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63136823A true JPS63136823A (en) | 1988-06-09 |
Family
ID=17682694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61284763A Pending JPS63136823A (en) | 1986-11-28 | 1986-11-28 | Cmos integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63136823A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0221721A (en) * | 1988-07-11 | 1990-01-24 | Toshiba Corp | Output buffer circuit |
| JPH03230616A (en) * | 1990-02-05 | 1991-10-14 | Fujitsu Ltd | Cmos output circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010920A (en) * | 1983-06-30 | 1985-01-21 | Mitsubishi Electric Corp | Complementary semiconductor integrated circuit |
| JPS62254520A (en) * | 1986-04-28 | 1987-11-06 | Mitsubishi Electric Corp | Complementary mos integrated circuit |
-
1986
- 1986-11-28 JP JP61284763A patent/JPS63136823A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010920A (en) * | 1983-06-30 | 1985-01-21 | Mitsubishi Electric Corp | Complementary semiconductor integrated circuit |
| JPS62254520A (en) * | 1986-04-28 | 1987-11-06 | Mitsubishi Electric Corp | Complementary mos integrated circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0221721A (en) * | 1988-07-11 | 1990-01-24 | Toshiba Corp | Output buffer circuit |
| JPH03230616A (en) * | 1990-02-05 | 1991-10-14 | Fujitsu Ltd | Cmos output circuit |
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