JPS6010920A - Complementary semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the through-current of a complementary semiconductor logical circuit by giving a signal having respectively timewise differences to a gate comprising a P-channel MOSFET and an N-channel MOSFET from an inverse amplifier of the pre-stage. CONSTITUTION:When a voltage applied to an input terminal 4 of the inverse amplifier 16 of the pre-stage starts changing from an L level to an H level, the through-current flows through a load resistor 12 between the P-channel MOSFET 8 and the N-channel MOSFET10 and a potential difference is produced between both terminals 9, 11 of the resistor. The difference between the time until a voltage at the 2nd connecting point 11 makes the N-channel MOSFET14 nonconductive and the time until a voltage at the 1st connecting point 9 makes the P-channel MOSFET13 conductive is decreased less than the case without using any load resistor by forming a gate signal of the next stage from both the terminals 9, 11 of the load resistor 12, thereby decreasing the through-current flowing to the MOSFETs 13 and 14.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a P-channel MO8FET and an N-channel MO8FET.
The present invention relates to a complementary semiconductor integrated circuit that can reduce the through current in any complementary semiconductor logic circuit composed of O8FETs.

[Prior art]

FIG. 1 is a circuit diagram showing a conventional complementary semiconductor integrated circuit, and shows, as an example, a complementary semiconductor logic circuit (1) comprising an inverting amplifier. In the figure, (2) is a first power supply terminal to which, for example, a positive voltage Ve (B volts) is applied, (3) is a second power supply terminal to which, for example, 0 volts is applied, and (4) is a complementary semiconductor logic circuit. (1) is the input terminal, (5) is the output terminal of this complementary semiconductor logic circuit (1), (6) has its source connected to the first power supply terminal (2), and its gate connected to the input terminal (
P-channel MO8FET (7) has its source connected to the second power supply terminal (3), its gate connected to the input terminal (4), and its drain connected to the output terminal (5). is an N-channel Mo8rET connected to the output terminal (5). In addition, Fig. 2 (a) and Fig. 2
Figure (b) qualitatively shows the waveform of the input signal and the waveform of the output signal, respectively.

Next, the operation of the complementary semiconductor integrated circuit having the above configuration will be explained with reference to FIG. 2 (al) and FIG. 2 (b). First, the input terminal (4) shown in FIG. Assuming that a voltage waveform is input and the voltage waveform shown in FIG. 2(b) is output from the output terminal (5), points A and D in the voltage waveform shown in FIG.
Since this corresponds to the threshold voltage of (7), N-channel Mo at point A
Point D is the point at which the 8rET (7) begins to conduct, and the point D is the point at which the N-channel Mo8rET (7) becomes non-conductive. In addition, since point B and point 0 in the voltage waveform shown in FIG. 2(a) correspond to the threshold voltage of the P-channel Mo8rET (6), point B is the point at which the P-channel Mo8rET (6) becomes non-conductive. , 0 point is the point at which the P-channel Mo8rET (6) begins to conduct. therefore.

When the input waveform applied to the input terminal (4) changes as shown in FIG.
In the time T from point to point D, P channel Mo5rE
Since both T(6) and N-channel Mo8rET(7) become conductive, the through current flows to the first power supply terminal (2)-
Pf Janel M08FET (6) -Nf'r*LEMO8
FET (7) - Flows toward the second power supply terminal (3). Moreover, although the load connected to the output terminal (5) is not shown, when this load is taken into consideration, the load current is further added.

However, in conventional complementary semiconductor integrated circuits, it is impossible to avoid the flow of through current as described above, and when this through current increases, the operating current of the entire integrated circuit increases, and the instantaneous current increases. had drawbacks such as being a source of noise signals.

[Summary of the invention]

Therefore, an object of the present invention is to utilize the through current flowing through the load resistor of the pre-stage inverting amplifier, and to use the time difference in the voltages generated across the load and resistor to generate a The present invention provides a complementary semiconductor integrated circuit in which the through current of a complementary semiconductor logic circuit is reduced by applying signals with different time differences to the gates of a channel Mo8rET and an N-channel MO8F'ET.

To achieve such an object, the invention provides a method in which the source is connected to the first power supply terminal, the gate is connected to the input terminal, and
P-channel Mo8r whose drain is connected to the first connection point
ET, an N-channel Mo8rET whose source is connected to the second power supply terminal, whose gate is connected to the input terminal, and whose drain is connected to the second connection point, and whose one end is connected to the first connection point and the other end is connected to the first connection point. and a load resistor connected to two connection points, the first connection point being connected to the gate of the P-channel Mo8rET of the complementary semiconductor logic circuit, and the second connection point being connected to the complementary semiconductor logic circuit. N of logic circuit
It is connected to the gate of the channel Mo8rET, and will be explained in detail below using an embodiment.

[Embodiments of the invention]

FIG. 3 is a circuit diagram showing an embodiment of a complementary semiconductor integrated circuit according to the present invention. In the same figure, the source of (8) is connected to the @1 power supply terminal (2), and the gate is connected to the input terminal (2).
4), the drain is connected to the first connection point (9), the P-channel Mo8rET, Qt) has its source connected to the second power supply terminal (3), and its gate connected to the input terminal (4), A 9N channel MO8FET whose drain is connected to the second connection point αυ, (13) a load resistor whose one end is connected to the first connection point (9) and the other end connected to the second connection point αυ, and a3 whose source is connected to the second connection point αυ. A 7cP channel MOS FET, (+
41 has a source connected to the second power supply terminal (3), a gate connected to the second connection point Ql), and a drain connected to the output terminal (
5) is an N-channel Mo8rET connected to

The P-channel MO8FETQ:1 and the N-channel Mo8rET (14) constitute a complementary semiconductor logic circuit a9 consisting of an inverting amplifier. Also, the P Chi? Channel MO8FET (8) I N Qi? #MO8FE
A pre-stage inverting amplifier αe of the complementary semiconductor logic circuit a4 is constructed from TQl and a load resistance a. Moreover, FIGS. 4(a) to 4(c) qualitatively show the waveforms of each part in FIG. 3.

Next, the operation of the complementary semiconductor integrated circuit having the above configuration will be explained with reference to FIGS. 4(a) to 4(C).
Using positive logic, the logically positive state is 1H',
Logically, the non-pressure state is expressed as 1L'. First, the voltage of the input signal applied to the input terminal (4) is shown in Fig. 4(a).
As shown in , when the steady state is at 1L', the first connection point (
9) and the state of the second connection point αυ is H'. Therefore, the output terminal (5) becomes 1L level. Next, when the voltage applied to the input terminal (4) begins to change from 1L level to 1H level, a through current flows between the P-channel Mo8rET (8) and the N-channel MO8FES (11) through the load resistance a. . As a result, a potential difference occurs between both ends of the load resistor Q2, and as shown in FIG. 4(b), the waveform L2 at the first connection point (9) and the waveform L2 at the second connection point (1) is obtained. In the waveform of this first connection point (9), the upper point E is a point corresponding to the threshold voltage of P channel Mo8rET (13), and the waveform of the second connection point aυ is,
The upper point F corresponds to the threshold voltage of the N-channel Mo8rETQ4). By creating a gate signal for the next stage from both ends of the load resistor (11J), the time required for the voltage at the second connection point αD to reach point F, which makes the N-channel Mo8rET (14) non-conductive, and the second connection point aυ
The difference in time required for the voltage of
Channel Mo5rET (+3.!=NchiyJruMo5
The through current flowing through pETQ4)K can be reduced.

Next, the voltage of the input signal applied to the input terminal (4) is 1
When it starts to change from H level to L level.

P-channel Mo8rET (8) and N-channel Mo8rE
A through current flows through the load resistor (one of the load resistors) during T←.

As a result, a potential difference is generated between both ends of the load resistance a, and the waveforms shown in FIG. can get.

And, the waveform of this first connection point (9), the upper point G is P
This is the point corresponding to the threshold voltage of Teyarne MO8FETQ3, the waveform of the second connection point 0υ, and the upper point E is the N channel M
This point corresponds to the threshold voltage of o8rETQ4).

Then, similarly to the case where the input signal voltage changes from 1L level to 1H level, the voltage at the first connection point (9) reaches point G, which makes the P-channel MO8FE'l'α level non-conductive. The difference between the time and the time required for the voltage at the second connection point a0 to reach the H point that makes the N-channel Mo8rET (14) conductive can be made smaller than when no load resistance is used. Hello, P channel MO
The through current flowing through the 8FET α rise and the N-channel Mo8rET (14) can be reduced. Therefore, in contrast to the input voltage waveform input to the input terminal (4) shown in FIG. 4(a), the output voltage waveform shown in FIG. 4(c) is obtained at the output terminal (5).

Note that although a load resistor is used in the above description, it goes without saying that a semiconductor element may also be used.

Further, although an inverter is used as the complementary semiconductor logic circuit, it is needless to say that the present invention is not limited to this and other logic circuits may be used. Also 1M08FET03) and MO
The through current flowing through the SFET (14) depends on the rise and fall times of the input waveform, the shape of each MO8FET, the gate capacitance9 distributed capacitance, the size of the load resistance, etc., so it is important to reduce the through current of any logic circuit. Of course, in order to do so, the design may include the preceding stages.

〔Effect of the invention〕

As explained in detail above, the complementary semiconductor integrated circuit according to the present invention can reduce the flowing through current, thereby reducing the operating current and reducing the generation of noise signals. There is.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional complementary semiconductor integrated circuit, Figure 2 (a) and Figure 2 (b) are diagrams showing the input voltage waveform and output voltage waveform of Figure 1, respectively, and Figure 3 is a diagram showing the input voltage waveform and output voltage waveform of Figure 1, respectively. FIGS. 4(a) to 4(c) are circuit diagrams showing one embodiment of the complementary semiconductor integrated circuit according to the invention of . (1)... Complementary semiconductor logic circuit, (2)...
First power terminal, (3)...Second power terminal, (4)...
...Input terminal, (5)...Output terminal, (6)...
...P channel MO8FET, (7)...N channel MO8FET, (8)-' --P channel MO8F
E.T. (9)...First connection point, GO)...N-channel MO8FET, αυ...Second connection point, (121...
...Load resistance, α (to)...P channel MO8FE
T, (14)...N channel MO8FET1α9・
... Complementary semiconductor logic circuit, (1G) ... Front stage inverting amplifier. In addition, in FIG. 9, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 1 Figure 2 Figure Otsu 44 - - 1 - Mr. Commissioner of the Japan Patent Office 1. Indication of case: Japanese Patent Application No. 58-120807 2. Title of invention: Complementary semiconductor integrated circuit. Circuit 3, person performing correction Figure 1

Claims (1)

[Claims] A P-channel MO8FET whose source is connected to a first power supply terminal and whose drain is connected to an output terminal;
A complementary semiconductor integrated circuit consisting of an arbitrary complementary semiconductor logic circuit configured in K and an N-channel MO8FET connected to a power supply terminal and whose drain is connected to an output terminal, the source of which is connected to the first power supply terminal, A P-channel MO8FET whose gate is connected to the input terminal, whose drain is connected to the first connection point, and whose source is connected to the second power supply terminal, whose gate is connected to the input terminal, and whose drain is connected to the second connection point. N-channel MO8FET with one end connected to the first
a pre-stage inverting amplifier consisting of a load resistor connected to a connection point and a load resistor having the other end connected to a second connection point, the first connection point being a P-channel MO8FET of the complementary semiconductor logic circuit;
connected to the gate. A complementary semiconductor integrated circuit, wherein the second connection point is connected to a gate of an N-channel MO8FET of the complementary semiconductor logic circuit.