JPH0610547Y2 - ジツタ吸収回路 - Google Patents

ジツタ吸収回路

Info

Publication number
JPH0610547Y2
JPH0610547Y2 JP1984179551U JP17955184U JPH0610547Y2 JP H0610547 Y2 JPH0610547 Y2 JP H0610547Y2 JP 1984179551 U JP1984179551 U JP 1984179551U JP 17955184 U JP17955184 U JP 17955184U JP H0610547 Y2 JPH0610547 Y2 JP H0610547Y2
Authority
JP
Japan
Prior art keywords
signal
circuit
clock
reproduction
variable delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1984179551U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6193862U (enrdf_load_html_response
Inventor
祀夫 富沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Priority to JP1984179551U priority Critical patent/JPH0610547Y2/ja
Priority to EP85109546A priority patent/EP0171022A3/en
Priority to EP90108905A priority patent/EP0395118A1/en
Priority to EP90108904A priority patent/EP0390226A1/en
Publication of JPS6193862U publication Critical patent/JPS6193862U/ja
Priority to US07/289,479 priority patent/US5012141A/en
Priority to US07/448,160 priority patent/US4956720A/en
Priority to US07/448,056 priority patent/US5039893A/en
Application granted granted Critical
Publication of JPH0610547Y2 publication Critical patent/JPH0610547Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Optical Recording Or Reproduction (AREA)
  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP1984179551U 1984-07-31 1984-11-26 ジツタ吸収回路 Expired - Lifetime JPH0610547Y2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP1984179551U JPH0610547Y2 (ja) 1984-11-26 1984-11-26 ジツタ吸収回路
EP90108905A EP0395118A1 (en) 1984-07-31 1985-07-30 Analog signal delay circuit
EP90108904A EP0390226A1 (en) 1984-07-31 1985-07-30 Jitter absorption circuit
EP85109546A EP0171022A3 (en) 1984-07-31 1985-07-30 Signal delay device
US07/289,479 US5012141A (en) 1984-07-31 1988-12-21 Signal delay device using CMOS supply voltage control
US07/448,160 US4956720A (en) 1984-07-31 1989-12-08 Jitter control circuit having signal delay device using CMOS supply voltage control
US07/448,056 US5039893A (en) 1984-07-31 1989-12-08 Signal delay device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984179551U JPH0610547Y2 (ja) 1984-11-26 1984-11-26 ジツタ吸収回路

Publications (2)

Publication Number Publication Date
JPS6193862U JPS6193862U (enrdf_load_html_response) 1986-06-17
JPH0610547Y2 true JPH0610547Y2 (ja) 1994-03-16

Family

ID=30737118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984179551U Expired - Lifetime JPH0610547Y2 (ja) 1984-07-31 1984-11-26 ジツタ吸収回路

Country Status (1)

Country Link
JP (1) JPH0610547Y2 (enrdf_load_html_response)

Also Published As

Publication number Publication date
JPS6193862U (enrdf_load_html_response) 1986-06-17

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