JPH06104950A - Selection circuit - Google Patents

Abstract

PURPOSE:To output data from a head of a cell to a line selected when either of two lines to which data (cell) having a significance in the unit of several bytes is inputted. CONSTITUTION:An input selection circuit 11 decides which of input data 1, 2 is to be selected by the input of a selection signal 5. The number of selected input data is counted by a counter circuit 12. A line selection circuit 13 selects the input data based on an output signal from the counter circuit 12. Thus, when cell data are inputted to each input line, the output data are outputted from th head of the one cell in spite of a time when the selection signal is switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a selection circuit, and more particularly, to input data having meaningful data in units of several bytes (hereinafter, referred to as
The present invention relates to a selection circuit that performs switching in units of cells.

[0002]

2. Description of the Related Art A conventional selection circuit, as shown in FIG. 2, has a selection signal 22 and input data 20 and 21 of two or more input lines.
And the output data 23 of the output 1 line, the selection signal 2
The input line selected by 2 is switched to output to the output line.

[0003]

In this conventional selection circuit, since the selected input circuit is switched at the moment the selection signal is switched and is output to the output line, the input data is meaningful data in units of several bytes. However, the selection signal is switched without being synchronized with the unit of several bytes of the input data, and there is a problem that the meaningless data is likely to be output as the output data.

It is an object of the present invention to provide a selection circuit that outputs data from the beginning of a cell regardless of which line is selected.

[0005]

To achieve the above object, a selection circuit according to the present invention comprises an input selection circuit, a counter circuit and a line selection circuit, and several bytes input from two or more lines. A selection circuit that switches and outputs meaningful input data in units, the input selection circuit selects an input synchronization signal indicating the beginning of input data of a plurality of lines by a selection signal, and the counter circuit selects The length of the input data is counted from the input synchronization signal thus generated, and the line selection circuit switches a plurality of lines according to the count end signal from the counter circuit.

[0006]

The input selection circuit 11 determines whether the input data 1 or 2 is selected by the input of the selection signal 5. The counter circuit 12 counts the selected number of input data. The line selection circuit 13 switches the input data according to the output signal of the counter circuit 12.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, the present invention has two or more lines for inputting meaningful data in units of a few bytes, and has an input clock 8, a selection signal 5, and input data for each input line. 1, 2, input sync signals 3 and 4 indicating the beginning of cells, input permission signals 6 and 7, and output data 9
And an output synchronization signal 10 indicating the beginning of the cell.

Further, according to the present invention, an input selection circuit 11 for selecting an input synchronization signal indicating the heads of cells on a plurality of lines by a selection signal, and a counter circuit 12 for counting the cell length from the selected input synchronization signal, And a line selection circuit 13 for switching input data.

8 bit parallel input data 1, 8b in which the input data has a meaning in a unit of n bytes (hereinafter referred to as a cell)
It Selects which of the input data 1 and the input data 2 is to be selected by the input selection circuit 11 by the input synchronization signal 3, the input synchronization signal 4 and the selection signal 5 which indicate the beginning of the input data of each line of the parallel input data 2. decide.

On the other hand, the input permission signal 6 or the input permission signal 7 is output to the line whose input is selected. The transmission side of the line data receives the input permission signal and stops the data transmission. Also, at this time, until the input data of the line selected to be input is input for one cell (n bytes), the input synchronization signal 3,
Counter circuit 12 so as not to accept input synchronization signal 4
The input synchronization signal selection signal 14 and the input synchronization signal selection signal 15 are gated by the 1-cell counting in-operation signal 17.

The counter circuit 12 is activated by the input synchronization signal selection signal 14 or the input synchronization signal selection signal 15 output from the input selection circuit 11, and the clock 8 counts up to n. The output synchronizing signal 10 is output at the timing of starting counting, and the line selection signal 16 is output. In accordance with the line selection signal 16 output from the counter circuit 12, the line selection circuit 13 selects either the input data 1 or the input data 2 and outputs it as the output data 9.
This output data 9 is output from the beginning of the cell in synchronization with the output synchronization signal 10.

When the data output for one cell is completed, the input selection circuit 11 accepts the input synchronization signal 3 and the input synchronization signal 4, and the same control as above is performed.

[0014]

As described above, according to the present invention, when the input data has two or more input data lines having meaningful data in units of several bytes, which line is selected by the selection signal regardless of when the selection signal is switched. However, there is an effect that the output data can be output from the beginning of the cell of the input data.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional selection circuit.

[Explanation of symbols]

 1 Input data 2 Input data 3 Input synchronization signal 4 Input synchronization signal 5 Selection signal 6 Input permission signal 7 Input permission signal 8 Input clock 9 Output data 10 Output synchronization signal 11 Input selection circuit 12 Counter circuit 13 Line selection circuit 14 Input synchronization signal Selection signal 15 Input synchronization signal selection signal 16 Line selection signal 17 1 Cell counting operation signal

Claims (1)

[Claims] 1. A selection circuit which has an input selection circuit, a counter circuit, and a line selection circuit and which switches and outputs meaningful input data input from two or more lines in units of several bytes. The selection circuit selects the input sync signal indicating the beginning of the input data of multiple lines by the selection signal, and the counter circuit counts the length of the input data from the selected input sync signal. The selection circuit is characterized in that a plurality of lines are switched by a count end signal from the counter circuit.