JPH0568048A - Optical fifo memory - Google Patents

Abstract

PURPOSE:To output packets while keeping an interval between adjacent packets to be apart by T or larger at all times. CONSTITUTION:The memory is provided with an output optical signal line 9 through which an optical packet signal string is outputted so that no optical packet or one optical packet is in existence for each time interval T(T>t), g-stages of 1Xm optical switches 11, 1/2 frequency dividers 13-1-13-(g-1) receiving a clock 12 whose period is 2T/m serially and doubling the period of the clock 12 sequentially, optical switch control lines 14-1-14-g used to connect outputs in multiple the clock 12 and the 1/2 frequency dividers 13-1-13-(g-1) to each stage of the 1Xm switches, optical delay circuits 15-1-15-m whose delay is respectively 0,T/m, 2T/m,..., (m-1)T/m and connecting respectively to outputs of the 1Xm optical switches 11, an mX1 photocoupler 16 and an output optical signal line 17 through which an output of the photocoupler 16 is sent.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical FIFO memory for controlling traffic of optical packets or converting throughput in an optical packet switch or the like.

[0002]

2. Description of the Related Art Conventionally, an optical FIFO memory of this type has been proposed in Japanese Patent Application No. 2-170578, and its operation principle will be described with reference to FIG. First, an optical packet signal having a fixed length t and a cycle t as shown in FIG. 4 arrives at the input optical signal line. Here, the packet intervals are separated by the guard time required for the processing performed in the subsequent stage. Then, the arrived optical packet is a tree type 1 ×
It is supplied to the (n + 1) optical switch.

On the other hand, the k-bit binary counter is multiple-connected to each 1 × 2 optical switch of each stage via an optical switch control line, and the k-bit binary counter is set to 1 depending on the value of each bit of the counter.
The switch of the × 2 optical switch is switched. This switch switching is performed by binary tree selection logic without using a decoder. As a result, the optical packet is output to the designated output position on the time axis. Here, for example, when all the bits of the k-bit binary counter are 0, the optical packet is output to the # 0 terminal of the tree type 1 × (1 + n) optical switch. Such a tree type 1x
An optical delay circuit for giving a delay amount of 0, T, 2T, ..., (n-1) · T is connected to each output # 0 to # (n-1) of the (1 + n) optical switch. , #J terminals are provided with a delay of j · T. The outputs of these delay circuits are output to the output signal line via the (n-1) optical coupler.

On the other hand, when the optical packet detection circuit detects an optical packet on the input optical signal line in parallel with the above process, it supplies a count-up pulse signal which is an electrical signal to the above-mentioned k-bit binary counter. .. At this time, immediately after the optical packet is output from the 1 × (n + 1) optical switch described above and before the packet is next input to this switch, the counter value of the k-bit binary counter is set. Count up only one (see FIG. 4).
That is, when the optical packets continuously arrive at every cycle t, the counter value increases each time. As a result, in each optical packet, j · T, (j + 1) · T,
The delay of (j + 2) · T, ... Is given, and one optical packet signal is output to the output signal line at a rate of one time T. (See FIG. 4).

A countdown pulse signal is externally supplied to the k-bit binary counter once every time T to count down the counter value. As a result, the interval between the optical packets is controlled so as not to exceed the predetermined value. Therefore, the output position of the optical packet on the time axis is determined by the timing at which the above-mentioned count-up pulse signal and count-down pulse signal are supplied, and cancels each other when both pulse signals are supplied. Furthermore, if the count value of the k-bit binary counter is n when the optical packet arrives, this optical packet is discarded as an overflow from the #n terminal. here,
This k-bit binary counter has a counter value not larger than n. Through the above operation, a signal string having a fixed length t and having at most one packet for each time T is output to this output optical signal line, and the function of the optical FIFO memory is realized.

[0006]

However, in the above-described conventional optical FIFO memory, the value of 1 in the time period T is reached.
Although it is possible to output so that no more than three packets are present, the intervals between adjacent packets are not always output at intervals of T or more, and perfect throughput control has not been realized. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an optical FIFO memory capable of outputting data with an interval between adjacent packets always being T or more.

[0007]

In order to solve the above problems, the present invention inputs an optical packet signal train of fixed length t,
An output unit that outputs an optical packet signal sequence in which 0 or 1 optical packet exists at each time interval T (T> t) and a plurality of 1 × 2 optical switches are used, and the j-th stage (j =
1, 2, ..., g) Each stage is configured so that the number of 1 × 2 optical switches is 2 ^j , and each output signal of the preceding 1 × 2 optical switch is 1 × 2 optical switch of the next stage. A 1 × m optical switch of g stages, each of which is connected so as to be input to the switch;
A control signal supply means for controlling the 1 × 2 optical switch by supplying the 1 × 2 optical switch at the j-th stage in the m optical switch by multiplying the period of the clock having a period of 2T / m by 2 ^(gj) times. , (M-1) T / m of delay amount 0, T / m, 2T / m, ..., Which are respectively connected to the outputs of the 1 × m optical switches, and the output of the delay line is coupled. It is characterized by comprising an m × 1 optical coupler and an output optical signal line for transmitting the output of the optical coupler.

[0008]

According to the above structure, the 1 × m optical switch is composed of 1 × 2 optical switches connected in a g-stage tree shape,
A control signal based on a clock with a period of 2 T / m is provided in each stage.
Each is supplied. At this time, the cycle of the control signal supplied to each stage is 2 ^(gj) times the clock at the j-th stage. As a result, the 1 × m optical switch repeatedly gives a signal having a fixed cycle.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. In this figure, 1 is an input optical signal line to which an optical packet signal is supplied, and 2-1 to 2-n are 1
× 2 optical switch. Reference numeral 3 denotes a 1 × (n + 1) optical switch, which includes 1 × 2 optical switches 2-1 to 2-n for k stages (k
= Log ₂ (n + 1)) It is configured by sequentially connecting in a tree type. 4 is an optical packet detection circuit, and 5 is an electrical k
It is a bit binary counter. 6-1 to 6-k is 1 × 2
It is an optical switch control line for controlling the optical switch. 7-1
7-n are optical delay circuits, each having a delay amount of 0, T, 2
,,, (n-1) · T is given. Reference numeral 8 is an n × 1 optical coupler, and 9 is an output optical signal line.

The configuration up to this point is as described in Japanese Patent Application No. Hei 2-17057.
8 and the operation of the optical packet up to this point is shown in FIG. That is, the output optical signal line 9 has a fixed length t
Then, a signal string in which at most one packet exists at each time T is output.

Next, 10-1 to 10- (m-1) is 1 ×
It is a two-optical switch. 11 is a 1 × m optical switch,
Similar to the 1 × (n + 1) optical switch 3, the 1 × 2 optical switches 10-1 to 10- (m-1) are equivalent to g stages (g = log _2).
m) It is configured by sequentially connecting in a tree type. Reference numeral 12 is a clock having a cycle of 2 T / m. 13-1 to 13- (g-
1) is a 1/2 frequency divider, which is connected in series to sequentially double the cycle of the clock 12. 14-1 to 14-g
Is an optical switch control line, and clocks 12 and 1/2
The outputs of the frequency dividers 13-1 to 13- (g-1) are multiply connected to each stage of the 1 × m switch. Reference numerals 15-1 to 15-m are optical delay circuits, which are connected to the outputs of the 1 × m optical switch, and have delay amounts of 0, T / m, 2T / m, ..., (m-1) T /.
have m. Reference numeral 16 is an m × 1 optical coupler that couples the outputs of the optical delay circuits 15-1 to 15-m, and 17 is an output optical signal line.

In the following, referring to FIGS. 1 and 2,
The operation after the output optical signal line 9 will be sequentially described. First, 1
The optical packet signal is input to the × m switch 11. Here, two or more packets do not exist in the cycle T but exist in a time slot in which T is equally divided. On the other hand, the outputs of the clock 12 and the 1/2 frequency dividers 13-1 to 13- (g-1) are
As shown in FIG. 2, 1 × m when each signal has the same phase
It is input to the optical switch 11 and a fixed control signal is always given to the time slot in T. For example, for the first time slot obtained by dividing T into m, the signal of all 0s, the second is 0, 0, ... Give 0.

Therefore, the optical delay circuits 15-1 to 15-m are installed at the respective distributed output ports, and then the optical packets are coupled by the m × 1 optical coupler 16 so that the optical packet is always in the last time slot of the cycle T. Output as it exists. Through the above operation, the output signal line 16 has a fixed length t.
Thus, an optical FIFO memory is realized in which adjacent packets can always be output with a distance of T or more.

[0014]

As described above, according to the present invention, it is possible to always output with the interval between adjacent packets being at least T. The 1 × (n + 1) optical switch in the first stage is switched by a binary tree selection logic, and the 1 × m switch in the second stage only gives a signal of a constant cycle repeatedly and controls both switches. Therefore, signal processing such as logical operation is unnecessary. Therefore, the switching time of the optical switch can be shortened. Further, even when a large-scale tree-type optical switch is configured, the optical packet paths have the same length for all paths, so that the optical output power can be made uniform.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart of the FIFO memory according to the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional optical FIFO memory.

FIG. 4 is a timing chart of a conventional optical FIFO memory.

[Explanation of symbols]

 1 Input Optical Signal Line 2-1 to 2-n 1 × 2 Optical Switch 3 1 × (n + 1) Optical Switch 4 Optical Packet Detection Circuit 5 kbit Binary Counter 6-1 to 6-k Optical Switch Control Line 7-1 ~ 7-n Optical delay circuit 8 nx1 optical coupler 9 Output optical signal line 10-1 to 10- (m-1) 1x2 optical switch 11 1xm optical switch 12 Clock 13-1 to 13- ( g-1) 1/2 divider 14-1 to 14-g optical switch control line 15-1 to 15-m optical delay circuit 16 m × 1 optical coupler 17 output optical signal line

Claims (1)

[Claims] 1. (a) Output means for inputting an optical packet signal sequence having a fixed length t and outputting an optical packet signal sequence such that 0 or one optical packet exists at each time interval T (T> t). (B) Using a plurality of 1 × 2 optical switches, the j-th stage (j =
1, 2, ..., g) Each stage is configured so that the number of 1 × 2 optical switches is 2 ^j , and each output signal of the preceding 1 × 2 optical switch is 1 × 2 optical switch of the next stage. A g-stage 1 × m optical switch connected so as to be input to each switch, and (c) each 1-th stage of the j-th stage of the 1 × m optical switch.
× 2 optical switch with 2T / m clock cycle
^(gj) times and supplies the control signal supply means for controlling the 1 × 2 optical switch, and (d) the delay amount 0, T / m, 2T / connected to the output of the 1 × m optical switch, respectively. m, ..., (m-1) T / m optical delay means, (e) m × 1 optical coupler for coupling the output of the delay line, and (f) output for transmitting the output of the optical coupler. An optical FIFO memory comprising an optical signal line.