JPH02186792A - Multi-input one-output light buffer - Google Patents

Abstract

PURPOSE:To reduce buffer quantity by accumulating data to be outputted to one output terminal in one buffer. CONSTITUTION:An input light signal from plural input terminals is switched and outputted to the optional terminal among plural change-over output terminals of a light switching means 13, and after signals from plural change- over output terminals are combined on a signal line to the output terminal of the multi-input one-output light buffer 12, signal delay quantity corresponding to each of plural change-over output terminals of the switching means 13 is given to the signal from each change-over output terminal by a light signal delaying means 14.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a multi-input, single-output optical buffer used in a switch node that accommodates multiple input/output highways in high-speed packet switching or asynchronous transfer mode (ATM) switching. The purpose of this method is to reduce the buffer size by storing data to be output in one buffer.In an optical buffer having multiple input terminals and a single output terminal, input optical signals from the multiple input terminals are an optical switching means for switching and outputting the signal to an arbitrary switching output terminal among the plurality of switching output terminals, and a signal path from the plurality of switching output terminals of the optical switching means to the output terminal of the optical buffer. and an optical signal delaying means for applying a signal delay amount corresponding to each of the plurality of switching output terminals of the optical switching means to the signal from each switching output terminal after the coupling.

[Industrial application field]

The present invention relates to optical switching systems such as I5DN, and more specifically to high-speed packet switching and asynchronous transfer mode (ATM).
) Relates to a multi-input single-output optical buffer used in a switch node accommodating multiple input/output highways in an exchange.

With the development of communication networks such as 15DN, the ATV switching method is attracting attention as a third switching mode that takes advantage of the respective advantages of high-speed packet switching, circuit switching, and packet switching. In such an exchange system, since data from a plurality of input highways may be simultaneously output to the same output highway, it is necessary to provide a buffer.

In order to further put optical communication systems into practical use, the configuration of optical buffers in switch nodes of optical exchanges has become an important issue.

[Conventional technology]

Typical conventional switching methods in communication networks such as I5DN include circuit switching methods and packet switching methods. When a circuit switching system handles many types of calls with large speed ratios, switching control becomes complex, and there are limits to the range of communication speeds that can be handled by one circuit switching network. The packet switching method has a complicated protocol and involves software processing, so there is a speed limit, and there is a problem that it cannot meet high-speed needs.

Therefore, like a wide-area 15DN, for example, 150 Mbit
AT is a third exchange mode that takes advantage of the advantages of both circuit switching and packet switching, and is capable of meeting the needs of handling data up to ultra-high speeds of up to 1/2 seconds.
A switching system called V (asynchronous transfer mode) is attracting attention.

In the ATM system, all information sent from a user, including data, is divided into short, fixed-length packets called cells, and a header of several bytes is attached to each cell. This cell header contains a logical channel number, an error check code for detecting header errors, and the like. In ATV exchanges, these cells are automatically switched by hardware to increase speed. That is, a cell in ATM switching is similar to a packet in packet switching, except that the data has a fixed length.

In high speed switching systems, such as ATV switching, buffers are used to avoid data from multiple input highways to the switch being output from one output highway at the same time, ie, data collisions. Particularly in optical switching equipment, since there is no physical buffer such as an electrical buffer for storing optical signals, a major problem is how to configure an optical buffer memory that performs the same function.

FIG. 7 shows a block diagram of the overall configuration of a conventional example of a switch node in an optical exchange. In the figure, each switch node 1 has n input and output terminals.

Signals from 0 input terminals are sent to n (IXn) write switch units 2a and 2b.

. . , 2n, and 0 outputs are output from n optical buffer memory sections 3a, 3b, . . . , 3n, respectively.

The optical buffer memory units 3a, 3b, ..., 3n are
Optical buffer section 4a and readout switch section 5a, 4, respectively.
It is composed of b, 5b, = ., 4n and 5n. Further, each of the optical buffer units 4a, 4b, . . . 4n has n optical buffers, for example, 4ml+4112+ .
．． It consists of n.

And these optical buffers 4ml+4m2+...4
Each of mn has a write switch section 2a.

Signals from 2b, . . . , 2n, that is, signals from each input terminal, are input. Further, the readout switch sections 5a, 5b, ..., 5n are, for example, multiplexers,
Optical buffer 4m++4mz+ ... combines the signals from 4mn and outputs them to the output terminal.

FIG. 8 shows optical buffer memory sections 3a, 3b, . . . , 3.
FIG. 2 is a block diagram showing the configuration of a conventional example of a device.

As shown in FIG. 7, for example, the optical buffer memory section 3a includes an optical buffer section 4a and a readout switch section, that is, a multiplexer 5a. There are optical buffers 4m + + 4m 21 in the optical buffer section a.

4mn, and signals from each input terminal of the switch node are input to each of these buffers, but the signals are processed by signal processing units 5a, 5b, and 5b provided in front of each buffer.
. . , is input through 6n.

These signal processing units detect that data is input from each input terminal, and notify the control unit 8 of this. In addition, the drive circuit 7 includes n optical buffers 4ml+41
12+..., for driving the internal optical switch of 41n.

In FIG. 8, for example, the optical buffer 4.1 is the unit optical buffer 4all+4m12+...4, I,
It consists of The configuration of each k-stage unit optical buffer is the same; for example, in 41,1, the signal processing unit 6
n optical switches 9m 1 + + to 9 ml I on a signal path, for example, an optical waveguide, through which the input optical signal from a passes.
n are provided in series, and a multiplexer 5.n is provided in series. n optical fiber rings 10m++t on the optical delay line connected to
~10.11n and n two-person optical couplers 1lal11
~11 m l I n are arranged alternately and sequentially as shown in the figure. Furthermore, the switching output of each optical switch on the optical waveguide is manually input to one input terminal of each two-power optical coupler, as shown in the figure.

As mentioned above, there is no physical buffer for storing optical signals, so data input to an optical switch is delayed by the necessary amount of time before being output, thereby performing the same function as a buffer. An optical fiber ring, for example, 10m++t to 10m++n, is used to delay this optical signal, and the signal processing unit 6. The delay time for the input signal is determined by whether the input optical signal is moved onto the optical delay line.

An optical fiber link delays an optical signal for a certain period of time by passing the optical signal through a certain length of optical fiber, for example. The total delay time from input to output of the optical signal is determined by how many optical fiber links are passed through. For example, by transferring the optical signal traveling on the optical waveguide onto the optical delay line by switching the optical switch 9a +
Compared to the case where + + is switched, a delay time corresponding to n optical fiber links can be provided. Here, for example, if the delay amount of one optical fiber link is the time equivalent to one cell in ATM exchange, the delay amount of the optical signal will be n cells.

In FIG. 8, the number of unit optical buffers 4m+ is 4all+ 4aI2r ""+ 46111
In other words, the number of stages of a unit optical buffer is determined by the information discard rate, necessary delay time, etc. That is, by increasing the number of stages k, it is possible to lengthen the delay time of the optical signal, but on the other hand, the amount of hardware increases, so data that must be delayed beyond a certain delay time must be discarded. , a value for the number of stages is determined as being related to how much such data exists, that is, the discard rate.

[Problem to be solved by the invention]

In the conventional structure of the switch node shown in FIG.
..., 4.7 was prepared, and the optical signals from each input terminal were stored independently. However, this method has the problem that as the scale of the switch (the number of input/output terminals) increases, the amount of buffer increases rapidly, which increases the size of the device and increases the cost.

An object of the present invention is to reduce the amount of buffering by storing data to be output to one output terminal in one buffer.

[Means to solve the problem]

FIG. 1(a) is a block diagram of the principle of the first invention.

In the figure, the multi-input/l-output optical buffer 12 is arranged in a vertical column among the unit optical buffers in the conventional example shown in FIG. 8, for example, 4*Il+48□1. . . 4 m n I, and consists of an optical switching means 13 and an optical signal delay means 14.

The optical switching means 13 outputs optical signals from a plurality of input terminals to any one of the plurality of switching output terminals, for example, the unit optical buffers 4a+t+4mz++..., 4□ in FIG. nl, n optical switches are provided on each signal line from each input terminal.

The optical signal delay means 14 couples the signals from the switching output terminals of the optical switching means 13 onto the signal path to the output terminal of the optical buffer 12, and then gives each signal a signal delay amount corresponding to each switching output terminal. So, for example, the 8th
This corresponds to a plurality of optical fiber links and optical cubes on the optical delay line in the unit optical buffer 4mII in the figure.

That is, in the present invention, the unit optical buffers 4all+4m21+...4Mn in the conventional example shown in FIG.
In I, the optical delay line part is used in common, for example, optical switches 9mtt+, 9mz+%,...9 a n l
All of the l switching optical outputs are input to one optical coupler IL+++, thereby forming a multi-input, one-output optical buffer.

The meaning is a little different from the conventional example shown in FIG. 8, but if this is also called a unit optical buffer, an optical buffer memory in which a plurality (k) of such unit optical buffers are connected is, for example, shown in FIG. 7. Optical buffer memory section 3. The output of the optical signal delay means 14 of the final stage unit optical buffer becomes the output of the switch node. Here, optical switching means 1
3, the switching output of the optical switches connected in series becomes the input to the subsequent stage as in FIG. 8, and as for the optical signal delay means 14, as in FIG. The stages are connected in such a way that the maximum delay in the optical buffer is added to the delay of the signal from the previous stage. In a switch node of an optical exchange, such an optical buffer memory is individually provided for each of the n outputs of the switch node.

FIG. 1(9) is a functional block diagram of the second invention.

In the figure, among the data input from multiple input terminals of a multi-input single-output optical buffer, one
5, the time interval between the two is determined. 1 in an ATM exchange whose interval corresponds to the fixed bucket length.
If the delay is within one cell, a delay amount of one cell is given to the subsequent data compared to the data outputted first at 16.

When the time interval is greater than or equal to one cell and less than or equal to two cells, the same delay amount of 17 as the previously output data is given to the subsequent data. Also, if the time interval is more than j (≧2) cells, (
j+1) cells, the subsequent data has an advance of (j-1) cells compared to the data to be output first.
is given by This is to minimize the propagation delay time as much as possible and speed up data output.

[For production]

The present invention will be explained in detail with reference to FIGS. 1(a) and 1(b).

In FIG. 1(a), cells serving as data inputted from a plurality of input terminals to the multi-input/one-output optical buffer 12 must be outputted from one output terminal without collision. For this reason, the arrival time of the cell input from each input terminal to the optical switching means 13 is monitored by, for example, a control unit (not shown), and two
The time interval between the two data is determined at 15 in FIG. 1 et al. Then, depending on the time interval, which optical switch in the optical switching means 13 is to be switched is controlled.
6.17.18, the time interval between the first data and the subsequent data is adjusted and the data is output, making it possible to avoid cell collisions on the output highway of the optical exchange.

〔Example〕

FIG. 2 is a block diagram of the overall configuration of an embodiment of a switch node according to the present invention. In the same figure, switch node 1
Reference numeral 9 has basically the same structure as the conventional example shown in FIG. .

2b, °°t, 2n and light bar sofa memory 20a
.

20b, . . . , 20n.

However, in the present invention, the optical buffer memory 20
a, 20b, . . . , 2On differ from the optical buffer memory sections 3a, 3b, . . and optical buffer memory 20a
, 20b, . . . , 20n each consist of a stage of unit optical buffers, as shown in the figure.

FIG. 3 is a block diagram of the configuration of an embodiment of the optical buffer memory according to the present invention. In the figure, a signal processing section 6a,
6b, . . . , 6n notify the control unit 21 of the arrival of signals from each input terminal, similar to the conventional example shown in FIG. The control unit 21 controls the optical switch drive circuit 22 inside the optical fiber sofa memory 20a. Further, the optical buffer memory 20a includes k stages of unit optical buffers 20.1, 20.2, . ..., 20-k are connected in cascade.

The structure of each stage of unit optical buffers connected in cascade is all the same. For example, the unit optical buffer 20AI has n optical switches, for example, 23. I23-12°..., 23aIn
are connected in series, and on the other hand, n optical fiber links 2411 to 24In and n optical couplers 25. , ~2517 are connected alternately in series as shown in the figure, and the switching outputs of each optical switch installed on the signal line from the input terminal side are sequentially connected as shown in the figure when viewed from the input terminal side. is input to each optical coupler on the optical delay line.

For example, the closest n optical switches 23-+fi to 23n1 .
All switching outputs are input to the input terminal of the optical coupler 251n. As described above, in the present invention, compared to the conventional example shown in FIG. 8, only one optical delay line is required to perform the optical buffer function, and the number of optical fiber links and optical couplers is significantly reduced.

FIG. 4 shows an algorithm and an embodiment of the data output control method according to the present invention. Figure (a) shows the algorithm of the control method, and the delay amount of subsequent data is is determined, and the driving point of the optical switch in FIG. 3 is changed. If the cell input interval is within one cell, it is necessary to delay the subsequent data, so the delay amount is set to +1 and the drive point of the optical switch is delayed by one cell. When the input interval is in the range of 1 to 2 cells, there is no need to delay subsequent data, so the delay amount is set to O, and there is no need to change the driving point of the optical switch.

When the cell input interval is two cells or more, it is necessary to advance the output timing of subsequent data in order to speed up the output. In other words, the cell input interval is j (≧2)
In the case of (j+1) cells, the delay amount is -(j-IL
That is, the driving point of the optical switch is advanced by (j-1) times to output the subsequent cell. For example, if the input interval is 2
and 3 cells, the output timing of the subsequent data is advanced by one cell.

FIGS. 4(b) and 4(c) show an embodiment of a method for controlling the output of cell data input from three input terminals. In the figure (b), data A, B, C, . . . are all data with a length of one cell. When the first data A is input from the input terminal side, there is no need to delay the data, so the optical switch 23-++ shown in FIG.

Next, data B is input, but since the interval between data B and data A is within one cell, the optical switch 23b+z is switched to delay data B by one cell, and data B is input via the optical coupler 2512. Optical fiber link 241
1 and is output after being delayed by one cell. Furthermore,
Since data C was input at the same time as data B,
Data C is switched by an optical switch 23c13 to delay data B by one cell.

Similarly, data D is delayed by one cell compared to data C, and data E is delayed by one cell compared to data D, and data D is delayed by one cell.
is the optical switch 23-21, and data E is the optical switch 23c.
22 and output after a necessary delay time. Next, since data F has an input interval of two cells or more compared to data F, its output timing is advanced by one cell in order to speed up data output.

That is, the data F is switched by the optical switch 23bz+ and outputted in a format in which the output interval between the data E and the data E is shortened by one cell. Similarly, data G, H,
I and J are optical switches 23c22 and 23-23, respectively.
,23bz3. and 23C31, and is output after being delayed by a predetermined time.

FIG. 5 is a block diagram showing the structure of the drive circuit and control section in the embodiment of the optical buffer memory shown in FIG. In the figure, signal processing units 6a and 6b.

. . , 6n and the configuration of the optical buffer memory 20a are exactly the same as those shown in FIG. In FIG. 5, the arrival time of cells from each input terminal is determined by the signal processing unit 6a.

6b, . . . , 6n, and the time checking circuit 26 in the control unit 21 checks the monitoring results.

The output data identification circuit 27 determines a cell with an early arrival time based on the verification result of the time verification circuit 26. The comparison circuit 28 calculates the difference in arrival time between the cell, that is, the next data to be output and the previously output data, and sends the result to the driving pulse output circuit 29. The driving pulse output circuit 29, based on the comparison result of the comparison circuit 28,
A necessary amount of delay is calculated, and a driving pulse corresponding to the amount of delay is sent to the driving circuit 22.

The drive circuit 22 is a drive pulse output circuit 29 of the control section 21.
a decoder 30 for decoding driving pulses from the
n optical switches located in the same position when viewed from the input terminal side in the optical buffer memory 20a, for example 23-++
~23. ．． An optical switch driving section 31a that drives optical switches up to +1 and an optical switch driving section 31b having exactly the same configuration.

Consists of... The optical switch driving section 31a also includes a decoder 32' for decoding the signal from the decoder 30).
and n voltage generating circuits 3311 to 33.7 for driving each optical switch.

Here, the number of input bits to the decoder 32a is the number of bits required to distinguish n optical switches, that is, log
2 n. In addition, n optical switch drive units are required for each unit optical buffer, and a total of kn optical switch drive units are required for a k-stage unit optical buffer, so the number of input bits of the decoder 30b is is log,
(k n logz n ).

FIG. 6 shows a comparison of the amount of hardware between the optical buffer memory of the present invention and a conventional example. By comparing the embodiment shown in FIG. 3 and the conventional example shown in FIG. The amount of coupler is significantly reduced. In FIG. 3 of the present invention, for example, the unit optical buffer 2
The number of optical switches within 01° is n2, and the numbers of optical fiber links and optical couplers are each n. Since several stages of such unit optical buffers are connected in cascade, the number of optical switches is n2, and the number of optical fiber links and optical couplers is each nk. On the other hand, in the conventional example shown in FIG. It does not increase rapidly as in the example, but is only proportional to n.

[Effects of the Invention] As explained above, according to the present invention, data from each input terminal is commonly stored in one buffer for each output terminal of a switch node and sent out, thereby improving buffer usage efficiency. However, the amount of buffers constituting the switch node can be reduced, which greatly contributes to miniaturization and cost reduction of optical communication devices.

[Brief Description of the Drawings] Figure 1(a) is a block diagram of the principle of the first invention;
b) is a functional block diagram of the second invention; FIG. 2 is a block diagram showing the overall configuration of an embodiment of a switch node in the present invention; FIG. 3 is a block diagram showing a configuration of an embodiment of an optical buffer memory; Figure 5 is a diagram showing the algorithm of the data output control method and its embodiment; Figure 5 is a block diagram showing the configuration of the drive circuit and control section of the optical buffer memory; and Figure 6 is the diagram showing the configuration of the optical buffer memory of the present invention FIG. 7 is a block diagram showing the overall configuration of the conventional example of a switch node; FIG. 8 is a block diagram showing the configuration of the optical buffer memory section of the conventional example. DESCRIPTION OF SYMBOLS 12... Multi-input l-output optical buffer, 13... Optical switching means, 14... Optical signal delay means, 19... Switch node, 20a-20n... Optical buffer memory, 2I... Control Part, 22... Drive circuit, 23, . 1~23.3n, 23n+t~23n! n...
・Optical switch, 24+t ~ 24311 ... Optical fiber link, 2
511-253. ...Optical coupler.

Claims (1)

[Claims] 1) In an optical buffer (12) having a plurality of input terminals and a single output terminal, input optical signals from the plurality of input terminals can be arbitrarily switched among the plurality of switching output terminals. An optical switching means (13) for switching to an output terminal and outputting an output;
After coupling the signals from the plurality of switching output terminals of 13) onto the signal path to the output terminal of the optical buffer (12), a signal delay corresponding to each of the plurality of switching output terminals of the optical switching means (13) is performed. a multi-input, single-output optical buffer, characterized in that it has an optical signal delay means (14) for providing a signal from each switching output terminal with a certain amount of time. 2) In an optical buffer having a plurality of input terminals and a single output terminal, determining the time interval between two pieces of data that are input from the plurality of input terminals and to be output to the output terminal one after the other (15); If the time interval is within 1 cell corresponding to the fixed packet length, a delay amount of 1 cell is given to the subsequent data compared to the data output earlier (16), and the delay amount is greater than or equal to 1 cell and less than or equal to 2 cells. When , the same amount of delay as the previously output data is given to the subsequent data (17), and when it is greater than or equal to j (≧2) cells and less than (j+1) cells, the delay is given to the subsequent data by (j-1) compared to the previously output data. ) A data output control method in a multi-input, single-output optical buffer, characterized in that a data collision on an output terminal is avoided by applying an advance amount for a cell to subsequent data (18) and outputting the data.