JP2840654B2 - Optical FIFO memory - Google Patents

Description

The present invention relates to an optical FI that performs traffic control or throughput conversion of an optical packet in an optical packet switch or the like.
Regarding FO memory.

2. Description of the Related Art Conventionally, an optical FIFO memory of this type has been proposed in Japanese Patent Application No. 1-255043, and its operation principle will be described with reference to FIG.

First, an optical packet signal having a fixed length t and a period t arrives at the input optical signal line 11. Here, each packet is provided with guard bits as necessary for the subsequent switch switching processing time. The arriving optical packet is 1 × (n) composed of (n + 1) 1 × 2 optical switches 12 _{0 to} 12 _n connected in series.
+1) Input to the optical switch 12 and each 1 × 2 optical switch 12
₀ through the port 0 side to 12 _n, k-bit binary counter
13 and port # 1 from terminal #j designated by decoder 14.
Output to the side. This serial type 1 × (n + 1) optical switch
The output of the 12 each delay amount 0, T, 2T, ..., are supplied to the optical delay circuit 15 ₀ ~15n-1 for delaying the (n-1) T. For example, the optical packet signal output from the terminal #j is given a delay of jT, which is (n ×
1) The signal is output from the output optical signal line 18 via the coupler 16.

On the other hand, when detecting the optical packet on the input optical signal line 11, the optical packet detection circuit 17 supplies a count-up pulse signal to the k-bit binary counter 13 described above. At this time, if the optical packet is immediately after output from the 1 × (n + 1) optical switch 12 and before the next packet is input to the switch 12, the counter value of the counter 13 becomes 1
Only one is counted up (see FIG. 2). That is, when an optical packet is detected every period t, the counter value increases each time. As a result, delays of jT, (j + 1) T, (j + 2) T,... Are sequentially given to the optical packet signal, and one optical packet signal is output to the output optical signal line 18 at a time T. It is output (see FIG. 2).

Also, this k-bit binary counter 13 has 1
A countdown pulse signal is supplied from the outside at the rate of the count, and the counter value is counted down. This allows
The packet interval is controlled. Therefore, the output position on the time axis of the optical packet is determined by the above-described count-up pulse signal and count-down pulse signal, and if both pulse signals are present, they cancel each other.

Further, if the counter value is n when the optical packet arrives, the optical packet is discarded from the terminal #n as an overflow (see FIG. 1). Here, it is assumed that the value of the k-bit binary counter 13 does not become larger than n.

By the above operation, a signal sequence having a fixed length t and at most one packet every time T is output to the output optical signal line 18, and the function of the optical FIFO memory is realized.

[Problem to be Solved by the Invention] However, in the above-described conventional optical FIFO memory, since it takes time to decode the counter value, it is necessary to lengthen a guard bit between input optical packets. For this reason, there is a problem that the throughput is reduced. In addition, in order to give each packet a delay of 0 to (n-1) .T, each packet must pass through a different number of stages of optical switches. There is also a problem that the power of the output optical packet differs depending on whether the packet is output.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an optical FIFO memory capable of shortening the switching time of an optical switch and making the power of an output optical signal uniform.

[Means for Solving the Problems] The present invention relates to an input optical signal line for transmitting an optical packet signal of a fixed length t, and 2 ⁱ 1 (i = 1, 2,..., K) ×
A 1 × (n + 1) optical switch formed by sequentially connecting two optical switches to form a k-stage tree, an optical packet detecting circuit for generating a detection signal when an optical packet arrives at the input optical signal line, A k-bit binary counter that counts up each time the detection signal is supplied and counts down in response to a count-down signal supplied from the outside every time T, and outputs each bit output of the k-bit binary counter to the 1 × (N + 1) optical switch control lines that are multiplex-connected to each stage of the optical switch, and each of which is connected to the output of the 1 × (n + 1) optical switch and has a delay length of 0, T, 2T,. n × 1 for coupling n kinds of optical delay lines and signals of the optical delay lines
An optical coupler is provided, and an output optical signal line for transmitting an output of the optical coupler is provided.

[Operation] According to the above configuration, the 1 × (n + 1) optical switch has k
It is composed of 1 × 2 optical switches connected in a tree shape,
Each bit output of the k-bit binary counter is 1 × (n +
1) Multiple connections are made to each stage of the optical switch. This allows
The 1 × (n + 1) optical switch is switched by the binary tree selection logic.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In this figure, 1 is an input optical signal line to which an optical packet signal is supplied, and 2-1 to 2-n are 1 × 2 optical switches. 3 denotes the 1 × 2 optical switches 2-1 to 2-n
Are connected in a k-stage (k = log ₂ (n + 1)) tree type for a 1 × (n + 1) optical switch. 4 is an optical packet detection circuit, and 5 is an electrical k-bit binary counter. Reference numerals 6-1 to 6-k denote optical switch control lines for controlling the 1 × 2 optical switch. Reference numerals 7-1 to 7-n denote optical delay circuits, which provide delay amounts 0, T, 2T,..., (N-1) · T.
8 is an n × 1 optical coupler, and 9 is an output optical signal line. Hereinafter, the operation of this embodiment will be sequentially described with reference to FIG. 1 and FIG.

First, a fixed length t as shown in FIG.
-An optical packet signal having a period t arrives. Here, the intervals between packets are separated by guard bits as necessary for the processing performed in the subsequent stage. Then, the arrived optical packet is supplied to the tree-type 1 × (n + 1) optical switch 3. On the other hand, the k-bit binary counter 5 is multiplex-connected to the 1 × 2 optical switches 2-1 to 2-n of each stage via the optical switch control signal lines 6-1 to 6-k, respectively. 1 × 2 optical switch 2 according to the value of each bit of 5
−1 to 2-n are switched. This switch is performed by binary tree selection logic without using a decoder. As a result, the optical packet is output to the specified output position on the time axis. Here, for example, when all bits of the k-bit binary counter 5 are 0, the optical packet is a tree-type 1 × (n + 1) optical switch 3.
Is output to the # 0 terminal. Such a tree type 1 × (n
+1) For each output # 0-# (n-1) of the optical switch 3,
Optical delay circuits 7-1 to 7-n for respectively providing delay amounts 0, T, 2T,..., (N-1) T are connected. For example, an optical packet output from a terminal #j includes A delay of jT is provided. The outputs of the optical delay circuits 7-1 to 7-n are output to the output optical signal line 9 via the (nx1) optical coupler 8.

On the other hand, when the optical packet detection circuit 4 detects an optical packet on the input optical signal line 11 in parallel with the above process, it supplies a count-up pulse signal, which is an electrical signal, to the k-bit binary counter 5 described above. . At this time, immediately after the optical packet is output from the above-mentioned 1 × (n + 1) optical switch 3 and before the next packet is input to the switch 3, the k-bit binary counter 5 Only one counter value is counted up (see FIG. 2). That is, when an optical packet continuously arrives at every cycle t, the counter value increases each time. Thereby, each optical packet sequentially includes j · T, (j + 1) · T,
The delay of (j + 2) · T,...
, One optical packet signal is output at a time T (see FIG. 2).

Also, this k-bit binary counter 5 has 1
A countdown pulse signal is supplied from the outside at the rate of the count, and the counter value is counted down. This allows
Control is performed so that the interval between the optical packets does not exceed a predetermined value.
Therefore, the output position on the time axis of the optical packet is determined by the timing at which the count-up pulse signal and the count-down pulse signal are supplied, and when both pulse signals are supplied, they cancel each other.

Further, when the count value of the k-bit binary counter 5 is n when the optical packet arrives, the optical packet is discarded from the terminal #n as an overflow. Here, it is assumed that the counter value of the k-bit binary counter 5 does not become larger than n.

By the above operation, a signal sequence having a fixed length t and at most one packet every time T is output to the output optical signal line 18, and the function of the optical FIFO memory is realized.

“Effect of the Invention” As described above, according to the present invention, 1 × (n +
1) The optical switch is composed of 1 × 2 optical switches connected in a k-stage tree shape, and each bit output of a k-bit binary counter is multiplex-connected to each stage of the 1 × (n + 1) optical switch. As a result, the 1 × (n + 1) optical switch is switched by the binary tree selection logic, so that no decoder is required. Therefore, the switching time of the optical switch can be shortened.

In addition, even when a small-scale integrated tree-type optical switch is further connected in a tree-type configuration to form a large-scale tree-type optical switch, the optical packet paths are similar to all paths, so that the output optical power is uniform. Can be Moreover, needless to say, the tree type 1 × (n + 1) of the present invention is used.
The amount of hardware of the optical switch, that is, the number of elements of the 1 × 2 optical switch can be configured to be substantially the same as that of the conventional serial 1 × (n + 1) optical switch.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention,
FIG. 2 is a timing chart of an optical FIFO memory according to a conventional example and the present invention, and FIG. 3 is a block diagram showing a configuration of a conventional optical FIFO memory. 1 ... input optical signal line, 2-1 to 2-n ... 1 x 2 optical switch, 3 ... 1 x (n-1) optical switch, 4 ... optical packet detection circuit, 5 ... k bit 2 Hexadecimal counter, 6-1 to 6-k optical switch control line, 7-1 to 7-n optical delay circuit, 8 n × 1 optical coupler, 9 output optical signal line.

Continuation of front page (56) References JP-A-3-117249 (JP, A) JP-A-2-186793 (JP, A) JP-A-60-244184 (JP, A) Lectures of IEICE Autumn National Convention Papers, B-283 (1991-8-15), p3-2 IEICE Technical Report, SS E90-83 (1990-11-22), p7-12 IEICE Technical Report, SS E88 −112 (1988−10−19), p13−18 (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/28 H04L 12/56 H04Q 11/00-11/08 H04B 10/00- 10/28

Claims (1)

(57) [Claims] 1. An input optical signal line for transmitting an optical packet signal of a fixed length t, and (b) 2 _i 1 × 2 at an i-th stage (i = 1, 2,..., K). 1 × consisting of optical switches connected sequentially and configured in a k-stage tree
(N + 1) an optical switch; (c) an optical packet detection circuit for generating a detection signal when an optical packet arrives at the input optical signal line; (d) counting up each time the detection signal is supplied; (E) multiplexing each bit output of the k-bit binary counter to each stage of the 1 × (n + 1) optical switch; (F) n types of optical delay lines connected to the output of the 1 × (n + 1) optical switch and having delay lengths 0, T, 2T,..., (N−1) T; (G) an n × 1 optical coupler for coupling the signals of the optical delay line; and (h) an output optical signal line for transmitting an output of the optical coupler.