JPH06104707A - Delay device - Google Patents

Abstract

PURPOSE:To set and change the delay time with the simple control and without causing the malfunctions of the peripheral circuits. CONSTITUTION:The bypass lines of signals and the bypass open/close parts which open and close the bypass lines are provided for each block consisting of groups of n-th power of 2 (n=0, 1, 2, 3...n) delay elements, that is, o-th power of 2 (1 piece), first power of 2 (2 pieces), second power of 2 (4 pieces) .... In such a constitution, the numbers of both bypass lines and bypass open/close parts can be decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay device capable of changing a signal delay time in various signal processing circuits.

[0002]

2. Description of the Related Art In a conventional delay device of variable delay time,
A plurality of delay elements are connected in series, and a bypass line for bypassing a signal and a changeover switch for opening and closing the bypass line are provided for each delay element.

FIG. 4 is a diagram showing an example of such a delay time variable type delay device.

This delay device includes seven delay elements D1 to D1.
7 are connected in series, and bypass lines L11 to L17 and changeover switches SW11 to S7 are provided for each delay element D1 to D7.
W17 is provided. This delay device is a synchronous delay device, and the delay elements D1 to D7 input and output the signal S in synchronization with the clock CLK, respectively, and set the delay time within a time range of 0 clock to 7 clocks. It changes.

That is, when delaying by one clock, for example, only the bypass line L11 is closed (disconnected) and the other bypass lines L12 to L17 are opened (opened) so that the changeover switches SW11 to SW17 are opened. The signal S passes through only the delay element D1 and does not pass through the other delay elements D2 to D7. When delaying by 2 clocks, the changeover switches SW11 to SW17 are controlled so that, for example, the bypass lines L11 and L12 are closed (disconnected) and the other bypass lines L13 to L17 are opened (open). By doing so, the signal S passes through the delay elements D1 and D2 and does not pass through the other delay elements D3 to D7. When delaying by 7 clocks, all the bypass lines L11 to L1
7 is closed (disconnected) so that the signal S has all the delay elements D1 to D1.
When the delay time is set to “0”, that is, when no delay is applied, all bypass lines L
11 to L17 are opened (opened) so that the signal S does not pass through all the delay elements D1 to D7. That is, the signal is made to pass through the number of delay elements corresponding to the clock time to be delayed.

[0006]

However, in the conventional delay device, since the bypass lines and the changeover switches are provided for all the delay elements, the number of the bypass lines and the changeover switches is large, and the bypass lines are changed. Opening and closing control of the line was complicated.

If no delay is applied, the signal must pass through all the many bypass lines and changeover switches, and when this transit time exceeds one clock time, the peripheral circuits malfunction. It was

The present invention has been made under such circumstances, and an object thereof is to make it possible to change the setting of the delay time with simple control and without causing malfunction of the peripheral circuits.

[0009]

In order to achieve the above object, according to the present invention, a plurality of delay elements are connected in series and the delay time is changed within the total delay time of the total delay times of the delay elements. In a possible delay device, n of 2 (n = 0,
1, 2, 3, 3, ..., n) Each of the delay element groups is provided as a block, and a bypass line for bypassing a signal and a bypass opening / closing unit for opening / closing the bypass line are provided. ing.

[0010]

In the delay device according to the present invention, the bypass line for bypassing the signal and the bypass opening / closing portion for opening / closing the bypass line are not provided in a one-to-one relationship with each delay element, and n (n = n) of 2 is provided. 0, 1, 2, 3, 3, ..., N) delay element groups, that is, 2 0 = 1 delay, 2 1 = 2 delays, 2 2 = 4 delays, The element group is provided for each block with one block.

In this case, for example, assuming that the delay time per delay element is 1 μsec, when delaying by 1 μsec, the bypass opening / closing section of each block has a bypass line corresponding to one delay element block. Close, open the bypass line corresponding to the other block,
Allow the signal to pass through only one delay element. Also, 3
When delaying by μsec, the bypass opening / closing unit of each block closes each bypass line corresponding to one delay element block and two delay element blocks, and opens the bypass lines corresponding to other blocks, Allow the signal to pass through the three delay elements.

In this way, the delay time is set and changed within the range of the total delay time obtained by adding the delay times of the respective delay elements. At this time, as described above, the bypass line and the bypass opening / closing section need not be provided in a one-to-one relationship with each delay element.
By providing 2 n (n = 0, 1, 2, 3, ..., N) power groups of delay elements in units of blocks, the number of bypass lines and bypass opening / closing sections is reduced. Therefore, the control when changing the delay time is simplified. Further, in the synchronous delay device, when the delay is not applied, the transit time of the signal does not exceed 1 clock time, and the malfunction of the peripheral circuit can be prevented.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing the outline of a delay device according to an embodiment of the present invention, and like the conventional delay device in FIG. 4, seven delay elements D1 to D7 are connected in series. However, the bypass line and the changeover switch are different from the conventional delay device in that they are not provided on a one-to-one basis with the delay elements D1 to D7.

That is, the bypass line L1 and the changeover switch SW1 are arranged for the delay element D1, the bypass line L2 and the changeover switch SW2 are arranged for the delay elements D2 and D3, and the delay elements D4 to D7. A bypass line L3 and a changeover switch SW3 are provided for the. That is, the bypass line and the changeover switch are
In the prior art, seven pieces were provided, but in the present embodiment, three pieces are provided and the number is reduced.

The manner of disposing the bypass lines L1 to L3 and the changeover switches SW1 to SW3 is based on the following rules. That is, n of 2 (n = 0, 1, 2,
3, ..., N) A delay line for bypassing a signal and a changeover switch for controlling the opening / closing of the bypass line are provided in each block unit in which a number of delay element groups each of which is one power block. That is, as shown in FIG. 2, a block of 2 0 delay elements, a block of 2 1 delay elements, a block of 2 2 delay elements,
Bypass blocks and changeover switches are arranged in units of blocks for 2 k blocks of delay elements, and 2 n blocks of delay elements.

Each of the delay elements D1 to D7 inputs and outputs the signal S in synchronization with the clock CLK.
Specifically, it is composed of a D flip-flop, a master-slave type JK flip-flop, and the like. Also,
The changeover switches SW1 to SW3 are the bypass lines L1 to
It has a contact point O for opening L3 and a contact point C for making it non-conductive.

The delay time setting circuit 1 (not shown) arbitrarily switches the changeover switches SW1 to SW3 to the contact O side or the contact C side to delay the delay time of an arbitrary number of clocks CLK. Is to be set. Although the delay time setting circuit 1 is described as an independent circuit in FIG. 1, in a general signal processing circuit, the control function of the delay time setting circuit 1 is often handled by the CPU or the like.

The delay time setting circuit 1 includes a changeover switch SW.
When switching 1 to SW3 to the contact O side to bypass the signal S, that is, when the signal S does not pass through the block of the delay element, the bypass opening signal "0" is given to the changeover switches SW1 to SW3 to perform the switching. Switch SW1
When SW3 is switched to the contact C side and the signal S is not bypassed, that is, when the signal S passes through the block of the delay element, the bypass closing signal "1" is given to the changeover switches SW1 to SW3. In this case, the delay time when the bypass closing signal “1” is given only to the changeover switch SW1 is 2 0 = 1 clock, and the delay time when given only to the changeover switch SW2 is 2 1 = This is 2 clocks, and the delay time when given only to the changeover switch SW3 is 2 2 = 4 clocks.

Next, the delay time setting operation by the delay time setting circuit 1 will be specifically described.

The delay time setting circuit 1 sets the delay time based on the table of FIG. That is, the table of FIG. 3 shows the delay time (how many clocks the delay time is).
And the bypass opening signal “0” and the bypass closing signal “1” given to the changeover switches SW1 to SW3. The numbers shown in () below SW1, SW2, and SW3 in FIG. 3 are the changeover switches SW1 and S described above.
It shows how many clock cycles each of the delay times when the bypass closing signal "1" is given to W2 and SW3 independently.

As shown in FIG. 3, the delay time setting circuit 1
For example, when the signal S is not delayed, that is, when the delay time “0” is set, all the changeover switches SW are
By giving the bypass opening signal "0" to 1 to SW3,
The signal S is prevented from passing through any of the delay elements D1 to D7.

Further, for example, when setting the delay time for one clock, the bypass closing signal "1" is given to the changeover switch SW1 and the bypass opening signal "0" is given to the changeover switches SW2 and SW3. This allows the signal S to pass only through the delay element D1.

Further, for example, when the delay time of 6 clocks is set, the bypass opening signal "0" is given to the changeover switch SW1 and the bypass closing signal "1" is given to the changeover switches SW2 and SW3. As a result, the signal S is transmitted to the group of delay elements D2 and D3 and the delay element D4.
.About.D7 group through a total of 6 delay elements.

In this way, the delay time setting circuit 1
Set the delay time for any number of clocks. in this case,
Since the number of bypass lines and changeover switches has been reduced from 7 in the past to 3, the control by the delay time setting circuit 1 is simplified, and when the delay is not applied, the signal S
However, the time for passing through the delay device does not exceed one clock time, and malfunction of peripheral circuits can be avoided. The larger the number of delay elements, that is, the longer the delay time that can be set, the greater the reduction rate of the number of bypass lines and changeover switches with respect to the conventional delay device, and the above-mentioned effect becomes remarkable.

The present invention is not limited to the above embodiment, but can be applied to, for example, an asynchronous delay device. In this case, by forming a plurality of groups that combine delay elements with different delay times,
It is also possible to reduce the degree of discreteness of each delay time that can be set and finely set the delay time.

In this embodiment, the changeover switch is provided on the signal input side for each group of delay elements, but the changeover switch may be provided on the signal output side.

[0028]

As described in detail above, according to the delay device of the present invention, n of 2 (n = 0, 1, 2, 3, ...,
n) a bypass line for bypassing a signal in each block unit in which the number of delay element groups is one block,
Since the number of the bypass lines and the changeover switches is reduced by adopting the configuration in which the changeover switch for opening and closing the bypass line is provided, it becomes easy to control the opening and closing of the bypass line, and when the delay is not applied, The time taken for the signal to pass through the delay device does not exceed one clock time, and the malfunction of the peripheral circuits can be avoided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a delay device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a generalized regularity of grouping of delay elements in FIG.

FIG. 3 is a diagram showing a relationship between a state of a changeover signal of each changeover switch and a delay time.

FIG. 4 is a block diagram showing a schematic configuration of a conventional delay device.

[Explanation of symbols]

 1 ... Delay time setting circuit D1-D7 ... Delay element L1-K7 ... Bypass line SW1-SW7 ... Changeover switch S ... Signal CLK ... Clock

Claims (1)

[Claims] 1. A delay device in which a plurality of delay elements are connected in series and the delay time can be changed within a range of a total delay time obtained by summing the delay times of the respective delay elements, n of 2 (n = 0, 1) , 2, 3, ..., N) By-pass lines for bypassing a signal and a bypass opening / closing unit for opening / closing the bypass line are provided for each block in which each of the delay element groups is a block. Delay device characterized by.