JP2007249639A - Spectrum diffusion clock generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To respond to a plurality of modulation degrees by a simple circuit structure while suppressing increase in circuit scale. <P>SOLUTION: This generator comprises a delay circuit 10 including a plurality of serially connected delay cells 11, each of the cells outputting input clock CLK with delay by a unit delay quantity; clock input circuits 20_0, 20_1, to 20_7 which input the clock CLK to the delay circuit 10; and a bypass circuit 4 including a two-input NAND gate 2 and an inverter 3. In a first mode for deep modulation degree, the clock CLK propagated from the propagation upstream side of the clock CLK of the delay circuit 10 to a first point P1 in the middle of the delay circuit 10 is transferred to the delay cell 1 on the downstream side closest to the first point P1, and in a second mode for shallow modulation degree, the clock CLK propagated to the first point P1 is inputted to the delay cell 11 of a second point P2 on the propagation downstream side of the clock CLK from the first point P1 of the delay circuit 10 while bypassing the middle of the delay circuit 10. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a spread spectrum clock generator that generates a spread spectrum clock whose frequency varies periodically from a constant frequency clock.

  2. Description of the Related Art In recent years, with increasing speed and density of electronic devices, electromagnetic noise (EMI (Electro Magnetic Interference) noise) radiated from the electronic devices tends to increase.

  Here, a spread spectrum clock generator (SSCG) is known as means for suppressing electromagnetic wave noise (see, for example, Non-Patent Document 1). Spread spectrum refers to periodically changing the frequency of a basic clock generated by a crystal resonator or the like with a predetermined profile (referred to as a frequency modulation profile). Since the frequency of the electromagnetic noise is dispersed by this, the peak level of the electromagnetic noise can be kept small.

  As a spread spectrum clock generator system, there are an analog system using a PLL (Phase Locked Loop) circuit and a digital system using a delay circuit (delay line).

  FIG. 3 is a diagram showing a circuit configuration of a conventional spread spectrum clock generator using a digital method.

  A spread spectrum clock generator 100 shown in FIG. 3 is a spread spectrum clock generator that generates a spread spectrum clock (referred to as modulation CLK) whose frequency periodically varies from a clock CLK having a constant frequency.

  The spread spectrum clock generator 100 includes a delay circuit 10 in which a plurality of delay cells (unit delay elements) 11 that output an input clock CLK by delaying the input clock CLK by a unit delay amount (dt) are connected in series. . Each of the plurality of delay cells 11 includes two 2-input NAND gates 11_1 and 11_2. The empty pins of the 2-input NAND gates 11_1 and 11_2 are fixed to the “H” level.

  The spread spectrum clock generator 100 is provided with eight clock input circuits 20_0, 20_1,..., 20_7 for inputting the clock CLK from the eight input ports on the delay circuit 10 to the delay circuit 10.

  Further, the spread spectrum clock generator 100 is provided with a two-input NAND gate 30 for outputting the modulation CLK from the spread spectrum clock generator 100.

  In the spread spectrum clock generator 100, when the clock CLK is input to the delay circuit 10, the clock input circuits 20_0, 20_1,. Specifically, each of the clock input circuits 20_0, 20_1,..., 20_7 includes a two-input NAND gate, and the clock CLK is commonly input to one of the two-input NAND gates. The selection signals SEL0 to SEL7 are input to the other of these two-input NAND gates. These selection signals SEL0 to SEL7 are sequentially set to the ‘H’ level, whereby the clock input circuits 20_0, 20_1,..., 20_7 are sequentially selected.

  FIG. 4 is a diagram showing the entrance of the delay circuit selected with the cycle of the clock CLK and the delay time increasing / decreasing along with the delay time and the period of the modulation CLK of the spread spectrum clock generator shown in FIG. It is a figure which shows the waveform of CLK.

  FIG. 4 shows the cycle of the clock CLK, the entrance of the delay circuit 10 corresponding to the selection signals SEL0 to SEL7, the delay time until the clock CLK input to the entrance reaches the exit, the modulation CLK The period is shown.

  In the spread spectrum clock generator 100, the entrance of the delay circuit 10 is selected and the clock CLK is input as shown in FIG. 4 in synchronization with the cycle of the clock CLK. Specifically, the clock input circuits 20_0, 20_1, ..., 20_7, 20_7, 20_6, ..., 20_0 are selected in this order, and the clock CLK is input to the delay circuit 10. Here, the number of the delay cells 11 constituting the delay circuit 10 between the clock input circuits 20_0 and 20_1 is one, and the number of the delay cells 11 between the clock input circuits 20_1 and 20_2 is two. The number of delay cells 11 between the clock input circuits 20_2 and 20_3 is three, and the number of delay cells 11 between the clock input circuits 20_3 and 20_4 is four. Further, the number of delay cells 11 between the clock input circuits 20_4 and 20_5 is three, the number of delay cells 11 between the clock input circuits 20_5 and 20_6 is two, and the number of the delay cells 11 between the clock input circuits 20_6 and 20_7. The number is one.

As described above, since the number of delay cells 11 is different corresponding to each selected entrance, when the entrance of the delay circuit 10 is selected in the order shown in FIG. 4, the input is made as shown in FIG. The delay time until the clock CLK reaches the exit changes. As a result, the period of the modulation CLK increases or decreases, and the waveform of the modulation CLK becomes a waveform whose period slightly increases or decreases as shown in FIG. In this way, by periodically increasing or decreasing the frequency of the clock CLK, the frequency of the electromagnetic noise can be dispersed and the peak level of the electromagnetic noise can be kept small.
Fujitsu Limited; FUJITSU ELECTRONIC DVICES NEWS (FIND Vol. 21, No. 4, 2003)

  Here, the degree of increase / decrease in the period of the clock CLK (± 0 to ± 4 dt in FIGS. 4 and 5) is referred to as a modulation degree (modulation depth) as a ratio to the period. When the modulation degree is deep, in general, the effect of noise reduction is large, but on the other hand, the cycle of the shortest clock CLK is shortened, so that a circuit operating with the clock CLK is required to operate at high speed. For this reason, the modulation degree is often selected as an appropriate value for each circuit while taking into account both the noise reduction effect and the normal operation of the circuit.

  In order to realize different modulation degrees in a digital spread spectrum clock generator, a spread spectrum clock generator described below is employed.

  FIG. 6 is a diagram showing a circuit configuration of a conventional spread spectrum clock generator different from FIG.

  The spread spectrum clock generator 200 shown in FIG. 6 differs from the spread spectrum clock generator 100 shown in FIG. 3 in that the clock input circuits 20_6 and 20_7 are reduced. Further, the number of delay cells 11 between the clock input circuits 20_3 and 20_4 is changed from four to two, and the number of delay cells 11 between the clock input circuits 20_4 and 20_5 is changed from three to one. Is different.

  FIG. 7 is a diagram showing the entrance of the delay circuit selected with the cycle of the clock CLK, the delay time increasing / decreasing along with the delay cycle, and the period of the modulation CLK of the spread spectrum clock generator shown in FIG.

  In the spread spectrum clock generator 200, when the clock CLK is input to the delay circuit 10, the clock input circuits 20_0, 20_1,..., 20_5, 20_5, 20_4,. By doing so, the spread spectrum clock generator 100 described above has a modulation degree of ± 4 dt as shown in FIGS. 4 and 5, but this spread spectrum clock generator 200 has a modulation degree as shown in FIG. Furthermore, the degree of modulation decreases to ± 3 dt.

  Now, in order to achieve both the deep modulation degree possessed by the spread spectrum clock generator 100 shown in FIG. 3 and the shallow modulation degree possessed by the spread spectrum clock generator 200 shown in FIG. The clock input circuit which is an entrance for inputting the clock CLK to the delay circuit 10 between the time of the above and the time of shallow modulation may be switched and used as shown below.

  FIG. 8 is a diagram showing a circuit configuration of a spread spectrum clock generator in which the clock input circuit is switched according to the deep modulation depth and the shallow modulation depth.

  The spread spectrum clock generator 300 shown in FIG. 8 includes clock input circuits 20_0, 20_1, 20_2, and 20_3 using two-input NAND gates, and clock input circuits 40_1, 40_2, 40_3, and 40_4 using three-input NAND gates. , 40_5, 40_6. Further, inverters 41 and 42 are provided for generating a mode signal MODE_0 for a deep modulation degree (deep) and a mode signal MODE_1 for a shallow modulation degree (shallow).

  In the spread spectrum clock generator 300, the mode signal MODE_0 is set to the “H” level in order to realize a deep modulation degree. Next, the clock input circuits 20_0, 20_1, 20_2, 20_3, 40_3, 40_4, 40_5, and 40_6 are selected in this order. As a result, the spread spectrum clock generator 100 shown in FIG. 3 is realized. On the other hand, in order to realize a shallow modulation degree, the mode signal MODE_1 is set to the ‘H’ level and the clock input circuits 20_0, 20_1, 20_2, 20_3, 40_1, and 40_2 are selected in this order. As a result, the spread spectrum clock generator 200 shown in FIG. 6 is realized. In this way, the delay cell 11 can also be used to achieve both a deep modulation degree and a shallow modulation degree.

  However, in the spread spectrum clock generator 300, the clock input circuits 20_0, 20_1, 20_2, and 20_3 using two-input NAND gates and the clock input circuits 40_1, 40_2, 40_3, 40_4, and 40_5 using three-input NAND gates are used. , 40_6. For this reason, there exists a problem that a circuit structure is complicated and there are many elements.

  Here, for the sake of simplicity, two examples of modulation degrees have been described, but in general, a spread spectrum clock generator capable of selecting three or more modulation degrees is required. Furthermore, although the example in which the number of stages of the delay cells 11 is simplified to 16 has been described here, the delay circuit 10 is configured by using several hundred stages of delay cells 11 in practice. Therefore, in order to actually cope with a plurality of modulation degrees, there is a problem that the circuit configuration is complicated and the circuit scale is increased.

  In view of the above circumstances, an object of the present invention is to provide a spread spectrum clock generator capable of supporting a plurality of modulation degrees while suppressing an increase in circuit scale with a simple circuit configuration.

The spread spectrum clock generator of the present invention that achieves the above object is a spread spectrum clock generator that generates a spread spectrum clock whose frequency periodically varies from a constant frequency clock.
A delay circuit in which a plurality of delay cells that output an input clock by delaying by a unit delay amount are connected in series;
A plurality of clock input circuits for inputting clocks to the delay circuit from a plurality of input ports on the delay circuit;
In response to the mode switching signal, in the first mode, the clock propagated from the upstream side of the clock propagation of the delay circuit to the first point in the middle of the delay circuit is the delay cell immediately downstream of the first point. In the second mode, the clock that has propagated to the first point is bypassed in the middle of the delay circuit, and the second point of the delay circuit on the downstream side of the clock propagation of the delay circuit is bypassed. And a bypass circuit for inputting to the delay cell.

  The present invention has been devised by paying attention to the following viewpoints. A specific example will be described. For example, the number of delay cells 11 between the clock input circuits 20_5, 20_6, and 20_7 of the spread spectrum clock generator 100 that realizes the deep modulation degree shown in FIG. 3 and the spectrum that realizes the shallow modulation degree shown in FIG. Attention is paid to the number of delay cells 11 between the clock input circuits 20_3, 20_4, and 20_5 of the diffusion clock generator 200. In the clock input circuits 20_5, 20_6, and 20_7 shown in FIG. 3 and the clock input circuits 20_3, 20_4, and 20_5 shown in FIG. 6, the number of delay cells 11 through which the clock CLK passes to the exit of the delay circuit 10 is different. The relationship between the clock input circuits shown in FIGS. 3 and 6 is the same. That is, the number of delay cells 11 between these clock input circuits is the same (here, three). Therefore, as shown in an embodiment described later, a bypass circuit according to the present invention is provided between the clock input circuit 20_2 and the clock input circuit 20_5 of the spread spectrum clock generator 100 that realizes the deep modulation degree shown in FIG. Even when the spread spectrum clock generator 100 that realizes a deep modulation degree is used, the number of delay cells 11 to the exit is the same as that when the spread spectrum clock generator 200 that realizes a shallow modulation degree shown in FIG. 6 is used. The clock CLK is bypassed. In this way, by providing a bypass circuit in the middle of the delay circuit 10 and enabling the function of the bypass circuit in the case of a shallow modulation degree, the number of delay cells 11 through which the clock CLK passes is reduced, so that FIG. The spread spectrum clock generator 300 shown in FIG. 3 does not require a clock input circuit using a three-input NAND gate, and can support a plurality of modulation degrees with a simple circuit configuration while suppressing an increase in circuit scale. A spread spectrum clock generator can be provided.

  Here, the first mode and the second mode are the input ports upstream of the first point of the delay circuit in both the first mode and the second mode. Preferably, the mode is one in which at least one of the input ports is also used to generate spread spectrum clocks having different frequency fluctuation ranges.

  In this way, it is possible to cope with a plurality of modulation degrees while suppressing an increase in circuit scale with a simple circuit configuration, and it is possible to freely adjust the plurality of modulation degrees.

  According to the spread spectrum clock generator of the present invention, it is possible to cope with a plurality of modulation degrees while suppressing an increase in circuit scale with a simple circuit configuration.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a circuit configuration of a spread spectrum clock generator according to an embodiment of the present invention.

  The same components as those of the spread spectrum clock generator 100 shown in FIG. 3 described above are denoted by the same reference numerals, and different points will be described.

  The spread spectrum clock generator 1 shown in FIG. 1 is different from the spread spectrum clock generator 100 shown in FIG. 3 in that a bypass circuit 4 including a two-input NAND gate 2 and an inverter 3 is added.

  In the first mode, which is a mode for a deep modulation degree (deep), the bypass circuit 4 is in the middle of the delay circuit 10 from the upstream side of the propagation of the clock CLK of the delay circuit 10 according to the mode switching signal Mode. The clock CLK propagated to the first point P1 is transmitted to the delay cell 11 immediately downstream of the first point P1. On the other hand, in the second mode, which is a shallow modulation mode, the clock CLK propagated to the first point P1 is bypassed in the middle of the delay circuit 10 and the first point of the delay circuit 10 is bypassed. The signal is input to the delay cell 11 at the second point P2 downstream of the propagation of the clock CLK from P1.

  Here, the first mode and the second mode are both the first mode and the second mode, and the clock input circuit 20_5 that is an input port upstream of the first point P1 of the delay circuit 10 is used. , 20_6, and 20_7 are combined to generate a modulation CLK that is a spread spectrum clock having different frequency fluctuation ranges.

  In the spread spectrum clock generator 1 configured as described above, the first mode is set in order to realize a deep modulation degree. Specifically, the mode switching signal Mode is set to ‘L’ level (logic 0). Then, 'L' is input to both the 2-input NAND gate 2 and the inverter 3 constituting the bypass circuit 4. Accordingly, the “H” level is output from both the 2-input NAND gate 2 and the inverter 3. Therefore, the circuit configuration of the spread spectrum clock generator 100 shown in FIG. 3 described above is achieved, and a deep modulation degree (± 4 dt) can be realized.

  On the other hand, the second mode is set to realize a shallow modulation depth. Specifically, the mode switching signal Mode is set to the “H” level (logic 1). Then, 'H' is input to one of the two-input NAND gates 2 constituting the bypass circuit 4 and the inverter 3. As a result, the inverter 3 outputs the ‘L’ level, and the ‘L’ level is input to the delay cell 11 at the first point P1. Therefore, the propagation of the clock CLK to the delay cell 11 downstream of the delay cell 11 at the first point P1 is stopped. Further, the 'H' level is input to one of the two-input NAND gate 2, and the clock CLK from the delay cell 11 at the first point P1 is input to the other of the two-input NAND gate 2. For this reason, the clock CLK from the delay cell 11 at the first point P1 is bypassed and input to the delay cell 11 at the second point P2. Therefore, the circuit configuration of the spread spectrum clock generator 200 shown in FIG. Thus, a shallow modulation degree (± 3 dt) can be realized. As described above, in the spread spectrum clock generator 1 of the present embodiment, an equivalent short delay circuit 10 for realizing a shallow modulation degree can be obtained simply by providing a simple bypass circuit 4 including a two-input NAND gate 2 and an inverter 3. Can be realized.

  FIG. 2 is a diagram showing the entrance of the delay circuit selected with the cycle of the clock CLK, the delay time increasing / decreasing with the delay circuit, and the period of the modulation CLK of the spread spectrum clock generator shown in FIG.

  In FIG. 2, the cycle of the clock CLK, the entrance of the delay circuit corresponding to the selection signals SEL0 to SEL7, the delay time until the clock CLK input to the entrance reaches the exit, the modulation CLK The period is shown.

  In the spread spectrum clock generator 1 of the present embodiment, the order of the entrances to be selected of the delay circuit 10 is changed due to the difference in modulation degree. That is, the order of the clock input circuits 20_0, 20_1,. This changes the operation of a counter (not shown) that determines the order of the clock input circuits 20_0, 20_1,. Specifically, both the operation in the selection order and the operation in the selection order shown in FIG. 2 in the spread spectrum clock generator 100 realizing the deep modulation degree shown in FIG. 4 are switched according to the level of the mode switching signal Mode. In other words, an anomalous counter that operates “slow” is required. Such an irregular counter generally has a more complicated configuration than a counter that simply performs operations in the selection order shown in FIG. 4, but the difference is slight.

  For example, as a practical example, in the case of a spread spectrum clock generator that has several hundred stages of delay cells and operates at a cycle of about 100 cycles, the operation can be controlled by a 7-bit counter. Even if the operation is switched by the mode switching signal Mode, since it is a 7-bit irregular counter, it can be realized by adding several tens of gates at most. On the other hand, compared with the fact that the circuit configuration is simplified and the circuit scale is reduced by making the entrance of the delay circuit having hundreds of delay cells connected in common, the increase in the circuit scale of the counter is better. It is clear that it is much smaller.

  In the spread spectrum clock generator 1 of the present embodiment, the bypass circuit 4 is installed only at one place in the delay circuit 10 to realize the delay circuit 10 having two lengths to cope with two kinds of modulation degrees. However, if more bypass circuits are installed, more modulation degrees can be dealt with. In that case, the increase in circuit scale is slight, and a more efficient delay circuit can be obtained.

It is a figure which shows the circuit structure of the spread spectrum clock generator of one Embodiment of this invention. FIG. 2 is a diagram illustrating an entrance of a delay circuit selected along with a cycle of a clock CLK, a delay time that increases / decreases accordingly, and a period of a modulation CLK of the spread spectrum clock generator illustrated in FIG. 1. It is a figure which shows the circuit structure of the conventional spread spectrum clock generator by a digital system. FIG. 4 is a diagram illustrating an entrance of a delay circuit selected along with a cycle of a clock CLK, a delay time that increases / decreases accordingly, and a period of a modulation CLK of the spread spectrum clock generator illustrated in FIG. 3. It is a figure which shows the waveform of modulation | alteration CLK. It is a figure which shows the circuit structure of the conventional spread spectrum clock generator different from FIG. FIG. 7 is a diagram showing the entrance of a delay circuit selected with the cycle of the clock CLK, the delay time increasing / decreasing with the delay circuit, and the period of the modulation CLK of the spread spectrum clock generator shown in FIG. 6. It is a figure which shows the circuit structure of the spread spectrum clock generator by which a clock input circuit is switched according to a deep modulation degree and a shallow modulation degree.

Explanation of symbols

1, 100, 200, 300 Spread spectrum clock generator 2, 11_1, 11_2, 30 2-input NAND gate 3, 41, 42 Inverter 4 Bypass circuit 10 Delay circuit 11 Delay cell 20_0, 20_1, ..., 20_7 Clock input circuit 40_1, 40_2 , ..., 40_6 3-input NAND gate

Claims (2)

In a spread spectrum clock generator that generates a spread spectrum clock whose frequency periodically varies from a constant frequency clock,
A delay circuit in which a plurality of delay cells that output an input clock by delaying by a unit delay amount are connected in series;
A plurality of clock input circuits for inputting clocks to the delay circuit from a plurality of input ports on the delay circuit;
In response to the mode switching signal, in the first mode, the clock propagated from the upstream side of the delay circuit to the first point in the middle of the delay circuit in the delay circuit is the delay cell immediately downstream of the first point. In the second mode, the clock that has propagated to the first point is bypassed in the middle of the delay circuit, and the second point of the delay circuit on the downstream side of the clock propagation of the delay circuit is bypassed. A spread spectrum clock generator comprising a bypass circuit for inputting to a delay cell.   The first mode and the second mode are at least one of the input ports upstream of the first point of the delay circuit in both the first mode and the second mode. 2. The spread spectrum clock generator according to claim 1, wherein the spread spectrum clock generator is a mode in which two input ports are also used to generate spread spectrum clocks having different frequency fluctuation ranges.

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