JPH0349417A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To always apply prescribed delay time without being affected by the capacity of a loading circuit to be applied to an output, surrounding temperature or power supply voltage, etc., by switching the delay time according to time difference between the output signal of an output buffer circuit and the output signal of a reference delay time setting circuit. CONSTITUTION:A circuit 1 is provided to set the reference delay time to an input signal IN and a circuit 2 is provided to switch the plural kinds of the delay time. Then, one kind of the delay time is selected from the plural kinds of the delay time corresponding to the time difference between this circuit 1 to set the reference delay time and an output OUT of a semiconductor integrated circuit. Accordingly, even when an environmental condition such as the capacity of the loading circuit to be applied to the output, surrounding temperature or power supply voltage, etc., is changed, the constant delay time can be always applied. Thus, it is not necessary to fit the other circuit to the external part of the semiconductor integrated circuit for adjusting the delay time and simultaneously, even in the case that width between the minimum standard and maximum standard of the output delay time is made wide, these kinds of the delay time can be set.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit designed so that the delay time of an output signal is constant.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit includes inverters I31 . It has an output buffer circuit 3A with inverters I32, and input signals IN are connected to inverters I31. I3
2, the signal is given a predetermined delay time and is output as an output signal OUT to the outside of the semiconductor integrated circuit.

[Problem to be solved by the invention]

The conventional semiconductor integrated circuit described above has an output buffer circuit 3.
Inverter I31. Since the delay time is set by I32, the delay time changes significantly depending on the capacity of the load circuit added to the output and environmental conditions such as ambient temperature and power supply voltage. In particular, it is difficult to design an output buffer circuit that satisfies the minimum and maximum delay time specifications at the same time.Moreover, since the width of the minimum and maximum specifications becomes wide, a separate circuit is required outside the semiconductor integrated circuit to adjust this width. The disadvantage is that a circuit must be provided.

The purpose of the present invention is to eliminate the need for an external adjustment circuit and to always provide a predetermined delay time without being affected by the capacity of the load circuit added to the output, ambient temperature, power supply voltage, etc. Our goal is to provide semiconductor integrated circuits that can.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a reference delay time setting circuit that gives an input signal a predetermined delay time and outputs it, and generates a plurality of signals each having a different delay time with respect to the input signal, and switches these signals by a switching signal. a delay time switching circuit that selects and outputs one of the delay time switching circuits, an output buffer circuit that transmits the output signal of the delay time switching circuit to the outside, and an output signal of the output buffer circuit for the input signal and the reference delay time setting. and a delay time switching control circuit that detects a time difference with the output signal of the circuit and outputs the switching signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

This embodiment includes inverters t and r2, and an input signal I
A reference delay time setting circuit 1 for giving and outputting a predetermined delay time to N, a plurality of inverters 3 and 4 and transfer gates T, T2 each having a different delay time for the input signal IN (this embodiment The delay time switching circuit 2 generates two signals (D, F) and selects and outputs one of these signals using the switching signal (D, F), and the inverter I5.
．． An output buffer circuit 3 comprising I6 and transmitting the output signal of the delay time switching circuit 2 to the outside as an output signal OUT, and an output buffer circuit i13 comprising gate circuits G1 to G4 and inverters I, , I for input signal IN. The output signal OUT of the reference delay time setting circuit 1 and the output signal (B
) and a delay time switching control circuit 4 that detects the time difference between the delay time switching signal (D, F) and outputs a switching signal (D, F).

Next, the operation of this embodiment will be explained.

FIG. 2 is a timing chart of signals of various parts for explaining the operation of this embodiment.

The signal input IN is inputted to the output buffer circuit 3 through the delay time switching circuit 2, and the output signal OU of the semiconductor integrated circuit is inputted to the output buffer circuit 3.
It is transmitted to the outside as T. At the same time, the signal input IN is input to the reference delay time setting circuit 1, and a signal delayed by a certain period of time is output to the output line B.

The output signal OUT is the output signal of the reference delay time setting circuit 1 (
B) If it is transmitted earlier (period t1 in Figure 2)
, the output signal (D) of the delay time switching control circuit 4 is L 11
level, the output signal (F) becomes "H'" level, the transfer gate T of the delay time switching circuit 2 turns off, and the transfer gate T2 turns on, and the input signal IN
The signals delayed by inverters I, I4 are input to the output buffer circuit 3, and the output signals OU and T are delayed.

Further, when the output signal OUT is transmitted later than the output signal (B) of the reference delay time setting circuit 1 (period t2 in FIG. 2), the output signal (D) of the delay time switching control circuit 4 becomes "H".
11 level, the output signal (F) becomes the "'L'° level, the transfer gate T1 of the delay time switching circuit 2 is turned on, the transfer gate T2 is turned off, and the output signal (F) is turned on.
UT will be faster.

Although this embodiment shows an example in which the present invention is applied to an output circuit, it can also be applied to other circuits of semiconductor integrated circuits.

〔Effect of the invention〕

As explained above, the present invention provides a circuit for setting a reference delay time and a circuit for switching a plurality of delay times for an input signal, and provides an output signal of the circuit for setting the reference delay time and an output signal of a semiconductor integrated circuit. By selecting one of multiple delay times according to the time difference between the This eliminates the need to install a separate circuit outside the semiconductor integrated circuit to adjust the delay time, and at the same time meets the minimum output delay time standard.

This has the advantage that even if the maximum standard range is wide, it can be set.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a timing diagram of signals of various parts for explaining the operation of the embodiment shown in the figure. FIG. 3 is a circuit diagram showing an example of a conventional semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1... Reference delay time setting circuit, 2... Delay time switching circuit, 3, 3A... Output buffer circuit, 4... Delay time switching control circuit, 01-G4... Gate circuit, I. ~'B, I31+ 132...Inverter, T,
, T2...transfer gate.

Claims (1)

[Claims] A reference delay time setting circuit that gives and outputs a predetermined delay time to an input signal, generates a plurality of signals each having a different delay time for the input signal, selects one of these signals by a switching signal, and outputs it. an output buffer circuit that transmits an output signal of the delay time switching circuit to the outside; and a time difference between the output signal of the output buffer circuit and the output signal of the reference delay time setting circuit in response to the input signal. A semiconductor integrated circuit comprising: a delay time switching control circuit that detects and outputs the switching signal.