JPH1197990A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain fine delay application less than the propagation delay amounts of a logical circuit element without using any analog circuit element by providing an opening and closing gate for preventing the passage of an input pulse signal at one logical circuit element. SOLUTION: An AND gate 4 is gate opened and closed according to the setting condition of a register 10. Propagation delay amounts Tpd2 at the AND gate 4 side are made larger than propagation delay amounts Tpd1 at a buffer 3 side. When the AND gate 4 is closed, a pulse at a path 1 side only is outputted, and an output pulse with delay amounts Tpd1+Tpd3 obtained by the buffer 3 and the OR gate 6 is outputted. When the gate of the AND gate 4 is opened, an output pulse is obtained by OR adding the both pulse signals with the delay amounts Tpd1 obtained by the buffer 3 and the delay amounts Tpd2 obtained by the AND gate 4 by an OR gate 6. The pulse width of the output pulse can be widened, and the tail position of the pulse can be the output pulse delay-increased only for the delay amounts Tpd2-Tpd1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit capable of providing a minute delay having a delay resolution less than a propagation delay amount of a logic circuit element.

[0002]

2. Description of the Related Art Generally, a variable delay circuit realizes a desired variable amount of a variable delay circuit by serially connecting a plurality of sets of variable delay circuits. This variable delay circuit is usually integrated into an LSI and put to practical use. A first example of a set of variable delay circuits in the prior art includes three serially connected delay buffers as shown in FIG. 5 and a delay selector unit for switching paths. This will be described with reference to the timing chart of FIG. Here, each delay amount of the delay buffer is Tpd1, and A
Let the delay amount of the ND gate be Tpd2 and each delay amount of the OR gate be Tpd3.

[0003] The delay selector section has a configuration example of a register 10, two AND gates and an OR gate. Register 1
Numeral 0 denotes one flip-flop for externally setting the delay amount to be variable. The positive and negative output terminals are connected to one ends of both AND gates, and only the pulse signal of one of the AND gates is output. . The other end of each of the AND gates receives the input pulse as it is on path 1 and receives the input pulse on path 2 as a delay pulse delayed by three serially connected delay buffers. One of the pulse signals in these two paths is selected and output from the output terminal of the OR gate.

This will be described with reference to the timing chart of FIG. By applying the input pulse shown in FIG. 6A, the delay amount of the output pulse (FIG. 6B) by the path 1 is Tpd2 + Tp
d3, and the delay amount of the output pulse (FIG. 6C) by the path 2 is 3 × Tpd1 + Tpd2 + Tpd3. Here, the position defining the delay amount in FIG. 6 is the trailing edge position of the pulse. As a result, the variable delay amount obtained by setting the register is obtained as 3 × Tpd1, which is a delay amount by three delay buffers, and is a delay amount that can be changed from the outside. The variable delay amount according to the above configuration is an example of a variable delay circuit applied when the propagation delay amount of a logic circuit element is used as a unit. By the way, the propagation delay of a basic logic circuit element integrated in an LSI is, for example, on the order of several tens of psec, although it depends on the thing. For this reason, a variable delay amount smaller than this needs to be realized by other constituent means.

Next, an example of a minute variable delay circuit which is smaller than the propagation delay amount of the logic circuit element will be described with reference to FIG. As a second example of a set of variable delay circuits in the prior art, as shown in FIG. 7, two inverters are connected in series, and three capacitors each having a control switch connected in series at the output terminal of the first stage inverter are provided. The switch is selectively controlled by a 3-bit register 11 which can be controlled from the outside. This is an example in which output can be performed with a desired minute delay amount. This will be described with reference to the timing chart of FIG. In this circuit, the output impedance of the first-stage inverter, the ON resistance of the control switch, and the capacitor connected to it form an integration time constant, and the capacitance value of the connected capacitor is switched by the control switch, so that the next-stage inverter input terminal The method uses an integration time required for a transition up to the threshold voltage of the threshold voltage. Thus, a variable delay circuit capable of changing a minute delay amount is provided.

However, the circuit using the capacitors and switches shown in FIG. 7 has a problem in LSI integration. That is, there is a disadvantage that the ON resistance of the control switch greatly varies depending on the temperature, and there is also a problem that the jitter is easily generated due to the influence of the interference of the power supply voltage and the adjacent pulse due to the CR integration circuit. From these points, it is not preferable in a device that requires stability of delay amount setting, low jitter, or high accuracy.

[0007]

As described above, when an attempt is made to integrate a variable delay circuit with a small delay amount into an LSI, the prior art is not preferable from the viewpoints of temperature change, jitter, power supply fluctuation and the like. There are practical difficulties. Accordingly, an object of the present invention is to provide a variable delay circuit capable of providing a minute delay less than the propagation delay amount of a logic circuit element without using an analog circuit element.

[0008]

According to an embodiment of the present invention, there is provided an input pulse signal to both input terminals of a first logic circuit element and a second logic circuit element having different amounts of propagation delay between input and output. , And one of the second logic circuit elements is provided with an opening / closing gate (for example, an AND gate) for blocking the passage of the input pulse signal, and a logical sum of the two delayed pulse signals having different propagation delay amounts passed through the two logic circuit elements This is a configuration means for outputting the result. According to the above invention, it is possible to realize a variable delay circuit capable of providing a minute delay less than the propagation delay amount of a logic circuit element without using an analog circuit element.

FIG. 1 and FIG. 2 show a solution according to the present invention. The invention configuration for solving the above-mentioned problems is as follows.
First delay means and second delay means having different propagation delay amounts between input and output (for example, buffers, AND gates, inverters, NAND gates, and circuit elements such as high-speed, medium-speed, and low-speed cells for changing the cell forming conditions on LSI). The same input pulse signal is applied to both input terminals of the first delay means, and the input pulse signal input to one of the paths of the first delay means passes through the delay amount of the first delay means and is output. For example, a buffer 3) is provided, and a control terminal is provided for controlling the gate opening / closing by a register 10 for setting the passage of the input pulse signal. The input pulse signal input to the other path of the second delay means is controlled by the control signal. A second delay means (for example, an AND gate 4) for preventing passage or outputting the signal as it is by a terminal is provided, and the signal is delayed by passing through both the first delay means and the second delay means In response to both the delay pulse signal, means for outputting both signals by a logical sum (e.g. OR gate 6)
There is a variable delay circuit comprising: As a result, the output pulse can be output with a minute delay amount variable with respect to the trailing edge position or the leading edge position. According to the above invention, a variable delay circuit having a small delay amount less than the propagation delay amount of the logic circuit element can be realized.

Further, there is the above-mentioned variable delay circuit which operates with a positive pulse signal or a negative pulse signal as an input pulse signal. Further, there is a variable delay circuit in which the configuration of the above-described variable delay circuit has a plurality of stages connected in series. Further, as one or both of the first delay means and the second delay means having different propagation delay amounts between the input and output, a delay which is a propagation delay amount of a single circuit element or a propagation delay amount of a plurality of circuit elements connected in series is used. There are means.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

The present invention will be described with reference to a configuration example of a set of variable delay circuits in FIG. 1 and a timing chart in FIG. One configuration example of the variable delay circuit includes a buffer 3, an AND gate 4, an OR gate 6, and a register 10, as shown in FIG. Here, it is assumed that the propagation delay amount Tpd2 on the AND gate 4 side which is a logic circuit element is larger than the propagation delay amount Tpd1 on the buffer 3 side. The position that defines the delay amount is the trailing edge position of the pulse. Here, as the logic circuit element, there are, for example, a buffer, an inverter, an AND gate, a NAND gate, an OR gate, a NOR gate, and the like. Also, by changing the cell size and the driving ability of the same logic circuit element, macro cells having different propagation delays are possible. This is formed on an LSI chip.

The buffer 3 passes the input pulse signal as it is and outputs it as a delayed pulse signal to which the propagation delay amount Tpd1 has been added. The other AND gate 4
The gate is opened and closed according to the setting condition of the register 10, and when the gate is open, a delay pulse signal to which the propagation delay amount Tpd2 is added is output. The OR gate 6 performs an OR operation on the two delayed pulse signals and outputs the result.

This will be described with reference to FIG. The output pulse output by application of the input pulse shown in FIG.
First, when AND gate 4 is closed, path 1
Pulse is output from the buffer 3 and the OR gate 6
Output pulse of delay amount Tpd1 + Tpd3 due to delay (see FIG. 2C)
Is output. Second, when the gate of the AND gate 4 is open, both pulses on the path 1 and the path 2 are output, and both pulse signals of the delay amount Tpd1 by the buffer 3 and the delay amount Tpd2 by the AND gate 4 are output. OR gate 6
And an output pulse obtained by OR addition (see FIG. 2E). As a result, the output pulse has a wider pulse width, and the trailing edge position of the pulse becomes an output pulse whose delay is increased by the delay amount Tpd2-Tpd1 shown in FIG. 2E. From this, it can be seen that the minute delay amount Tpd2-Tpd1 of the difference between the two circuit elements can be variably controlled.

According to the invention described above, an input pulse is applied to two paths having different propagation delays, and an open / close gate for preventing passage of the applied pulse is provided on one of the paths.
By providing a means for ORing and outputting the signals of the two paths, the delay amount Tpd2−
Variable control of a small delay difference Tpd1 is possible. Therefore, there is obtained a great advantage that a variable delay circuit having a small delay amount can be realized without using an analog circuit element as in the related art.

In the description of the above embodiment, A shown in FIG.
Although it has been assumed that the propagation delay amount Tpd2 of the ND gate 4 is larger than the propagation delay amount Tpd1 of the buffer 3, either one may be used as long as the two delay amounts are not the same. However, whether the position defining the delay based on the difference between the two delay amounts is the trailing edge position or the leading edge position of the output pulse changes.
In addition, as shown in FIG.
N buffers 3 are connected in series, and one to N
Circuit elements having different propagation delays including the AND gates 4 may be connected in series so that a predetermined delay difference can be obtained between the two paths. As described above, by inserting circuit elements having different propagation delay amounts in combination so as to obtain a desired delay difference in the delay amount between the two paths, a minute variable delay amount different from that in FIG. Various types of propagation delays equal to or greater than the propagation delay of the element can be realized. The circuit element used at this time is not limited to the buffer or the AND gate, and may be configured by combining other circuit elements having different propagation delay amounts through which the pulse can pass.

Further, a circuit configuration using an inverting gate shown in FIG. 4 instead of the circuit of FIG.
It is clear that the same can be implemented. Further, in the above-described embodiment, a specific example has been described in which the trailing edge position of the output pulse is used as the position defining the delay amount. However, the delay amount may be defined at the leading edge position of the output pulse. In the above-described embodiment, a specific example in which a positive input pulse is applied has been described. However, in the case of a negative input pulse, as shown in FIG. It is clear from the above description that the present invention can be similarly implemented.

[0018]

According to the present invention, the following effects can be obtained from the above description. According to the configuration of the invention described above, 2
Apply input pulses to the paths with different propagation delays in the system,
An open / close gate for preventing passage of an applied pulse is provided on one of the paths, and a means for outputting a logical sum of signals on the two paths is provided, so that a delay amount Tpd2-Tpd1 of a difference between the two paths is obtained. The variable control of the minute delay difference can be performed. Therefore, a variable delay circuit having a minute delay amount can be realized without using an analog circuit element unlike the related art, so that the conventional difficulties associated with temperature changes, jitters, and power supply fluctuations can be significantly improved. There is a great advantage that integration is easy.

[Brief description of the drawings]

FIG. 1 is a configuration example of a variable delay circuit according to the present invention.

FIG. 2 is a timing chart of the configuration of FIG. 1 according to the present invention;

FIG. 3 is a configuration example of another variable delay circuit of the present invention.

FIG. 4 is a configuration example of another variable delay circuit of the present invention.

FIG. 5 is a configuration example of a conventional variable delay circuit.

6 is a timing chart of the conventional configuration of FIG. 5;

FIG. 7 is a configuration example of a conventional variable delay circuit with minute delay.

8 is a timing chart of the conventional configuration of FIG. 7;

FIG. 9 is a configuration example of another variable delay circuit of the present invention.

[Explanation of symbols]

 1, 2 path Tpd1 to Tpd3 propagation delay amount 3 buffer 4 AND gate 6 OR gate 10, 11 register

Claims (5)

[Claims] An input pulse signal is applied to both input terminals of a first logic circuit element and a second logic circuit element having different amounts of propagation delay between input and output, and the input signal is applied to one of the second logic circuit elements. A variable delay circuit comprising: an open / close gate for preventing passage of a pulse signal; and means for logically summing and outputting both delayed pulse signals passed through both logic circuit elements. 2. The same input pulse signal is applied to both input terminals of a first delay means and a second delay means having different propagation delay amounts between input and output, and the input pulse signal input to one of the paths is A first delay means for passing and outputting the delay amount of one delay means; and a control terminal for gate opening / closing control of the passage of the input pulse signal, and the input pulse signal input to the other path is controlled by the control terminal. Second delay means for preventing passage or outputting the signal as it is, and means for receiving both delayed pulse signals that have been delayed by passing through the two paths, and performing an OR operation on both signals to output the signals. Variable delay circuit. 3. The variable delay circuit according to claim 1, wherein the input pulse signal operates by applying a positive pulse signal or a negative pulse signal. 4. One or both of the first delay means and the second delay means having different propagation delay amounts between input and output are the propagation delay amounts of a single circuit element or a plurality of circuit elements connected in series. 3. A delay means according to claim 1 or 2,
A variable delay circuit as described. 5. The variable delay circuit according to claim 1, wherein the configuration of the variable delay circuit is a plurality of stages connected in series.