JPH0222577A - Waveform generating circuit - Google Patents

Abstract

PURPOSE:To test an IC which operates for several cycles in one test cycle by composing the waveform generating circuit of exclusive OR circuits, gate groups, a couple of variable delay elements, an FF, and multiplexers. CONSTITUTION:Pattern signals PA-PC are supplied to one-input-terminal sides of the exclusive OR circuits 2A-2C and control signals INA-INC for controlling whether or not the pattern signals PA-PC are inverted in logic are supplied to the other-input-terminal sides. Gate groups 3 and 4 are opened and closed according to the logical levels of pattern signals outputted from the exclusive OR circuits 2A-2C and 15A-15C to control the passage of clocks. The variable delay elements 7 and 8 pass the clocks outputted from gate groups 5 and 6 while delaying them. The FF 11 is set and reset with the outputs of the elements 7 and 8. The multiplexers 14A and 14B switch the state wherein the same pattern signal is supplied to the circuits 2A-2C and the state wherein the individual pattern signals are supplied. This constitution generates an optional number of pulses within the range of the number of the pattern signals.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a waveform generation circuit that can be used in an IC testing device that tests ICs such as memories.

"Prior Art" Figure 3 (= shows a conventional waveform generation circuit. Input terminal 1 (2 is No. 41gAl= As shown, a pattern signal PA having a Hibiki two-way logic "1" or "0" is given. This pattern Signal P
A is applied to one input terminal of each of the exclusive OR circuits 2A, 2B, and 2C.

The other input terminal +1 of the exclusive OR circuits 28 to 2C provides control signals INA, INB, and INC for controlling whether or not to invert the pattern signal PA.

That is, these control signals INA, INB, INCl:
When H logic is applied, the logic of pattern signal PA is inverted and output from exclusive OR circuits 2A, 2B, and 2C.

The exclusive OR circuits 2A, 2B, and 2C each have a non-inverting output terminal and an inverting output terminal, and the output of the non-inverting output terminal is input to one input terminal of each AND gate in the AND gate group 3. , the output of the inverted output terminal is AND gate group 4
is applied to one input terminal of each AND gate.

Control signals As, BS, C8, and AR, BR, CR are applied to the other input terminals of AND gate groups 3 and 4, respectively. The output of each AND gate in AND gate group 3 is given to one input terminal of each AND gate in AND gate group 5, and the output of the AND gate in AND gate group 4 is fed to the AND gate in AND gate group 6. Add 4 to one input terminal of the .

For each AND gate in AND gate groups 5 and 6,
, C, D+2 clocks CLA, CLB.

Give CLC.

The output of each AND gate of the AND gate groups 5 and 6 is passed through the skinny adjustment variable delay elements 7 and 8 to an OR circuit 9.
and 10 (two inputs), the logical sum is taken, and 4 is applied to the set terminal S and reset terminal R of the flip-flop 11.

Therefore, and gate groups 5 and 6 ant games) 5B and 6C
is open (when two clocks CLB and CLC are connected to the sector terminal S and reset terminal R of the flip-flop 11
4, the pulse PE shown in FIG. 4E (2) is generated,
This pulse PE passes through the driver 12 to the ICI under test.
given to one terminal of 3.

When the logic of each control signal is set as shown in FIG. 5 (2), the driver 12 outputs a signal having a waveform as shown in FIG.

In this way, signals with various waveforms can be generated by setting the two control signals, and the structure is such that the generated waveform can be selected depending on the type of ICI 3 to be tested, for example.

The above-described waveform generation circuit is provided corresponding to one terminal of the ICl 3 under test, and at least as many waveform generation circuits with such a configuration as there are terminals of the ICl 3 under test are provided.

``Problems to be Solved by the Invention'' Conventional waveform generation circuits have a drawback that they cannot generate a plurality of output signals PE even if a plurality of clocks CLA, CLB, and CLC are applied within the period of the pattern signal PA.

In other words, the maximum is the signal whose waveform shown in the 5th tBE1-th line gives the maximum change point.

Therefore, there is a drawback that the state of the ICI 3 under test cannot be changed over an arbitrary period within one test period.

"Means for Solving the Problem" In the present invention, a pattern signal is applied to one input terminal, and the other input terminal part: a plurality of input terminals to which a control signal for controlling whether or not to invert the logic of the pattern signal is applied. An exclusive OR circuit, a group of gates that are controlled to open and close according to the logic of the pattern signal output from this exclusive OR circuit, and which control the passage of clocks, and a time difference is created between the clocks output from this gate group. A pair of variable delay elements, a flip-flop whose set and reset are controlled by the output of this variable delay element, and a state where the same pattern signal is given to the exclusive OR circuit and a state where different pattern signals are given. The waveform generation circuit consists of a switching multiplexer and the following.

"Function" According to the structure of the present invention (according to 2), a multiplexer is provided at the front stage of the exclusive OR circuit, and the multiplexer allows pattern signals input to the exclusive OR circuit to be the same pattern signal, or to separate pattern signals from different pattern signals. I”- or can be switched.

According to this invention, if all the pattern signals are set to O logic (==) with different pattern signals being applied to all of the exclusive OR circuits, no pulse will be generated on the output side.

Also, if only one pattern signal has 1 logic (2), one pulse is output within the period of the pattern.

When two pattern signals are set to 1 logic, two pulses are output within the period of the pattern.

If all three pattern signals are set to 1 logic, three pulses can be output within the period of the pattern signal.

In this way (2) According to this invention: 2. Setting of pattern signal (
2, any number of pulses can be generated within the range of the number of pattern signals, and the state of the IC under test can be advanced an arbitrary number of times within one test cycle (2).

"Example" Figure 1 below shows an example of the present invention. In this invention, a multiplexer 14 is provided on the input side of the exclusive OR circuits 2B and 2C.
A and 14B are provided, and the multiplexers 14A and 14B are
switching (exclusive OR circuits 2A, 2B, 2C according to 2)
1. A state where two common pattern signals PA are given, and separate pattern signals PA, PB.

(Two configurations) so that the PC can be switched to the state of giving.

In other words, there are two input terminals IB in addition to input terminal IA.

An IC is provided, and pattern signals PA, PB, and PC are input to these input terminals IA, IB, and IC.

Input terminal IA1: The applied pattern signal PA is directly applied to one input terminal (2) of the two exclusive OR circuits, and is also manually applied to one input terminal A (2) of the multiplexers 14A and 14B.

Pattern signals PB and pc are applied from the input terminals IB and IC to the other input terminals B of the multiplexers 14A and 14B.

The control terminals S (2) of the multiplexers 14A, 14B provide a control signal CNT. When this control signal CNT is 0 logic, the input terminal A of the multiplexers 14A, 14B is connected to the output terminal Q (2). Therefore, in this state, exclusive A pattern signal PA is applied to all of the logical sum circuits 2A, 2B, and 2C.

On the other hand, when 1 logic is applied to the control terminals S of the multiplexers 14A and 14B, the multiplexer 14A.

14B is switched to a state in which input terminal B is connected to output terminal Q. In this state, the exclusive OR circuit 2A.

2B and 2C are switched to a state where pattern signals PA, PB, and PC are applied separately.

An exclusive OR circuit 15A is connected to each inverting output terminal of the exclusive OR circuits 2A, 2B, and 2C.

15B and 15C operate as inverters when the control signal CNT is 1 logic, and are designed to control each AND gate 1 of the AND gate group 4 so that the pattern signal given to it has the same polarity as the pattern signal given to the AND gate group 3. (There are two.

In addition, in this embodiment, the output side of the second AND gate group 5 and 6 (two direct OR circuits 9 and 10 are provided, and the OR circuits 9 and 10 obtain the OR of the three AND gates, respectively, and adjust the skew). In this case, the delay time of variable delay elements 7 and 8 is made to have a difference.In other words, the delay time of delay element 7 is set to τ1. , the delay time of delay element 8 τ
2, so that τ2−τ1=T (2τ2〉τ1
relationship (select).

In the above configuration, when the control signal CNT is set to O logic, the same pattern signal PA is applied to each exclusive OR circuit 2A, 2B, 2C, and the same operation as in the conventional circuit is performed.

If the control signal CNT is set to 1 logic 2 for this;
Exclusive OR circuits 2A, 2B, and 2C1 are supplied with separate pattern signals PA, PB, and PC.

Here, the control signal is INA=INB=INC=O.

When AS=BS=C8=1 and AR=BR=CR=IC, the period T1 shown in FIG. is output from.

The clock CLA output from the AND gate group 5 passes through the variable delay element 7 to the set terminal of the flip-flop 11.
: FSl two people are strong. Further, the clock CLA outputted from the AND gate group 6 is applied to the reset terminal R of the flip-flop tube 11 through the variable delay element 8.

Since the delay amounts of variable delay elements 7 and 8 have a time difference T, the clock CL A' applied to the reset terminal R is delayed by the time T with respect to the clock CLA applied to the set terminal S. . Therefore, flip-flop 1
1 outputs a pulse having a pulse width of the time difference T as shown in the second diagram.

As shown in the period C'-T2 in FIG. 2, the pattern signal PB
When only one logic is 1, the clock CLB is output from AND gate groups 5 and 6. For this reason, the flip-flop 11
outputs a pulse with a pulse width T at the phase position of the clock CLH.

Figure 2 (as shown by two T3 (two pattern signals PA and PB)
When is logic 1, clock C is output from AND gate groups 5 and 6.
LA and CLB are output. For this purpose, the flip-flop 11 outputs two pulses having a pulse width T at each timing of the clocks CLA and CLB.

Since the pattern signal PC is at logic 1 at T4 shown in FIG. Therefore, at this time, the flip-flop 11 outputs a pulse with a pulse width T at the timing of the clock CLC.

At T5 shown in FIG. 2, the pattern signals PA and PC are 1 logic. Therefore, in this case, 1 U is the and gate group 5
and 6 output clocks CLA and CLC. Therefore, in this case, the solve flop 11 outputs two pulses with a pulse width of T at the timing of the clocks CLA and CLC.

Furthermore, at T7 shown in FIG. 2, the pattern signals PA and PB.

Everything on the PC is 1 logic. Therefore, in this case (2), three pulses are output at each timing of each clock CLA, CLB, and CLC.

"Effects of the Invention" As explained above, according to the present invention, each logical value of the pattern signals PA, PB, and PC can be set appropriately:
Therefore, any number of rectangular waves that maximize the number of pattern signals can be generated. Therefore, it is possible to test an IC that operates for several cycles within one test cycle.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram for explaining one embodiment of the present invention,
FIG. 2 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 is a connection diagram for explaining the conventional technology.
FIGS. 4 and 5 are waveform diagrams for explaining the operation of the conventional technology. 2A, 2B, 2C: exclusive OR circuit, 3, 4: first AND gate group, 5, 6: second AND gate group, 7, 8:
Variable delay element, 11: Solitub flop. E 4 Figure

Claims (1)

[Claims] (1) A, a pattern signal is given to one input terminal,
A plurality of exclusive OR circuits, each of which is supplied with a signal for controlling whether or not to invert the logic of the pattern signal at the other input terminal; B. According to the logic of the pattern output from the exclusive OR circuits A group of gates that are controlled to open and close to control the passage of a clock; C. A pair of variable delay elements that allow the clock output from this gate group to pass with a time difference; D. Set and reset control by the output of the variable delay element. E, a multiplexer that switches between a state in which the same pattern signal is given to the exclusive OR circuit and a state in which different pattern signals are given to the exclusive OR circuit.