JPH01202916A - Pulse width adjusting circuit - Google Patents

Abstract

PURPOSE:To adjust freely the pulse width of an ultrahigh speed signal by ORing and ANDing an input pulse and a pulse being the result of retarding the pulse by a time delay element, generating two pulses with different width and selecting either of the two pulses by a selection circuit. CONSTITUTION:If a pulse width W1 of a waveform 1s given to an input terminal 1 is too wide, the pulse width W2 of a waveform 15s of an output 15 of an AND circuit 13 is made narrow by t41 with respect to the input waveform 1s, where t41 is the delay by a variable delay element 7. If the pulse width W1 inputted to the input terminal 1 is too narrow, the pulse width W2 of a waveform 16s of an output 15 of an OR circuit 14 is made narrow by t42 with respect to the input waveform 1s, where t42 is the delay by a variable delay element 8. Thus, optional pulse width is formed by selecting and outputting one of the signals 15s and 16s by the selection circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pulse width adjustment circuit suitable for use in a clock distribution circuit or the like in an information processing device.

(Prior art) A conventional pulse width adjustment circuit is disclosed in Japanese Patent Application No. 59-822.
There is No. 32 "Pulse Width Creation Circuit".

FIG. 4 is a circuit diagram showing the conventional pulse width adjustment circuit. This circuit is an AND circuit that outputs the logical product of two inputs.
A gate 42 , a gate 41 that takes and outputs the AND and NAND of two inputs, a delay element 43 , and an input terminal 4
4 and an output terminal 45.

FIG. 5 is a timing chart showing signals 46s to 50s of signal lines 46 to 50 in the conventional example shown in FIG.

The following explanation is all based on negative logic, and in order to simplify the explanation, it is assumed that there is no delay between elements. When the signal 468 shown in FIG. 5 is input to the signal line 46 via the input terminal 44, the signal 46S changes from logic "1" (hereinafter referred to as "1") to logic "0'° (hereinafter referred to as "0"). ), signal 4
7S goes from "0'" to "1" Signal 48S goes from 1" to "0"
The signal 49s changes to the signal 4 by the delay element 43.
It changes from "1" to "O" after 8 seconds. signal 50
s changes from "1'" to "OH" as the signal 47S changes from "0" to "1", or returns to "'1" again when the signal 49s changes from "1" to "0".Signal 46s
has returned to "1" before the signal 50s returns to "1", so when the signal 50s returns to "1", the output signal 47 becomes "0".
'', and a pulse width W is created.The conditions for this operation to be performed normally are that the period in which the signal 46S is 0 is guaranteed until the signal 50s changes to 0, and the period when the signal 50s is 1 is guaranteed. It changes to 1'' before returning to ''.

From the above explanation, it can be seen that the generated pulse width W is the sum of the delay time of the gate 41, the delay time of the gate 42, and the delay time of the delay element 43.

Therefore, by appropriately setting the delay time of the delay element 43, a desired pulse width W can be obtained.

(Problem to be Solved by the Invention) However, in the above-mentioned conventional pulse width adjustment circuit, it is difficult to create a pulse width that is less than the sum of the delays of the gates 41 and 42, the delays of the delay elements 43, and the wiring delays between these elements. Can not. Therefore, conventional pulse width adjustment circuits have not been able to obtain signals with a sufficiently narrow pulse width for use in ultrahigh-speed computers that require pulse widths of several nanoseconds.

(Means for Solving the Problems) Means provided by the present invention to solve the above-mentioned problems are as follows:
A pulse width adjustment circuit that inputs a pulse signal, adjusts the pulse width of the pulse signal, and outputs the adjusted pulse width, the circuit comprising first and second delay elements that respectively apply a time delay to the input pulse signal independently of each other; an AND circuit that generates an AND signal of an input pulse signal and an output signal of the first delay element; and an AND circuit that generates an OR signal of the input pulse signal and an output signal of the second delay element. The device includes an OR circuit, and a selection circuit that selects and outputs either the output signal of the AND circuit or the output signal of the OR circuit in accordance with a selection signal.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, including a pulse input terminal 1, a selection signal input terminal 2, and a pulse output terminal 18.
each terminal, driver circuits 3 to 6, variable delay element 7,
8, AND gate 13, OR gate 14, selection circuit 17
It consists of:

FIGS. 2 and 3 are timing diagrams of signals of various parts to explain the operation of the pulse width adjustment circuit shown in FIG. 1, and the pulse width adjustment operation in this embodiment will be explained using these diagrams. do. To simplify the explanation, it is assumed that there is no delay in any circuit other than the delay element.

Adjustment when the pulse @Wl of the waveform 1S input to the input terminal 1 is too wide will be explained using FIG. 2. AN
The waveform 9S input to one input of the D circuit 13 remains the input waveform 1S, and the waveform 105 delayed by the variable delay element 7 is input to the other input 10. If the delay due to variable delay element 7 is tdl, AND circuit 1
The waveform 15s of the output 15 of No. 3 is output with a pulse width W2 narrower by td1 than the input waveform 1S. That is, W2
= Wlt d+.

Pulse width W of waveform 1S input to input terminal 1.

The adjustment when the width is too narrow will be explained with reference to FIG. Waveform 1 input to one input 11 of OR circuit 14
13 is the input waveform 1S! There are up to L, and the other input 12
A waveform 12s delayed by the variable delay element 8 is input to the input signal. If the delay caused by the variable delay element 8 is td2, the waveform 16S of the output 16 of the OR circuit 14 is output with a pulse width W2 wider by t4□ than the input waveform 1S. That is, W 2 = W r + t a2.

Therefore, if you want to narrow the pulse width, the AND circuit 131
Adjust the pulse width of circuit 11 and use OR if you want to widen it.
By adjusting the pulse width of the circuit on the circuit 14 side and selecting and outputting one of the signals 15s and 16s using the selection circuit 17, an arbitrary pulse width can be created.

(Effects of the Invention) The pulse width adjustment circuit of the present invention takes the logical sum and logical product of an input pulse and a pulse delayed by a time delay element, generates two pulses with different widths, and selects these two pulses by a selection circuit. By selecting one of the two pulses, the pulse width of the ultrahigh-speed signal can be freely adjusted. As described above, according to the present invention, it is possible to provide a pulse width adjustment circuit that can arbitrarily adjust the pulse width of a pulse signal by selecting the delay time of the time delay element.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Figs. 2 and 3 are timing diagrams showing the time relationships of various signals in the embodiment of Fig. 1, and Fig. 4 is a conventional pulse width adjustment circuit. FIG. 5 is a timing chart showing the time relationship of signals of various parts in the conventional circuit of FIG. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Selection terminal, 3-6... Driver circuit, 7, 8... Variable delay element, 13...
AND circuit, 14...OR circuit, 17...selection circuit, 18...output terminal.

Claims (1)

[Claims] A pulse width adjustment circuit that inputs a pulse signal, adjusts the pulse width of the pulse signal, and outputs the pulse width, the circuit comprising: first and second delay elements that respectively give a time delay to the input pulse signal independently of each other; and the input pulse an AND circuit that generates a logical product signal of the signal and the output signal of the first delay element; and a logical sum circuit that generates a logical sum signal of the input pulse signal and the output signal of the second delay element. A pulse width adjustment circuit comprising: a circuit; and a selection circuit that selects and outputs either the output signal of the AND circuit or the output signal of the OR circuit according to a selection signal.