JPS60226210A - Pulse width forming circuit - Google Patents

Abstract

PURPOSE:To change the pulse width during operation by providing plural pulse width forming circuits and allowing a selection circuit to select the circuits. CONSTITUTION:A circuit consisting of gates 201, 202 and a delay circuit 205 is the 1st pulse width forming circuit, and a circuit comprising gates 201, 203 and a delay circuit 206 is the 2nd pulse forming circuit. These circuits are selected by an output of a gate 204 and when logical ''1'' is inputted as a selection signal on a signal line 214, the 1st pulse width forming circuit is selected and a pulse having a pulse width of the total W1 of delay times of the gates 201, 202 and the delay element 205 to an output line 208. On the other hand, when logical ''0'' is inputted as the selection signal, the 2nd pulse width forming circuit is selected, and a pulse having the pulse width of total W2 of delay times of the gates 201, 203 and the delay element 206 is outputted to the output line 208.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a pulse width generating circuit.

[Prior art]

FIG. 1 is a circuit diagram showing a conventional pulse width generation circuit.
This circuit includes an AND gate 102 that outputs the AND of two inputs, a gate 101 that outputs the AND of the two inputs, and a delay element 103, an input terminal 104, and an output terminal 105. It consists of Figure 2 (
&) to (e) are signal lines 106 to 110 in FIG. 1, respectively.
FIG. 4 is a timing diagram showing signals 106S to 110S of signals 106 to 110 of FIG.

The following explanation is all based on negative logic, and it is assumed that there is no delay between elements to simplify the explanation. The signal +[O6C Fig. 2 (a) K: Input signal 10 shown through the input terminal 104
The operation when 6S is input is that the signal 106S is logic '
1" (hereinafter referred to as 11") to logic 10" (hereinafter referred to as 10")
, the signal 107S changes from 10'' to 11'' and the signal 108S changes from ``1'' to 'O''. Signal 1098
is delayed by 11" from the signal 108S by the delay element 103.
The signal 110S changes from 11" to 10" due to the signal 107S changing from 10" to 11".
However, when the signal 109S changes from 11" to 10", it returns to 11" again. Signal 1068 is signal 11
Since 0S returns to '1' before returning to 11', the signal is 1.
When 10S returns to 11", the output signal 107S has a pulse width W of '0". The conditions for this operation to occur normally are that the period in which the input signal 106S is O'' is guaranteed until the signal 110S changes to '0'', and the signal 110S changes to '1'' before returning to 11''. That is what we are doing. From the above explanation, the pulse width W created by the gate 101 is as follows.

It can be seen that the delay time is the sum of the delay time of the gate 102 and the delay time of the delay element 103.

Therefore, by appropriately setting the delay time of the delay element 103, a desired pulse width W can be obtained.

However, once the pulse width W is set, the delay element 1
Since the pulse width cannot be changed other than by changing the delay amount of 03, there is a drawback that the pulse width cannot be changed during operation.

[Purpose of the invention]

SUMMARY OF THE INVENTION The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a pulse generation circuit which allows the pulse width to be changed during operation.

[Structure of the invention]

The circuit of the present invention includes a plurality of first circuits that have a plurality of input terminals and outputs a NAND of signals applied to these input terminals, and a selection signal that selects one of the plurality of first circuits. and a plurality of first input terminals to which respective outputs of the plurality of first circuits are input, and second input terminals to which input signals are input, respectively. a second circuit that outputs multiple NANDs and ANDs of signals applied to the input terminals and supplies the NAND output to the plurality of first circuits; and a second circuit provided in one-to-one correspondence with the plurality of first circuits, respectively. the second one having different delay times;
and a count delay circuit that delays the AND outputs of the circuits and supplies the delayed AND outputs to the plurality of first circuits.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing one embodiment of the present invention.

This embodiment has three input terminals, and two NA outputs the NAND e and the signals applied to these input terminals.
ND gates 202 and 203; and a gate 204 that selects one of the NAND gates 202 and 203 in response to a selection signal.

These input terminals have two first input terminals to which respective outputs of the gates 202 and 203 are input, and a second input terminal to which an input signal is input.

A gate 201 which outputs multiple NAND and logical products of signals applied to the gate and asks the gates 202 and 203 for the NAND output, and a gate 201 which is provided in one-to-one correspondence with the gates 202 and 203 and each has a different delay time. gate 202 by delaying the AND outputs of
and two delay elements 205 and 2 giving 203 K
06, and transmission lines 207-214 through which signals 207S-214S propagate, respectively.

Figure 4 (aJ to (h) are the signal lines 207 in Figure 3, respectively)
214 is a timing diagram showing signals of 208, 209, 210, 211, 212 and 213.

The operation of this embodiment will be explained with reference to FIGS. 3 and 4. First, the 1 selection signal 214S is 11" and the signal line 2
07 K The operation when the input signal 207S shown in FIG. 4 (&) is input will be explained. When the input signal 207S changes from 11" to 10", the output signal 208S changes to 10.
From "1" to "1", signals 209-IS and 209-28 change from &1" to '0". The signal 211S changes from 11# to 10'' with a delay from the signals 209-Is and 209-2S due to the delay element 205.
1", the output signal 212S of the gate 203 constantly becomes 11". Signal 213S is similar to signal 208S'
Due to the change from 0" to 11", 11" to 10
However, when the signal 211S changes from 11" to 10", it returns to 11" again. If the input signal 207S is input with consideration given to returning to 11" before the signal 213S returns to 1", the output signal 208S becomes 10" as the signal 213S returns to 11", and a pulse width W□ is created. Ru. The pulse width W□ at this time is the sum of the delay time of the gate 201, the delay time of the gate 202, and the delay time of the delay element 205.

On the other hand, when the 1 selection signal 214S is '0'', the waveform is shown by the dotted line in FIG. The gate 203 performs the function of the gate 202 in the explanation when the signal 214S is 11'', and the pulse width W2 is created. The pulse width W at this time is the sum of the delay time of the gate 201, the delay time of the gate 203, and the delay time of the delay element 206. Delay elements 202 and 2
If the delay time with 03 is set appropriately, the 1 selection signal 21
The pulse width can be switched from 48K.

The present invention is not limited to the configuration of the above embodiment;
A desired number of gates corresponding to 2 and 203 and delay elements 205 and 206 corresponding to delay elements 206 and 206 are provided,
This is achieved by configuring a selection circuit to select one of these delay elements.

Multiple pulse widths can be selected.

〔Effect of the invention〕

The present invention has the advantage of being able to switch the pulse width even during operation.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional pulse width generation circuit. FIG. 2 is a timing diagram for explaining the operation of FIG. 1,
FIG. 3 is a production circuit diagram showing one embodiment of the present invention, and a fourth
The figure is a timing diagram for explaining the operation of this embodiment. In the figure, 201 to 204...gates, 2
05°206...Delay element, 207-214.
·····Signal line. Mayuzumi 1 Hyōmine 2 Betsuko 3 eyes and a half 4 - Edict

Claims (1)

[Claims] A plurality of first circuits each having a plurality of input terminals and NANDing signals applied to these input terminals and outputting the result, and one of the plurality of first circuits being selected in response to a selection signal. a selection circuit, a plurality of first input terminals to which respective outputs of the plurality of first circuits are inputted, and a second input terminal to which input signals are inputted, and signals given to these input terminals; Output the NAND and AND of 9 and output this N
a second circuit that provides an AND output to the plurality of first circuits; and a second circuit that is provided in one-to-one correspondence with the plurality of first circuits and has different delay times, and outputs an AND output of the second circuits. A pulse width generating circuit comprising a plurality of delay circuits each delaying and applying the signal to the plurality of first circuits.