JPH10170604A - Input/output buffer test circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test an input/output buffer of an LSI chip precisely and easily. SOLUTION: Testing pulses are orderly and selectively impressed to input terminals I(0), I(n) during a test period. The test pulses are passed through an OR gate OR (1), and the output is set as a shift clock of a shift resistor SR(1). As input for shift data, a single pulse synchronizing with one of test pulses is generated with a inverter NOT(1), a NOR gate NOR(1), and RS flip- flop RST/F(1). By supplying each shift output of the shift resistor to each output buffer BO(0)-BO(7) through a selector 15, the output which successively changes '0' to '1' is selectively outputted to each output terminal in time sharing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an input / output buffer test circuit and a semiconductor integrated circuit, and more particularly to an input / output buffer test circuit for testing an input buffer connected to an input terminal and an output buffer connected to an output terminal. The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art An example of a test circuit for an input / output buffer in a semiconductor integrated circuit of this type is disclosed in JP-A-7-198.
There is a technique disclosed in JP-A-795. FIG. 4 shows a block diagram of this circuit. Referring to FIG. 4, the semiconductor integrated circuit 101 includes functional blocks 102 and 103,
A separation signal generation circuit 104, a test latch circuit 105,
An input buffer unit 106 and an output buffer unit 107 are provided.

The function block 102 comprises an internal circuit 128 and latches 129 and 130, and the function block 103 similarly includes an internal circuit 131 and a latch 13
2,133. The function blocks 102 and 103 are connected by wirings 142 to 144.

Each signal input from the input terminals 108 to 111 is transmitted to the functional block 1 via the input buffer unit 106.
02, 103 and the test latch circuit 105. Signals output from the functional blocks 102 and 103 are transmitted to the output buffer unit 107 via output switching circuits 138 to 141, and output from output terminals 114 to 117.

A test latch circuit 105 composed of latches 134 to 137 having the same shape as the latches 129, 130, 132, 133 in the functional blocks 102, 103.
Is also transmitted to the output buffer unit 107 via output switching circuits 138 to 141, and output terminals 114 to 117
Output.

A test signal input from test signal input terminal 113 is transmitted as an output switching signal to output switching circuits 138 to 141 via input buffer section 106. The output switching circuits 138 to 141 output "0" as an output switching signal.
When "1" is input, the output of the functional blocks 102 and 103 is output, and when "1" is input, the test latch circuit 1 is output.
05 is output.

That is, the selection of the output of the functional blocks 102 and 103 or the output of the test latch circuit 105 from the output terminals 114 to 117 is determined by the test signal input from the test signal input terminal 113. Done.

[0008] The test signal input from the test signal input terminal 112 is input to the separation signal generation circuit 104 via the input buffer section 106, and separation signals 145 and 146 are output. The function block 10 is output by the separation signal 145.
2 is separated from the functional block 103, and is set to a state where a test can be performed using a test pattern prepared for the functional block 102 in advance.

Similarly, the function block 103 is separated from the function block 102 by the separation signal 146, and the function block 103 is set in a state where a test can be performed using a test pattern prepared for the function block 103 in advance.

Next, the operation will be described. First, in a normal operation, the test signal input terminal 113 is clamped to "0" and "0" is inputted as a test signal. Each signal input from the input terminals 108 to 111 is transmitted to the functional blocks 102 and 103 and the test latch circuit 105 via the input buffer unit 106.

The latches 129 to 133 receive the input from the input buffer unit 106 to the functional blocks 102 and 103 and transmit the output of “0” or “1” to the internal circuits 128 and 131. That is, the latches 129, 130, 132, 1
Reference numeral 33 determines “0” or “1” of the input level voltage to the functional blocks 102 and 103. Therefore, input terminal 1
Even when an intermediate level voltage is applied to 08 to 111, the intermediate level voltage is not transmitted to the internal circuits 128 and 131.

At this time, since "0" is input to the output switching circuits 138 to 141 as an output switching signal, the function blocks 102 and 10 are output via the output switching circuits 138 to 141.
3 is transmitted to the output buffer unit 107. Therefore, the outputs of the functional blocks 102 and 103 are output to the output terminals 114 to 117 via the output buffer unit 107, and the output of the test latch circuit 105 is not output.

The input buffer unit 106 and the output buffer unit 1
At the time of the test 07, “1” is input as a test signal from the test signal input terminal 113. At this time, "1" is input to the output switching circuits 138 to 141 as an output switching signal. Therefore, the outputs of the functional blocks 102 and 103 are not transmitted to the output buffer unit 107, and the input terminals 108 to 108
The signal input from the input 111 is input to the output buffer 107 via the input buffer 106 and the test latch circuit 105.
And output from output terminals 114-117.

As described above, the input terminal and the output terminal correspond to the buffer in the input buffer unit 106 and the test latch circuit 105.
And the output switching circuits 138 to 141 and the buffer in the output buffer unit 107.

Therefore, the signals input from the input terminals 108 to 111 are connected to the latch 13 in the test latch circuit 105.
4 to 137 determine “0” or “1”, and output terminals 114 to 117 output signals of “0” or “1”. The input of “0” to the semiconductor integrated circuit 101 means that the latches 129, 130, 132, and 133 in the function blocks 102 and 103 transmit the internal circuit 12.
That is, "0" is input to 8,131.

Similarly, the input of “1” to the semiconductor integrated circuit 101 means that the functional blocks 102 and 103
Means that "1" has been input from the latches 129, 130, 132, 133 to the internal circuits 128, 131. That is, the input to the semiconductor integrated circuit 101 is made by the latches 129, 130, 1 in the functional blocks 102, 103.
32 and 133, it is determined as “0” or “1”.

[0017]

In the conventional input / output buffer test circuit shown in FIG. 4, as an example of a test pattern at the time of testing, all "1" s or all "0" is supplied, and all "1",
Alternatively, it is designed to test that all “0” is derived.

As described above, all output terminals are simultaneously set to "0".
Since the switching control is performed so as to be "1", a large amount of current flows in the LSI, and the power supply voltage fluctuates, and the threshold level fluctuates. There is a drawback that you can not.

Further, since only "0" / "1" is considered as the state of the output terminal, there is a disadvantage that the input / output level test of the bidirectional terminal (input / output shared terminal) and the three-state output terminal cannot be performed.

It is an object of the present invention to provide an input / output buffer test circuit and a semiconductor integrated circuit capable of preventing a large amount of current from flowing at the time of a test and performing an accurate test.

Another object of the present invention is to provide an input / output buffer test circuit and a semiconductor integrated circuit which can also perform an input / output level test of a bidirectional terminal or a three-state output terminal.

[0022]

According to the present invention, there is provided an input / output buffer test circuit for testing an input buffer connected to an input terminal and an output buffer connected to an output terminal. ORing means for logically ORing output pulses of the sequentially supplied test pulses through the input buffers respectively, and a single pulse synchronized with the test pulse in response to one of the test pulses , A shift means for sequentially shifting the single pulse in synchronization with an output of the OR means, and a supply for supplying each shift output of the shift means to an input of the output buffer during a test. And an input / output buffer test circuit.

The supply means includes switching means for switching each output of a functional circuit block provided between the input buffer and the output buffer to a corresponding output buffer in a normal state other than a test. It is characterized by having.

Also, at least one of the output buffers is a three-state buffer, and one of the shift outputs of the shift means is supplied to a control terminal of the three-state buffer so that a high impedance output state can be generated. It is characterized by.

Further, at least one of the input terminals is an input / output shared terminal, and an input and an output buffer are respectively connected to the input / output shared terminal. And an output of an input buffer connected to the input / output shared terminal is supplied to one input of the logical sum means.

The output buffer is controlled to the active state at least during a period when one of the shift outputs of the shift means is supplied to the output buffer corresponding to the input / output terminal, and the high impedance is maintained during the remaining period. It is characterized by further including control means for controlling the state.

According to the present invention, the input / output buffer test circuit, the input and output terminals, the input and output buffers, and the functional circuit block have a one-chip semiconductor integrated circuit configuration. Is obtained.

The operation of the present invention will be described. A test pulse is sequentially and selectively applied to all of the input terminals and the input side of the bidirectional (input / output) terminal, and a clock obtained by performing a logical OR operation on all of the applied pulses is used as a shift clock. Operate the register. A single pulse synchronized with one of the test pulses is applied to the data input of the shift register, and each output of the shift register is sequentially supplied to the output terminal and the output side of the bidirectional terminal. I do.

One of the outputs of the shift register is also supplied to the control terminal of the three-state buffer, which is a three-state terminal, to generate a high impedance state.

By doing so, changes of "0" and "1" can be generated in a time-division manner on all of the output terminals and the output side of the bidirectional terminal, and "0" can be generated on the three-state terminals. , "1", a high impedance state can be generated.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor integrated circuit showing an embodiment of the present invention. In the semiconductor integrated circuit 1 of FIG. 1, each of the input terminals I (0) to I (n) of the input terminal group 13 corresponds to the corresponding input buffer BI (0) to B (B) in the input buffer group 14.
I (n) is connected to the original circuit (internal functional circuit block) 11 via each
Is also connected to.

Each output of the original circuit 11 is connected to the selector 1
5, the output buffers BO (0) to BO (7) in the output buffer group 16, the 3-state buffer group 17, and the bidirectional buffer group 18 via the corresponding switches S (0) to S (11), respectively. , And control terminals (in the case of a three-state buffer).

These output buffers BO (0) to BO (7)
Are output terminals O (0) to O (5), corresponding to the output terminal group 19, the three-state terminal group 20, and the bidirectional terminal group 21.
It is supplied to IO (0) and IO (1), respectively.

The bidirectional terminals IO (0) and IO (1) become the input of the original circuit 11 and the input of the input / output test circuit 12 via the input buffers BIO (0) and BIO (1), respectively. ing.

The output of the input / output test circuit 12 is
Of each of the selectors S (0) to S (11), and a test switching signal from a test terminal I (test) is supplied to a buffer BI.
It is input to the input / output test circuit 12 via (n + 1) and is also supplied as a selection signal for each of the selectors S (0) to S (11).

FIG. 2 is a circuit diagram showing a specific example of the input / output test circuit 12 of FIG. The OR circuit OR (1) includes all input buffers (including the input side of the bidirectional terminal) BI (0) to BI (0)
(n), BIO (0) and BIO (1).

The output of the OR gate is led to an output terminal O (0) via a selector S (0) and an output buffer BO (0). The output via the OR gate selector S (0) is the shift clock input of the shift register SR (1). The output pulse of the delay circuit DL (1) is applied to the data input of the shift register.

The inputs of the delay circuit include an inverter NOT (1), a NOR gate NOR (1), and an AND gate AN.
A single pulse is applied by a single pulse generating circuit including D (1) and RS flip-flop RSF / F (1). This one-shot pulse is delayed by the delay circuit DL (1). This delay is to compensate for the delay due to the delay time by the OR gate OR (1). Thus, the data is sequentially shifted according to the shift clock.

The shift outputs Q0 to Q6 are connected to selectors S1 to S7.
Input (D1 input), and the shift outputs Q7 to
Q9 is an input of an OR gate OR (2), and shift outputs Q10 to Q12 are inputs of an OR gate OR (3). Each output of the OR gates OR (2) and OR (3) becomes one input (D1 input) of the selectors S (9) and S (11), and the output of the AND gates AND (4) and AND (5). It is also one input.

The other inputs of the AND gates AND (4) and AND (5) are the outputs of the input buffers BIO (0) and BIO (1) of the bidirectional terminals IO (0) and IO (1), respectively. Has been applied. The output of these AND gates is OR gate OR (1)
Is also input. The shift outputs Q8 and Q11 are each one input (D1 input) of the selectors S (8) and S (10).

The selectors S (1) to S (4), S (6), S (8),
Each output of S (10) is led to a corresponding output terminal via output buffers BO (1) to BO (7).

As described above, the three-state buffer BO
The selectors S (5) and S (7) are connected to the control inputs of (4) and BO (5).
The outputs of the selectors S (9) and S (11) are applied to the control inputs of the three-state buffers BO (6) and BO (7), respectively.

Inverter NOT (1), NOR gate NOR
In the single-pulse generation circuit consisting of (1), AND gate AND (1) and RS flip-flop RSF / F (1), the output of input buffer BI (1) is connected to inverter NOT.
(1), the input buffers BI (0), BI
The output of (2) is two inputs of the NOR gate NOR (1). One input of the AND gate AND (1) is connected to the output of the NOR gate NOR (1), and the other input is connected to a test input terminal I (test).

The output of the inverter NOT (1) and the output of the AND gate AND (1) are applied to the set input and the reset input of the RS flip-flop RSF / F (1), respectively.

FIG. 3 is a timing chart showing an example of a signal waveform of each part of the circuit of FIG. During a period when the test signal I (test) is at a high level, a test pulse is alternately sequentially transmitted to the input terminals I (0) to I (n) and the bidirectional terminals IO (0) and IO (1). Shall be supplied by

Each of these test pulses is OR gate OR
(1), the shift register SR
The shift clock of (1) is generated. on the other hand,
RS flip-flop R constituting a single pulse generation circuit
A single pulse having a pulse width of one cycle of the test pulse is generated at the output of SF / F (1) in synchronization with the test pulse.

Since this single pulse is the data input to the shift register SR (1) via the delay circuit DL (1), this single pulse is sequentially shifted in the shift register in synchronization with the shift clock. Become.

Therefore, the OR gate output appears at the output terminal O (0) as it is, and the one-shot pulse sequentially shifted appears at the output terminals O (1) to O (5) in a time division manner.

In this case, the three-state buffer BO (4),
BO (5) enters a through state when its control terminal is at a low level, and has a high impedance (Hi) when its control terminal is at a high level.
-Z) state, as shown in FIG. 3, the three-state terminals O (4) and O (5) have "Hi-Z" after one shift clock from the state of "0" → "1". "It turns out that it is in a state.

The three-state buffers BO (6) and BO (7) corresponding to the bidirectional terminals IO (0) and IO (1) have a through (output) state when their control terminals are at a high level and a low state when their control terminals are at a low level. Assuming that the input terminal is in a high impedance state (input state as a bidirectional terminal), an OR gate O is connected to each control terminal.
Since high-level pulses for three cycles of the shift clock are applied by R (2) and OR (3), a through state is provided during that period, the circuit is activated and operates as an output buffer.

During this period, the outputs S8 and S11 of the shift register are applied to the inputs of these three-state buffers BO (6) and BO (7) via the selectors S (8) and S (10), respectively. , The terminals IO (0) and IO (1) are changed from "0" to "1".
Appears.

The AND gates AND (4) and AND (5)
Is a gate for passing the inputs of the bidirectional terminals IO (0) and IO (1), and is for masking the inputs during the remaining period.

At the time of normal operation, by setting the test signal of the test terminal I (test) to low level, the selector 15
Of course, all the selectors operate to derive the output of the original circuit 11 to the output buffer.

[0055]

As described above, according to the present invention, since all the output terminals do not change at the same time, there is no change in the current and, consequently, in the power supply voltage. There is an effect that there is.

For the three-state output terminal,
In addition to the change of “0” and “1”, a change of high impedance can be caused, and further, a change of “0” and “1” can be caused on the output side of the bidirectional terminal.

Furthermore, the scale of the test circuit can be reduced by connecting one shift output of the shift register to a plurality of output terminals. In this case, assuming that the circuit simultaneous operation limit number is M, the required bit number N of the shift register is N = (number of output terminals / M) + (number of three-state terminals / M) + (number of bidirectional terminals / M) × 3

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a specific circuit diagram of an embodiment of the present invention.

3 is an operation timing chart of each part of the circuit of FIG. 2;

FIG. 4 is a block diagram illustrating an example of a conventional test circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 11 Original circuit (functional circuit block) 12 I / O test circuit 13 Input terminal group 14 Input buffer group 15 Selector 16 Output buffer group 17 3-state buffer group 18 Bidirectional buffer group 19 Output terminal group 20 3-state terminal Group 21 Bidirectional terminal group OR (1), OR (2), OR (3) OR gate AND (1), AND (4), AND (5) AND gate NOT (1) Inverter NOR (1) NOR gate RSF / F (1) RS flip-flop SR (1) shift register DL (1) delay circuit

Claims (6)

[Claims] 1. An input / output buffer test circuit for testing an input buffer connected to an input terminal and an output buffer connected to an output terminal, the test pulse being selectively supplied to the input terminal sequentially. ORing means for ORing output pulses respectively passed through the input buffers of the above, and a single pulse generating means for generating a single pulse synchronized with the test pulse in response to one of the test pulses; Input means for sequentially shifting the single pulse in synchronization with the output of the OR means, and supply means for supplying each shift output of the shift means to the input of the output buffer during a test. Output buffer test circuit. 2. The switching unit according to claim 1, wherein the supply unit switches the output of a functional circuit block provided between the input buffer and the output buffer to a corresponding output buffer in a normal state other than a test. 2. The input / output buffer test circuit according to claim 1, comprising: 3. At least one of said output buffers is 3
3. The input / output buffer according to claim 1, wherein the input / output buffer is a state buffer, and one of the shift outputs of the shift means is supplied to a control terminal of the three-state buffer to generate a high impedance output state. Test circuit. 4. An input / output terminal, wherein at least one of the input terminals is an input / output terminal, an input / output buffer is connected to the input / output terminal, and the test pulse is supplied to the input / output terminal. And an output of an input buffer connected to the input / output terminal is supplied to one input of the OR circuit.
The input / output buffer test circuit according to any of the above. 5. The output buffer is controlled to an active state at least during a period when one of the shift outputs of the shift means is supplied to an output buffer corresponding to the input / output common terminal, and the high impedance is maintained during the remaining period. 5. The apparatus according to claim 4, further comprising control means for controlling the state.
An input / output buffer test circuit as described. 6. The input / output buffer test circuit according to claim 1, wherein said input and output terminals, said input and output buffers, and said functional circuit block are configured as a one-chip semiconductor integrated circuit. A semiconductor integrated circuit.