JPH06101636B2 - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent power switching devices and their control circuits mounted on a single metallic substrate as modules and connected in bridges from making malfunctions due to noise, etc. CONSTITUTION:The first and second control circuits 13 and 14 are formed on an aluminum substrate 31 respectively through the first insulating layer 32, first and second shield patterns 101 and 104, and second and third insulating layers 105 and 106 and, at the same time, the first and second shield patterns 101 and 104 are respectively fixed at potentials corresponding to the potentials of the output electrodes of the first and second power transistors 1 and 2. When noise is impressed upon the current routes of the first and second power switching elements with respect to the metallic substrate, the noise also appears in their control circuits with respect to the metallic substrate. As a result, the state becomes equivalent to such a state where no noise exists in the control circuits when the state is viewed from the output electrodes of the first and second power switching elements. Therefore, such an effect is obtained that no malfunction is caused by the noise.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to prevention of malfunction of a bridge-connected power switching device modularized on a single metal substrate and its control circuit due to noise or the like.

[0002]

2. Description of the Related Art FIG.
It is a circuit diagram which shows the conventional inverter circuit of a phase bridge structure. This inverter circuit includes six power NPN transistors 1-6. Transistors 1 and 2, 3 and 4,5
And 6 are connected to the totem pole respectively, and the power supply terminals P,
It is connected in parallel between N. A high voltage with the terminal P side being positive is applied between the power supply terminals P and N. Transistor 1
Is connected to the U-phase output terminal U, and the connection point between the emitter of the transistor 3 and the collector of the transistor 4 is connected to the V-phase output terminal V.
And a connection point between the emitter of the transistor 5 and the collector of the transistor 6 is connected to the W-phase output terminal W. Flywheel diodes 7 to 12 are connected between the emitters and collectors of the transistors 1 to 6, respectively.

A control circuit 1 for controlling on / off of the transistors 1-6 is provided at the bases of the transistors 1-6.
3-18 are respectively connected. Control circuits 13-1
Reference numeral 8 includes drivers 25 to 30 for receiving control signals applied to input terminals 19 to 24 and generating base drive signals for transistors 1 to 6, respectively. Transistor 1
6 to 6 are turned on / off in response to a control signal input to input terminals 19 to 24. The control circuits 13 to 18 also include a protection circuit that detects an overcurrent, an overvoltage, an overheated state, and the like and takes an appropriate protection operation, if necessary. Further, the control circuits 13, 15 and 17 on the upper arm side include the input terminals 19, 21 and
It also includes an interface circuit such as a photocoupler for level-shifting the control signal of low voltage level applied to 23 to a high voltage level. The control circuits 13 to 18 are composed of ICs, discrete transistors, resistors, capacitors, and the like. Control circuit 13, 15, 1 on the upper arm side
As the power source of 7, individual power sources V _UP , V _VP , V _WP
And a common power source V _N is provided as a power source for the control circuits 14, 16 and 18 on the lower arm side.

The circuit shown in FIG. 12 has power supplies V _UP , V _VP , V _WP ,
Except for V _N , it is formed as a module on a single metal substrate. The power supplies V _UP , V _VP , and V _WP on the upper arm side can also be generated in the module by boosting the power supply V _N on the lower arm side by a charge pump circuit formed on a metal substrate.

FIG. 13 is a sectional view showing the structure of a U-phase portion when the circuit of FIG. 12 is formed on a single metal substrate. An insulating layer 32 is formed on the aluminum substrate 31,
A copper pattern 33 similar to the wiring pattern of the printed wiring board is formed thereon. The power transistors 1 and 2 and the control circuits 13 and 14 are copper patterns 3 by soldering or the like.
Fixed on 3. The aluminum wires 34 and 35 are base wires, and the aluminum wires 36 and 37 are emitter wires. The copper pattern 33 is properly connected outside the figure, and a part of the connection is connected to the connecting line 3.
Equivalently shown by 8,39. In this way, the U-phase circuit portion of FIG. 12 is formed on the single aluminum substrate 31, and is connected to the outside through the external terminals U, N, P, 19, 20 also formed on the aluminum substrate 31. It is supposed to be done.

FIG. 14 is an enlarged sectional view showing a portion on the upper arm side in FIG. Since the copper pattern 33 and the aluminum substrate 31 are opposed to each other with the insulating layer 32 interposed therebetween, a capacitance is formed between them. That is, the copper pattern 33 is capacitively coupled to the aluminum substrate 31.
14, the capacitance between the copper pattern 33a and the aluminum substrate 31 are connected (the negative side of the collector and the power supply V _U P emitter of thus power transistor 1 and the power transistor 2) the output terminal U C
1. The capacitance between the copper pattern 33b to which the input terminal 19 is connected and the aluminum substrate 31 is shown as C2. The inter-pattern capacitance between the copper patterns 33a and 33b is shown as C3. The terminals S connected to the aluminum substrate 31 are for convenience of description.

[0007]

In order to examine how the noise applied between the terminals U and S affects the terminal 19, attention is paid only to the capacitors C1, C2 and C3. The capacity of is ignored.

FIG. 15 is an equivalent circuit diagram showing the capacitors C1, C2 and C3. The area of the copper pattern 33a is the copper pattern 3
Since the area is larger than that of 3b, the capacitance C1 is larger than the capacitance C2. Since the capacitance C3 is the capacitance between patterns,
It is extremely smaller than the capacitances C1 and C2. Therefore, the following relation holds.

[0009]

[Equation 1]

Now, it is assumed that dV / dt (U) is applied as noise to the terminal U with respect to the terminal S. At this time, noise dV / dt (1
9) can be expressed by the following equation.

[0011]

[Equation 2]

From the relation of the expression of the equation 1,

[Equation 3]

Therefore, the same noise as that applied to the terminal U with respect to the terminal S appears at the terminal 19 with respect to the terminal U. As is apparent from FIG. 12, the terminal U is an output terminal connected to the output electrode (emitter) of the power transistor 1 and also supplies the reference potential of the control circuit 13 of the power transistor 1. On the other hand, the terminal 19
Is an input terminal of the control circuit 13. There is a problem in that the circuit malfunctions due to the appearance of noise at the terminal 19 which supplies the control input of the control circuit 13 to the terminal U which supplies the reference potential of the control circuit 13. Further, such noise appears not only in the input terminal 19 but also in various signal paths of the control circuit 13, and causes a malfunction such as erroneously operating a protection function (overcurrent, overvoltage protection, etc.). There was an inconvenience. Further, such inconvenience is caused not only by the terminal U but also by the terminals V, W,
The same occurs when noise is applied to P and N (that is, the current paths of the power transistors 1 to 6).

The present invention has been made in order to solve the above problems, and is a semiconductor composed of a bridge-connected power switching device arranged on a metal substrate and a control circuit therefor, which does not malfunction due to noise. The purpose is to obtain the device.

Another object of the invention is to provide a semiconductor device capable of reducing the leakage current to a metal substrate when a power switching device is operated at high speed, in addition to achieving the above main object. Especially.

[0016]

According to another aspect of the present invention, there is provided a semiconductor device including a metal substrate, a first insulating layer formed on the metal substrate, and a totem pole connection formed on the first insulating layer. The first and second power switching elements,
First and second conductors formed on the first insulating layer
A shield pattern, a second insulating layer formed on the first shield pattern, a third insulating layer formed on the second shield pattern, and a second insulating layer formed on the second insulating layer. A first control circuit for controlling ON / OFF of the first power switching element, and a second control circuit formed on the third insulating layer for controlling ON / OFF of the second power switching element. A circuit, a first connecting means for connecting the first shield pattern to a potential according to the potential of the output electrode of the first power switching element, and a second shield pattern for the output electrode of the second power switching element. And a second connecting means for connecting to a potential according to the potential.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor device is formed on the first insulating layer at least between the first and second shield patterns and the first insulating layer. And a third shield pattern to which a constant reference voltage is applied, and a fourth shield pattern formed between the third shield pattern and the first or second shield pattern.
And an insulating layer of.

[0018]

The first and second control circuits of the first invention are
It is formed on the metal substrate via the first insulating layer, the first and second shield patterns, and the second and third insulating layers, respectively. Therefore, direct capacitive coupling between the first and second control circuits and the metal substrate is eliminated. On the other hand, the first and second
The capacitance between the control circuit and the first and second shield patterns is large. The first and second shield patterns are fixed to potentials corresponding to the potentials of the output electrodes of the first and second power switching elements, respectively. Therefore, the first and second power switching elements of the first and second power switching elements are fixed to the metal substrate. When noise is applied to the current path, noise also appears in the control circuit for the metal substrate. As a result, when viewed from the output electrodes of the first and second power switching elements, it is equivalent to that the control circuit has no noise, and the malfunction of the control circuit can be avoided.

In the semiconductor device according to the second aspect of the invention, since the third shield pattern is fixed at a constant reference potential, direct capacitive coupling between the first and second shield patterns and the metal substrate is eliminated. Therefore, the leakage current flowing through the metal substrate along with the turning on / off of the power switching element is extremely reduced.

[0020]

1 is a circuit diagram showing an inverter circuit having a three-phase bridge structure which is an embodiment of a semiconductor device according to the present invention. The circuit configuration is the same as that of the conventional inverter circuit shown in FIG.

In this embodiment, the control circuit 1 on the upper arm side
3, 15 and 17 are individual shield patterns 1
It is formed on 01, 102, 103. The control circuits 14, 16 and 18 on the lower arm side are formed on the common shield pattern 104. Shield pattern 1
01, 102, 103 are fixed to the potentials of the output terminals U, V, W (that is, the potentials of the output electrodes (emitters) of the power transistors 1, 3, 5), and the shield pattern 104 is the potential of the power supply terminal N (that is, the power). It is fixed to the output electrodes (emitter potentials) of the transistors 2, 4, and 6. The control circuits 13, 15 and 17 operate on the basis of the emitter potentials of the power transistors 1, 3, 5 respectively, and the control circuits 14, 16 and 18 operate on the basis of the common emitter potential of the power transistors 2, 4 and 6. Therefore, the shield patterns 101, 10
The potentials of 2, 103 are control circuits 13, 15, 17 respectively.
Is kept at the same potential as the reference potential of the shield pattern 104.
Is maintained at the same potential as the common reference potential of the control circuits 14, 16 and 18.

FIG. 2 is a sectional view showing the structure of the U-phase portion when the circuit of FIG. 1 is formed on a single metal substrate.
An insulating layer 32 is formed on an aluminum substrate 31, and a copper pattern 33 and shield patterns 101 and 104 similar to the wiring pattern of the printed wiring board are formed on the insulating layer 32. Shield patterns 101 and 104 are copper patterns 3
It is a copper pattern like No. 3. The copper pattern 33 may have the same thickness as the shield patterns 101 and 104, or may have a larger thickness than that. When the thickness is the same, both can be formed at the same time.

Insulating layers 105 and 106 are formed on the shield patterns 101 and 104, respectively, and a copper pattern 41 similar to the copper pattern 33 is formed thereon.
The power transistors 1 and 2 are fixed on the copper pattern 33 by soldering or the like as in the conventional case, while the control circuits 13 and 1 are
4 is fixed on the copper pattern 41 by soldering or the like.

A through hole 107 is provided in the insulating layer 105, and a copper pattern 41a connected to the minus side of the power source V _UP (that is, the output electrode (emitter) side of the power transistor 1) through the through hole 107. The shield pattern 101 is connected. Insulation layer 1
A through hole 108 is provided in 06, and the copper pattern 41b and the shield pattern 104 connected to the negative side of the power supply V _N (that is, the output electrode (emitter) side of the power transistor 2) are connected through the through hole 108. It is connected.

The aluminum wires 34 and 35 are base wires, and the aluminum wires 36 and 37 are emitter wires. The copper patterns 33 or the copper patterns 41 are properly connected to each other outside the drawing, and the copper patterns 33 and 41 can also be appropriately connected by an aluminum wire or the like. Connect some of the connections to connection line 4
2, 43 are equivalently shown. In this way, the U-phase circuit portion of FIG. 1 is formed on the single aluminum substrate 31, and is connected to the outside through the external terminals U, N, P, 19, 20 also formed on the aluminum substrate 31. It is supposed to be connected.

The external terminals U, N, P are formed on the insulating layer 32, and the external terminals 19, 20 are respectively formed on the insulating layer 10.
5, 106 is formed.

FIG. 3 is an enlarged sectional view showing a portion on the upper arm side in FIG. Since the copper pattern 33 and the aluminum substrate 31 are opposed to each other with the insulating layer 32 interposed therebetween, a capacitance is formed between them. Further, since the copper pattern 41 and the shield pattern 101 are also opposed to each other with the insulating layer 105 sandwiched therebetween, a capacitance is formed between them. In FIG. 3, the capacitance between the copper pattern 33a to which the output terminal U (therefore, the emitter of the power transistor 1 and the collector of the power transistor 2 and the negative side of the power supply V _UP ) and the aluminum substrate 31 is shown as C1. The capacitance C1 includes the capacitance between the shield pattern 101 and the aluminum substrate 31, because the potential of the shield pattern 101 is the same as the potential of the output terminal U. The capacitance between the copper pattern 41c to which the input terminal 19 is connected and the shield pattern 101 is shown as C4. Further, the capacitance for directly capacitively coupling the copper pattern 41c and the aluminum substrate 31 is C5.
And Terminal S connected to aluminum substrate 31
Are for convenience of explanation. Now terminals U and S
In order to examine how the noise applied between the terminals affects the terminal 19, only the capacitors C1, C4, and C5 are focused, and the other capacitors are ignored.

FIG. 4 is an equivalent circuit diagram showing the capacitors C1, C4 and C5. Since the total area of the copper pattern 33a and the shield pattern 101 is larger than the area of the copper pattern 41c, the capacitance C1 is larger than the capacitance C4. Further, the capacitance C5 is the capacitance of the direct capacitive coupling between the copper pattern 41c and the aluminum substrate 31, but the shield pattern 101 is interposed between the copper pattern 41c and the aluminum substrate 31 to prevent the direct capacitive coupling between the two. Therefore, the capacitance C5 is substantially equal to zero. Therefore, the following relationship holds.

[0029]

[Equation 4]

Now, it is assumed that dV / dt (U) is applied as noise to the terminal U with respect to the terminal S. At this time, noise dV / dt (1
9) can be expressed by the following equation.

[0031]

[Equation 5]

From the relation of the equation (4),

[Equation 6]

Therefore, even if noise is applied to the terminal U with respect to the terminal S, noise does not appear at the terminal 19 with respect to the terminal U. That is, the shield pattern 10
Since 1 is kept at the same potential as the terminal U, when noise is applied to the terminal U (that is, the aluminum substrate 31) with respect to the terminal S (that is, the aluminum substrate 31), the potential of the shield pattern 101 also changes, and accordingly, the shield pattern 101 and the capacitance The potential of the coupled copper pattern 41c (that is, the terminal 19) also fluctuates. Therefore, when viewed from the terminal U, the terminal 19
Is equivalent to no noise.

The terminal U is an output terminal connected to the output electrode (emitter) of the power transistor 1, and also supplies the reference potential of the control circuit 13 of the power transistor 1. On the other hand, the terminal 19 is an input terminal of the control circuit 13.
Even if noise is applied to the terminal U with respect to the aluminum substrate 31, the terminal U that provides the reference potential of the control circuit 13
On the other hand, no noise appears at the terminal 19 which gives the control input of the control circuit 13, so that the circuit does not malfunction.

Further, not only the input terminal 19 but also various signal paths of the control circuit 13 formed on the shield pattern 101 do not show noise with respect to the terminal U. Malfunctions such as overcurrent and overvoltage protection can be avoided. Other control circuit 14
The same applies to ~ 18.

Further, when noise is applied to not only the terminal U but also the terminals V, W, P and N (that is, the current paths of the power transistors 1 to 6) with respect to the aluminum substrate 31, the same operation as described above is performed. Therefore, malfunction can be avoided. Since a large-capacity capacitor is generally connected between the terminals P and N to which the high-voltage power supply is connected, noises at the terminals P and N appear in exactly the same manner.

Although the shield patterns 101 to 104 are directly fixed to the potentials of the output electrodes (emitters) of the corresponding power transistors 1 to 6 in the above embodiment,
This is not always necessary. For example, as shown in FIG. 5, when a relatively large-capacity capacitor 44 is connected between the positive terminal and the negative terminal of the power supply V _N , noise appears at the emitter of the power transistor 2 (that is, the terminal N). The potential on the positive side of the power supply V _N also changes accordingly. As shown in FIG. 6, a reverse bias circuit composed of a resistor 45 and diodes 46 and 47 is connected to the emitter of the power transistor 2 in order to reverse bias the base when the power transistor 2 is off, and the emitter potential is level-shifted up. In this case, if noise appears in the emitter of the power transistor 2, noise also appears in the negative side of the power supply V _N. Diode 4
6, 47 may be Zener diodes. If the shield pattern 104 is fixed to a potential according to the potential of the output electrode (emitter) of the power transistor 2, the above-described effect can be exhibited, so that the shield pattern 104 is not directly connected to the emitter of the power transistor 2 but is, for example, as shown in FIG. In some cases, the positive side of the power source V _N , or in the case of FIG.
_It may be connected to the negative side of _N. This also applies to the other shield patterns 101 to 103.

In the embodiment of FIG. 2, the shield patterns 101 and 104 are arranged on the aluminum substrate 31 as follows.
It is preferably carried out by any of the following methods. In the first method, the copper pattern 33 is first formed on the insulating layer 32. Then, the structure in which the copper pattern 41 and the shield pattern 101 are formed on the front surface and the back surface of the insulating layer 105, and the laminated body in which the copper pattern 41 and the shield pattern 104 are formed on the front surface and the back surface of the insulating layer 106 are formed on both sides, respectively. Of the printed circuit board or the like, and these laminated bodies are arranged at predetermined positions on the insulating layer 32. In the second method, the copper pattern 33 and the shield patterns 101 and 104 are simultaneously formed on the insulating layer 32. Then, a laminated body in which the copper pattern 41 is formed on the surfaces of the insulating layers 105 and 106 is formed by a single-sided printed board or the like, and these laminated bodies are arranged on the shield patterns 101 and 104, respectively.

FIG. 7 is a sectional view showing another embodiment of the semiconductor device according to the present invention. Unlike the embodiment of FIG. 2, the shield patterns 101 and 104 are arranged on the relatively thick insulating layers 109 and 110 formed on the insulating layer 32, respectively. Further, the copper pattern 33 for the power transistors 1 and 2 is formed relatively thick. Since a large current flows through the power transistors 1 and 2, the copper pattern 33
Thicker is preferable.

Insulating layer 109, shield pattern 101,
The laminated body of the insulating layer 105 and the copper pattern 41 may be formed of a two-layer printed circuit board or the like, and this may be arranged at a predetermined position on the insulating layer 32. According to this embodiment, there is an advantage that the laminate can be placed on the copper pattern 33 so as to reduce the area.

In the above embodiment, the electrical connection via the through holes 107 and 108 was described as means for fixing the potential of the shield patterns 101 and 104, but a short circuit made of aluminum wire, soldering, or metal pieces is used. You may connect by components. in this case,
Connection can be facilitated by removing a part of the insulating layers 105 and 106 and exposing a part of the upper surfaces of the shield patterns 101 and 104.

By the way, in the semiconductor device of the embodiment shown in FIG. 2 or FIG. 7, the malfunction of the control circuits 13 to 18 due to the noise as described above can be avoided, but the shield patterns 101 and 104 and the aluminum substrate 31 are prevented. Since they face each other with the insulating layer 32 interposed therebetween and are capacitively coupled, the following inconvenience may occur. That is, in these semiconductor devices, the potentials of the output electrodes (emitters) of the power transistors 1, 3, 5 on the upper arm side fluctuate significantly depending on the on / off states of the power transistors on the upper arm side and the lower arm side of each phase. For example, regarding the U phase, when the power transistor 1 is on and the power transistor 2 is off, the shield pattern 1
The potential of 01 becomes equal to the potential of the terminal P, while the potential of the shield pattern 101 becomes equal to the potential of the terminal N when the power transistor 1 is off and the power transistor 2 is on. Therefore, when the power transistors 1 and 2 are PWM-controlled, for example, when the carrier frequency of the pulse sent to the base is increased, the potential of the shield pattern 101 is displaced at high speed, and as a result, the capacitance between the shield pattern 101 and the aluminum substrate 31 changes. A leakage current to the aluminum substrate 31 is generated. Shield pattern 101
Area is relatively large, and accordingly, the capacitance between the shield pattern 101 and the aluminum substrate 31 also increases accordingly. Therefore, the leakage current increased by this capacitance may exceed the standard of the device. The semiconductor device of the embodiment shown in FIGS. 8 and 9 reduces such leakage current to the aluminum substrate 31.

The inverter circuit of the three-phase bridge configuration shown in FIG. 8 has the same circuit configuration as that of the conventional inverter circuit of FIG. 12 described above, like FIG. 1, and therefore the description thereof is omitted here. The semiconductor device of FIG. 8 also has shield patterns 101, 102, 103 kept at the same potential as the reference potentials of the control circuits 13, 15, 17 and a common reference potential of the control circuits 14, 16, 18, respectively. It has the shield pattern 104 kept at the same potential,
Since these shield patterns 101 to 104 are formed in the same manner as in FIG. 1, detailed description thereof will be omitted here.

In this embodiment, the insulating layer 32 formed on the aluminum substrate 31 and the shield pattern 10 are formed.
1 to 104 between the shield pattern 111 and the insulating layer 1
12 are provided. The shield pattern 111 is formed on the insulating layer 32.
An insulating layer 112 is formed on the above. The shield pattern 111 includes power transistors 1, 2 (or power transistors 3, 4,
It is fixed to the reference potential of the power transistors 5, 6), that is, the potential of the power supply terminal N.

The shield pattern 111 is fixed to the potential of the power supply terminal N as shown in FIG. 9, for example. FIG. 9 is a cross-sectional view showing the structure of the U-phase portion when the circuit of FIG. 8 is formed on a single metal substrate. An insulating layer 32 similar to that in FIG. 2 is formed on the aluminum substrate 31. A shield pattern 111 made of copper is formed on the insulating layer 32 so as to overlap the insulating layer 32. An insulating layer 112 is formed on the shield pattern 111 so as to overlap the entire area of the shield pattern 111. The copper pattern 3 is formed on the insulating layer 112 with the same structure as the insulating layer 32 in the embodiment of FIG.
3. Shield patterns 101 and 104 are formed. These copper pattern 33, shield pattern 101,
The configuration above 104 is exactly the same as that in FIG. 2, and therefore its explanation is omitted here.

The copper pattern 33 is formed on the insulating layer 112.
A through hole 113 is formed in a portion corresponding to the copper pattern 33c which is a part of the through hole 11.
3, the shield pattern 111 is a copper pattern 3
3c is connected. The copper pattern 33c is a terminal that relays the output electrode (emitter) of the power transistor 2 and the power supply terminal N. That is, the shield pattern 111 is connected to the power supply terminal N via the copper pattern 33c, and thereby fixed to a constant reference potential.

By providing the shield pattern 111 and the insulating layer 112 fixed to the constant reference potential as described above between the shield patterns 101 and 104 and the insulating layer 32, the shield pattern 10 is provided in the semiconductor device of this embodiment.
1 between the aluminum substrate 31 and the shield pattern 111
Is shielded by, and there is no direct capacitive coupling between them. Therefore, even if the potential of the shield pattern 101 is displaced at high speed as described above, the leakage current to the aluminum substrate 31 is extremely reduced as compared with the case of the embodiment of FIG.

The semiconductor device of the embodiment shown in FIG.
Insulating layer 32 and shield pattern 1 as in the semiconductor device of
A shield pattern 111A and an insulating layer 112A fixed at a constant reference potential are provided between 01 to 104. However, the shield pattern 111A and the insulating layer 112A of this embodiment are not formed at the locations corresponding to the power transistors 1 to 6. That is, the shield pattern 111A does not shield the power transistors 1 to 6. Only in this respect, the semiconductor device of FIG. 10 is different from the semiconductor device of FIG. 8 above, and the other parts have the same configuration.

FIG. 11 is a sectional view showing the structure of the U-phase portion of FIG. On the insulating layer 32, a shield pattern 111A is formed in a portion other than the portions corresponding to the power transistors 1 and 2. This shield pattern 11
1A is connected to the power supply terminal N via the external wiring 114 using an aluminum wire, soldering, a short-circuit component, etc. and the copper pattern 33c. Shield pattern 111
An insulating layer 112A is formed on A, and shield patterns 101 and 104 are formed on the insulating layer 112A. Since the configuration on the shield patterns 101 and 104 is the same as that of the above-described embodiment, the description thereof is omitted here.

On the other hand, copper patterns 33 are formed on the insulating layer 32 at the portions corresponding to the power transistors 1 and 2. This copper pattern 33 is a shield pattern 111A
They may be formed at the same time or may be formed independently. The power transistors 1 and 2 are connected to the copper pattern 33 by soldering or the like.

The shield pattern 111A may be formed by enlarging the copper pattern 33c forming the output terminal of the power transistor 4 in the copper pattern 33. This simplifies the external wiring that connects the shield pattern 111A and the power supply terminal N.

According to the semiconductor device of the embodiment shown in FIGS. 10 and 11, the leakage current to the aluminum substrate 31 can be reduced for the same reason as the semiconductor device of FIGS. 8 and 9. Moreover, in this embodiment, since the insulating layer directly under the power transistors 1 to 6 is only the insulating layer 32,
Compared with the embodiment of FIGS. 8 and 9 in which the insulating layer 32 and the insulating layer 112 are doubly formed immediately below the power transistors 1 to 6, the effect of reducing the thermal resistance of the power transistors 1 to 6 is obtained. is there.

In the embodiment shown in FIGS. 8 and 10, the shield pattern 1 formed on the insulating layer 32 is used.
Although 11 or 111A is connected to the power supply terminal N to reduce the leakage current, the same effect can be obtained even if the shield pattern 111 or 111A is connected to the power supply terminal P. In short, the shield patterns 111 and 111A need only be fixed to a constant reference potential.

In each of the above embodiments, the case where the power switching device is a bipolar transistor has been described, but a power MOSFET, an insulated gate bipolar transistor (IGBT) or the like may be used.
Further, it is not limited to the NPN transistor and may be a PNP transistor.

[0055]

According to the first aspect of the present invention, the first substrate is formed on the metal substrate.
Insulating layer, the first and second shield patterns, the second,
The first and second control circuits are formed via the third insulating layer, respectively, and the first and second shield patterns are formed at potentials corresponding to the potentials of the output electrodes of the first and second power switching elements. Since the first and second control circuits and the metal substrate are not directly capacitively coupled to each other, the first and second control circuits and the first and second shield patterns are not connected to each other. When the noise is applied to the current paths of the first and second power switching elements with respect to the metal substrate, noise also appears in the control circuit with respect to the metal substrate. As a result, when viewed from the output electrodes of the first and second power switching elements, the control circuit is equivalent to having no noise, and there is an effect that malfunction due to noise can be avoided.

According to the second aspect, in addition to the effect of the first aspect, there is an effect that the leakage current generated due to the switching of the power switching element can be reduced.

[Brief description of drawings]

1 is an embodiment of a semiconductor device according to the present invention; FIG.
It is a circuit diagram which shows the inverter circuit of a phase bridge structure.

FIG. 2 is a cross-sectional view showing a structure of a U-phase circuit portion when the circuit of FIG. 1 is formed on a metal substrate.

FIG. 3 is an enlarged sectional view showing a portion on the upper arm side in FIG.

FIG. 4 is an equivalent circuit diagram showing a coupling capacitance.

5 is a circuit diagram showing a modification of the embodiment of FIG.

FIG. 6 is a circuit diagram showing another modification of the embodiment of FIG.

FIG. 7 is a sectional view showing another semiconductor device according to the present invention.

FIG. 8 is a circuit diagram of another semiconductor device according to the invention.

9 is a cross-sectional view showing the structure of a U-phase circuit portion when the circuit of FIG. 8 is formed on a metal substrate.

FIG. 10 is a circuit diagram of another semiconductor device according to the invention.

11 is a cross-sectional view showing the structure of a U-phase circuit portion when the circuit of FIG. 10 is formed on a metal substrate.

FIG. 12 is a circuit diagram showing a conventional inverter circuit having a three-phase bridge configuration.

13 is a cross-sectional view showing the structure of a U-phase circuit portion when the circuit of FIG. 12 is formed on a metal substrate.

FIG. 14 is an enlarged cross-sectional view of a portion on the upper arm side in FIG.

FIG. 15 is an equivalent circuit diagram showing a coupling capacitance.

[Explanation of symbols]

 1-6 Power NPN transistor 13-18 Control circuit 31 Aluminum substrate 32,105,106 Insulating layer 101-104 Shield pattern 107,108 Through hole 111,111A Shield pattern

Claims (2)

[Claims] 1. A metal substrate, a first insulating layer formed on the metal substrate, and first and second power switching elements formed on the first insulating layer and connected to a totem pole. A first and a second shield pattern made of a conductor formed on the first insulating layer; a second insulating layer formed on the first shield pattern;
A third insulating layer formed on the shield pattern, and a first control circuit formed on the second insulating layer for controlling ON / OFF of the first power switching element; A second layer for controlling on / off of the second power switching element, the second layer being formed on the third insulating layer.
Of the control circuit and the first shield pattern
First connecting means for connecting to a potential according to the potential of the output electrode of the power switching element, and a second connecting means for connecting the second shield pattern to a potential according to the potential of the output electrode of the second power switching element. 2. A semiconductor device having two connecting means. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed on the first insulating layer at least between the first and second shield patterns and the first insulating layer, and is fixed to a constant reference potential. A semiconductor device comprising: a third shield pattern; and a fourth insulating layer formed between the third shield pattern and the first or second shield pattern.