JPH06100892B2 - Computer system display controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for a computer system, and more particularly, to a liquid crystal television receiver coupled to a computer main body,
The present invention relates to a display control device of a computer system that displays characters by using the liquid crystal television receiver as a display monitor.

(Prior Art) Conventionally, a portable computer called a pocket computer or the like is provided with a liquid crystal display for display integrated with the computer. By the way, in recent years, a small liquid crystal television receiver has been developed in response to a request for a portable television receiver. In view of such circumstances, the liquid crystal television receiver is not specially provided in the portable computer, the liquid crystal television receiver is coupled to the portable computer, and the liquid crystal display of the liquid crystal television receiver is It can be considered to be used as a display monitor of the computer.

However, for example, a liquid crystal display for a color display used in a liquid crystal television receiver has an R value as shown by a bold line in FIGS. 10 and 11.
One display dot 2 (2 ₁ to 2 ₄ ) is composed of three dots of (red), G (green), and B (blue). Moreover, since the shape of one display dot is small, if each display data of the character pattern output from the computer main body is allocated in a one-to-one relationship with the display dot, the character shape displayed on the liquid crystal display becomes small. As a result, there is a problem that the displayed characters are very difficult to see.

In addition, when the display is performed using the display dots arranged in one vertical line or one horizontal line as described above, the display characters may extend in the vertical direction or the horizontal direction, resulting in different display images. . In order to eliminate such a change in the display image, if one display dot ₂₅ is composed of four dots as shown by the bold line in FIG. 12, the ratio of one primary color (for example, in FIG. Another problem arises that the ratio of G) becomes high, which causes color misregistration.

(Object of the Invention) The present invention has been made in view of such circumstances, and in performing character display using the liquid crystal display of the liquid crystal television receiver coupled to the computer main body as a display monitor, It is an object of the present invention to provide a display control device for a computer system, which can display a display character in an easy-to-see shape and does not cause color misregistration.

(Structure of the Invention) The present invention has the following structures in order to achieve the above object.

That is, the present invention is a display control device for a computer system, in which a liquid crystal television receiver is coupled to a computer main body and character display is performed using the liquid crystal television receiver as a display monitor. Character display dots are formed by a substantially rectangular display area formed by collecting a plurality of unit display dots consisting of three dots of R (red), G (green), and B (blue) on the liquid crystal display of the receiver. By configuring and accessing the memory storing the display data to be given to the character display dots by the same number of times as the number of unit display dots constituting the character display dot, the same display data is repeatedly output from the memory. Character display is performed by sequentially reading out and allocating these display data to the unit display dots forming the character display dots in order. It is characterized by a door.

Next, the operation of the present invention having the above configuration will be described.

Character display dots are composed of a display area where multiple sets of unit display dots are gathered in a substantially rectangular shape, and the same display data is given to each unit display dot, so that the characters displayed on the liquid crystal display can be easily read. can do. Also, the character display dots are the same number of R,
Since it is composed of G and B dots, no color shift occurs.

(Example) Next, one example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an outline of the configuration of a computer system according to an embodiment of the present invention.

10 is a liquid crystal television receiver, 12 is a computer main body to which the liquid crystal television receiver 10 is detachably connected, and 14 is a connector for connecting the liquid crystal television receiver 10 to the computer main body 12.

First, the configuration of the liquid crystal television receiver 10 will be described.

The high frequency signal taken in from the antenna is given to the tuner section 16 and tuned. The television signal output from the tuner section 16 is given to the intermediate frequency processing section 18 and subjected to audio detection and video detection. The audio signal output from the intermediate frequency processing unit 18 is amplified by the audio amplification unit 20 and then output to the speaker 22. On the other hand, the video signal output from the intermediate frequency processing unit 18 is given to the chroma processing unit 24. The chroma processing unit 24 converts this video signal into an RGB signal suitable for the liquid crystal display 28 and outputs it. This RGB signal is given to the liquid crystal display 28 via the changeover switch 26. In addition, the liquid crystal television receiver 10 has an interface 3 for converting the character display data given from the computer main body 12 into RGB signals suitable for the liquid crystal display 28.
Equipped with 0. The output of the interface 30 is given to the liquid crystal display 28 via the changeover switch 26.

The liquid crystal display 28 is provided with a 3-bit (actually, 4 bits added with redundant bits are supplied) RGB signal to correspond to a predetermined array of color pixel (R, G, B) dots. It is gated and driven. The arrangement of color pixel dots is, for example, R, G, B such that the first line is RGBRGB ..., The second line is GBRGBR ..., The third line is BRGBRG ...
It is a repeating array of each dot corresponding to. As is well known, the liquid crystal display 28 of such a color display is, for example, an amorphous silicon thin film transistor.
Liquid crystal is enclosed between a transparent substrate on which an array is formed and a transparent glass substrate on which R, G, B color filters are formed, and is composed of a liquid crystal color panel displayed in a twisted nematic mode. There is.

The changeover switch 26 is a switch that can be changed over depending on whether a television image is displayed on the liquid crystal display 28 or a character from the computer main body 12 is displayed. The changeover switch 26 is changed over by a manual operation of an operator. However, such switching may be performed by program processing.

Next, the configuration of the computer main body 12 will be described.

The CPU 32 performs data processing according to the system program stored in the ROM 34 in advance. The RAM 36 is composed of a user program area for storing a user program, a data area for storing data such as display information created by the user program, and a system area including various buffers. A keyboard 38 for inputting data is provided in association with the CPU 32.

The display controller 40 is an essential part of this embodiment, and based on the data stored in the RAM 36, the video controller 40
Read / Write control is performed on AM42, and this video RAM42
The display data read from the device is bit-developed into a form suitable for the liquid crystal display 28 and supplied to the interface 30. Details of the configuration of the display controller 40 will be described later. The video RAM 42 has an R, G, B data memory area for storing the display data by dividing it into R, G, B in pixel units.

2 and 3 are block diagrams showing the main configuration of the display controller 40. In particular, FIG. 2 is a block diagram of a data horizontal layout section that allocates display data in the horizontal direction of the display screen, and FIG. 3 is a block diagram of a data vertical layout section that allocates display data in the vertical direction of the display screen. is there.

The horizontal data allocator shown in FIG.
The latch circuits 44 _{1 to} 44 _{3 for} latching the R, G, and B display data output from each of them, and the parallel outputs of the latch circuits 44 _{1 to} 44 ₃ are individually given, and the shift is performed to convert these to serial data. a register 46 ₁ to 46 _3, composed of three frequency divider 48 to provide a shift timing to the shift register 46 ₁ to 46 _3, the shift register 46 ₁ to 46 ₃ to the data load timing 8 divider circuit 50 for providing a Has been done.

On the other hand, the vertical data allocator shown in FIG.
An address generation circuit 52 that specifies the upper addresses A ₁₀ and A ₁₁ of the RAM 42, an address generation counter 54 that specifies the lower addresses A _{0 to} A ₉ of the video RAM 42, and an address generation counter 54.
And an address latch circuit 56 for latching the output of the.

Next, the operation of the embodiment having the above configuration will be described.

The feature of the present embodiment is that the unit display dots of the liquid crystal display 28 are allocated to the character display dots, and the same display data is output to the plurality of unit display dots forming the character display dots. These will be described. Here, the unit display dot of the liquid crystal display 28 is a set of three dots corresponding to R, G, B, and the character display dot is displayed on the liquid crystal display 28 based on the data from the computer main body 12. The dots that form the character are formed by the display area, which is composed of a plurality of sets of unit display dots, which will be described later.

For example, as shown in FIGS. 4 and 5, in order to make the characters displayed on the liquid crystal display 28 easy to see, the character display dots 4 ₁ to 4 ₄ are composed of a plurality of sets of unit display dots. There is. Fig. 4 shows an example of a liquid crystal display in which R, G, B dots are linearly arranged vertically and horizontally, and Fig. 5 shows R, G, B dots.
An example of a liquid crystal display in which G and B dots are arranged with a half pitch shifted for each line is shown. In the arrangement of the liquid crystal display shown in FIG. 5, the distance between the same colors is smaller than that in the arrangement of the liquid crystal display shown in FIG. Therefore, in order to improve the image quality, it is preferable to use the liquid crystal display of this arrangement. Also, the fourth
Character display dots shown in Figure (a) and Figure 5 (a)
4 ₁ and 4 ₃ are composed of two sets of unit display dots, and the character display dots 4 ₂ and 4 ₂ shown in FIGS. 4 (b) and 5 (b) are shown.
4 ₄ is composed of three sets of unit display dots. How many sets of unit display dots make up one character display dot
It is determined in relation to the visibility of the displayed characters and the number of characters displayed on one screen. In other words, if the character display dots are composed of a large number of unit display dots, the display characters become large and are easy to see, but the number of display characters in one screen is reduced accordingly.

In any case, the character display dot composed of a plurality of sets of unit display dots needs to be substantially square.
Otherwise, the form of the characters displayed on the liquid crystal display is significantly deformed, which is not practical. Here, the substantially quadrangle includes the shape of the character display dots as shown in FIG. 4 and FIG.
This means that the unit display dots composed of R, G, B dots are not included in a shape such as three sets arranged in the horizontal direction.

Hereinafter, for the sake of convenience, the case of using the character display dots as shown in FIG. 4B will be described.

FIG. 6 shows the panel surface of the liquid crystal display 28 to which the character display dots 4 shown in FIG. 4 (b) are allocated. The liquid crystal display 28 is assigned 128 character display dots 4 in the horizontal direction and 64 character display dots 4 in the vertical direction. Since the character display dots 4 are composed of three sets of unit display dots, the same display data is given to these unit display dots. These display data are divided into R, G, B dots and are stored in the above-mentioned video RAM 42.

FIG. 7 is an explanatory diagram showing addresses of the video RAM 42 corresponding to the allocation of the character display dots shown in FIG.
The numerical values shown in the figure are the hexadecimal numbers of the addresses of the video RAM 42, and the R data storage area is extracted and shown. The addresses are the same for the other G data and B data storage areas. One address stores 8-bit R data, that is, R data supplied to eight character display dots in the horizontal direction. Therefore, the video RAM 42 has a memory area of 16 bytes in the horizontal direction, and the R data of 128 character display dots allocated in the horizontal direction of the liquid crystal display 28 is stored in the addresses "000H" to "00FH" in order. Has been done. Similarly, the display data of the second line of the character display dots is stored in the addresses "010H" to "01FH" in order. Further, since there are 64 character display dots in the vertical direction of the liquid crystal display 28, there is a memory area of 64 bytes in the vertical direction of the video RAM 42, and therefore the display data given to the character display dots in the 64th line. Addresses from "3F0H" to "3FF
H ”in order.

Writing display data to the address as described above
The display controller 40 performs write control based on the data stored in the RAM 36. The writing of such display data is similar to that of the conventional device, and thus detailed description thereof will be omitted.

Next, allocation of display data to character display dots, which is a feature of this embodiment, will be described.

First, the horizontal allocation of display data will be described with reference to FIG.

The R data read from the video RAM 42 is the latch circuit 4
4 is put on _{1-44 3} display data bus connected to. When there is R data on this display data bus, R data synchronized with the display basic clock in the liquid crystal display 28 is displayed.
By receiving the data latch signal, 8-bit R data on the display data bus is latched by the latch circuit 44. Next, G data carried on to the display data bus is read from the video RAM42 is latched by the latch circuit 44 ₂ by G data latch signal. Similarly, video R
B data read from AM42 is latched in the latch circuit 44 ₃ by B data latch signal. Each of the latched display data is placed on the R, G, B data buses connected to the shift registers 46 _{1 to} 46 ₃ . The R, G, B data latch signals as described above are created by the display controller 40 by taking in the display basic clock in the liquid crystal display 28 and based on this basic clock.

On the other hand, the basic clock fetched from the liquid crystal display 28 is divided by ₃ by the divide-by-3 circuit 48, given as shift clocks to the shift registers 46 _{1 to} 46 ₃ and divided by 8 by the divide-by-8 circuit 50. , And are given to the shift registers 46 _{1 to} 46 ₃ as load signals, respectively. By receiving this load signal, the R, G, B data on the data bus are individually fetched by the shift registers 46 _{1 to} 46 ₃ respectively. The 8-bit R, G, B data taken into the shift registers 46 _{1 to} 46 ₃ are sequentially output as serial R, G, B data in accordance with the timing of the shift clock, and the interface 30 of the liquid crystal television receiver 10 is used.
To the liquid crystal display 28 via. In this way, the display data stored in the video RAM 42 is allocated in the horizontal direction of the liquid crystal display 28.

Next, the vertical allocation of the display data is shown in FIGS.
Description will be made with reference to the drawings. FIG. 9 shows an operation waveform diagram of the vertical data allocating section shown in FIG.

Read signal from display controller 40 ▲
The address generation circuit 52, which is given the ▼ and the chip select signal CS, determines the upper 2 bits of the address of the video RAM 42.
Outputs A ₁₀ and A ₁₁ . By this addressing, the R, G, and B memory areas 42 _{1 to} 42 _{3 of} the video RAM 42 are specified.
On the other hand, as described with reference to FIG. 2, the load signal obtained by dividing the shift clock (see FIG. 9A) by 8 is also given to the address generation counter 54 as the count-up clock b. This count-up clock b is shown in FIG. 9 (b). In addition,
FIG. 2B2 shows the count-up clock shown in FIG. 1B1 with its time axis reduced.

The address generation counter 54 specifies the lower 20 bits A _{0 to} A ₉ of the address of the video RAM 42 by multiplying the count-up clock b. When the address generation counter 54 counts the first count-up clock, the lower bit A _{0 of the} address to be accessed first is
~ A ₉ is specified. Then, when the R data memory area 42 ₁ is designated by the address generation circuit 52, the R data
The address "000H" of the memory area 42 ₁ is accessed.
As a result, the 8-bit R data stored in the address "000H" is read and placed on the display data bus. Then, R data is latched in the latch circuit 44 ₁ as described in Figure 2.

Next, when the G data memory area 42 ₂ by the address generating circuit 52 is designated, the address "400H" based on the output of the address generating counter 54 is accessed. As a result, the 8-bit G data stored in the address "400H" is read out, and the latch circuit 44 shown in FIG.
Latched to ₂ . Similarly, by B data memory area 42 ₃ by the address generating circuit 52 is designated,
Address 8 bits are stored in the "800H" B data is read and latched by the latch circuit 44 ₃ shown in Figure 2.

After the display data of the addresses "000H", "400H", "800H" are read, the address generation counter 54 counts the second count-up clock and the lower bits of the second address from which the display data should be read. Is specified. Then, the address generation circuit 52 causes the data memory area
By sequentially specifying 42 _{1 to} 42 ₃ , the address “00
The display data stored in "1H", "401H", and "801H" are sequentially read.

In this way, the address generation counter 54 sequentially counts the 16 count-up clocks, so that the address "000H" of the first row of each of the data memory areas 42 _{1 to} 42 ₃
"00FH", "400H" to "40FH", "800H" to "80FH" are accessed in order, and R, G, B data is given to the unit display dots arranged on the first line of the liquid crystal display 28. become. FIG. 8 shows the display data thus allocated on the liquid crystal display 28 by its address. It should be noted that the figure shows only addresses for R data, but it goes without saying that the same applies to G data and B data. Further, in the figure, L _{1 to} L ₆ ... Show the number of lines of unit display dots.

By the way, as described above, in the present embodiment, the character display dots are composed of three sets of unit display dots. Therefore, as shown in FIG. 8, the second line L ₂ and the third line L ₃ of the unit display dots are formed. For, it is necessary to allocate the same display data as in the first line L ₁ .

Hereinafter, returning to FIG. 3 and FIG. 9, the data allocation of the second and subsequent lines will be described.

The address generation counter 54 shown in FIG. 3 is a presettable counter, and the count value thereof is preset to the output value of the address latch circuit 56 by receiving the preset signal c. This preset signal c is the 9th
As shown in FIG. 7C, 16 count-up clocks are output each time the address generation counter 54 counts. Although not shown, the circuit for generating the preset signal c can be easily created by monitoring the count value of the address generation counter 54 or by separately counting the count-up clock. . It should be noted that FIG. 9 (c2) shows the preset signal c shown in FIG. 9 (c1) with the time axis reduced.

Further, the address latch circuit 56 latches the output of the address generation counter 54 by the latch clock d. This latch clock d is 3 as shown in FIG. 9 (d).
Each preset signal c is output every time it is input to the address generation counter 54. Although not shown, a circuit for generating such a latch clock d can be easily created by counting the preset signal c.

Now, returning to the description when the first count-up clock is input to the address generation counter 54, the latch clock d is supplied to the address latch circuit 56 in synchronization with this, so that the address latch circuit 56 operates in the address generation counter 54. 1st address (count value "0") output from
(Corresponding to)). Then, the address generation counter 54 counts the 16 count-up clocks so that the data memory areas 42 _{1 to} 42 ₃ of the video RAM 42 are counted.
When the display data of the first row of is read, the next preset signal c is input to the address generation counter 54. As a result, the first address output from the address latch circuit 56 is set in the address generation counter 54. As a result, the address generation counter 54 is again "0".
Start counting from. Therefore, when the data memory area 42 _{1-42 3} of the first row of the display data reading of the video RAM42 is completed, again, the display data of the same first row is read. The display data of the first line read again in this manner is given to the liquid crystal display 28 via the data horizontal direction allocating section shown in FIG.
It is assigned to the unit display dots of the second line L ₂ shown in the figure.

When the second reading of the display data of the first row is completed, the next preset signal c is given and the address generation counter 54 is set to the first address (count value "0") again. Then, similarly, the display data of the first row of each data memory area 42 _{1 to} 42 ₃ of the video RAM 42 is read. This display data is assigned to the unit display dot of the third line L ₃ shown in FIG. Thus, the video RA
Display data for one line of the data memory area 42 _{1-42 3} M42 is, by being read out repeatedly three times, the first line of the character display of the liquid crystal display 28 is completed.

After the character display on the first line is completed, the second latch clock d is synchronized with the count-up clock b input to the address generation counter 54, and the second latch clock d
While being given to 56, the preset signal c ′ is given to the address generation counter 54. At this time, the address generation counter 54 has the second address corresponding to the count value "16". The second address is latched by the address latch circuit 56, and the address generation counter 54 is set to the second address corresponding to the count value "16" by the preset signal c '. Therefore, the address generation counter 54 continuously counts the count-up clock b from the count value "16". This allows video RAM42
The display data of the second row of each data memory area 42 _{1 to} 42 ₃ is read out. As shown in FIG. 8, this display data is assigned to the unit display dot of the fourth line L ₄ of the liquid crystal display 28.

Then, when the data allocation to the 4th line L ₄ is completed,
The address generation counter 54 is preset to the second address corresponding to the count value "16" by the next preset signal c '. As a result, the address generation counter 54 again counts the count-up clock b from the count value "16", so that the display data of the second row of the video RAM 42 is read again, and the five lines shown in FIG. Assigned to eye L ₅ . Then, as described above, 2 of the video RAM 42
The display data of the second line is read out again and assigned to the sixth line L ₆ of the liquid crystal display 28, whereby the character display of the second line ends.

Thereafter, similarly, the display data of the same line of the video RAM 42 is repeatedly read three times to display one line of characters. FIG. 9E shows the display data repeatedly read out in this way. In the figure, “◯”, “×”, and “Δ” indicate the same display data.

In addition, in the above-mentioned embodiment, since one character display dot is constituted by three sets of unit display dots, the display data of the same row of the video RAM 42 is read three times correspondingly. Therefore, for example, the character display dot is 4
Video RAM4 when configured with a set of unit display dots
The display data of the same row of 2 will be repeatedly read four times.

The configuration for allocating the display data read from the video RAM 42 to the liquid crystal display 28 is not limited to those shown in FIGS. 2 and 3, and various modifications can be made. As long as such a modified example also allocates display data based on reading the same display data from the video RAM 42 multiple times according to the number of unit display dots forming the character display dot. , Included in the present invention.

(Effect of the Invention) As is apparent from the above description, the display control device of the computer system according to the present invention is a unit display dot composed of three dots of R, G, B in the liquid crystal display of the liquid crystal television receiver. Character display dots are formed in a substantially rectangular display area formed by collecting only a plurality of sets, and a memory storing display data to be given to the character display dots is used as a unit display dot forming the character display dot. By accessing the same number of times as the number of sets, the same display data is read from the memory only a plurality of times, and character display is performed by sequentially applying these display data to the unit display dots forming the character display dots. There is.

Therefore, according to the present invention, it is possible to display characters in a size that is easy to read on the liquid crystal display of the liquid crystal television receiver connected to the computer main body.

Further, since the character display dots are composed of the same number of R, G, B dots, respectively, it is possible to perform character display without color deviation.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention, FIG. 2 is a block diagram of a data horizontal allocation section in the display controller 40 of the embodiment, and FIG.
FIG. 4 is a block diagram of a data vertical allocating section in the display controller 40 of the above embodiment, FIG. 4 and FIG.
FIG. 6 is an explanatory diagram of an example of the allocation of unit display dots forming the character display dots, and FIG.
28 is an explanatory diagram of an example of allocating character display dots to 28, FIG. 7 is an explanatory diagram of address arrangement of the video RAM 42 corresponding to FIG. 6, and FIG. 8 is an explanatory diagram of allocation of display data to the liquid crystal display 28 in the embodiment, FIG. 9 is an operation waveform diagram of the data vertical allocating section in the display controller 40 shown in FIG. 3, and FIGS. 10 to 12 are configuration examples of conventional character display dots. 10 ... Liquid crystal television receiver, 12 ... Computer main body, 14 ... Connector, 28 ... Liquid crystal display, 32 ... CPU, 40 ... Display controller, 42 ... Video RAM, 44 _{1 to} 44 ₃ ... Latch circuit, 46 _{1 to} 46 ₃ … Shift register, 48… 3 frequency divider,
50 ... 8 frequency divider circuit, 52 ... Address generation circuit, 54 ... Address generation counter, 56 ... Address latch circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 62-299992 (JP, A) JP 60-134293 (JP, A) JP 63-104588 (JP, A)

Claims (1)

[Claims] 1. A display control device for a computer system, wherein a liquid crystal television receiver is connected to a computer main body to display characters using the liquid crystal television receiver as a display monitor. Character display dots are formed by a display area of a quadrangle formed by assembling a plurality of unit display dots consisting of three dots of R (red), G (green), and B (blue) in the liquid crystal display of the machine. However, by accessing the memory storing the display data to be given to the character display dots by the same number of times as the number of sets of unit display dots forming the character display dots, the same display data can be obtained from the memory only a plurality of times. Character display by reading out and assigning these display data to the unit display dots that make up the character display dots in order The display control device of the computer system according to claim.