JPH059957B2 - - Google Patents

Info

Publication number
JPH059957B2
JPH059957B2 JP63025913A JP2591388A JPH059957B2 JP H059957 B2 JPH059957 B2 JP H059957B2 JP 63025913 A JP63025913 A JP 63025913A JP 2591388 A JP2591388 A JP 2591388A JP H059957 B2 JPH059957 B2 JP H059957B2
Authority
JP
Japan
Prior art keywords
wiring
forming
substrate
electrical components
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63025913A
Other languages
Japanese (ja)
Other versions
JPH01201989A (en
Inventor
Akira Mase
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP63025913A priority Critical patent/JPH01201989A/en
Priority to US07/303,241 priority patent/US4934045A/en
Publication of JPH01201989A publication Critical patent/JPH01201989A/en
Priority to US07/495,758 priority patent/US5072519A/en
Priority to US07/495,757 priority patent/US5025555A/en
Publication of JPH059957B2 publication Critical patent/JPH059957B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4685Manufacturing of cross-over conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/50Fixed connections
    • H01R12/59Fixed connections for flexible printed circuits, flat or ribbon cables or like structures
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0286Programmable, customizable or modifiable circuits
    • H05K1/0287Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】 「技術分野」 本発明は、電気部品等を設ける配線基板に関し
特に電気部品等を複数個装着後に、個々にテスト
を行うことが可能な配線基板の構造に関するもの
である。
[Detailed Description of the Invention] [Technical Field] The present invention relates to a wiring board on which electrical components, etc. are mounted, and particularly relates to a structure of a wiring board that allows testing of a plurality of electrical components, etc., individually after mounting them. .

「従来の技術」 従来、電気部品等を電気回路が描かれた基板上
に装着し、液晶表示装置、イメージセンサー、サ
ーマルプリントヘツド、その他の電子部品を駆動
するための回路を持つ配線基板としてはPボード
が一般に使用されていた。
``Prior Art'' Conventionally, electrical parts and the like are mounted on a board on which electric circuits are drawn, and wiring boards with circuits for driving liquid crystal display devices, image sensors, thermal print heads, and other electronic parts have been used. P-boards were commonly used.

このPボードはエポキシ又はガラスエポキシ樹
脂基板上にエツチング処理等によつて形成された
銅配線とその銅配線上にあけられた電気部品の足
挿入用の穴よりなるもので、この穴に電気部品の
足を挿入しはんだ付け等を施して電気回路に接続
してゆくものであつた。
This P-board consists of copper wiring formed on an epoxy or glass epoxy resin substrate by etching, etc., and holes drilled on the copper wiring for inserting the feet of electrical components. The legs were inserted and connected to the electrical circuit by soldering.

このPボードに設けられた電気回路は電気部品
を装着する以前に、ほぼ共通の配線部分が完成し
ており、電気部品を層装着した後に個々の電気部
品のテスト及び個々の電気部品との接続部のテス
トを行うことができなかつた。
In the electric circuit installed on this P board, the common wiring part is almost completed before the electric parts are installed, and after the electric parts are installed in layers, the individual electric parts are tested and the connections with the individual electric parts are completed. I was unable to test the section.

又、Pボードの電気回路を設け特定の電子部品
を駆動させる時などはPボードと電子部品の間を
接続することが必要となるため、接続部が増し、
不良接続等の新たな問題が生じてきた。
Also, when installing an electric circuit on the P-board and driving a specific electronic component, it is necessary to connect the P-board and the electronic component, so the number of connections increases.
New problems have arisen, such as poor connections.

これに対して、電気部品等を装着する電気回路
をイメージセンサー、液晶表示装置、サーマルヘ
ツド等の電子部品を構成している基板上の一部に
直接電気回路を描き、そして電気部品を装着する
技術も知られている。この方式はPボードを使う
場合に比べて部品点数を減らすことができ、駆動
する電子部品との接続部が不要等の点においてす
ぐれている。
On the other hand, the electric circuit to which the electrical parts are attached is drawn directly on a part of the board that constitutes the electronic parts such as the image sensor, liquid crystal display device, thermal head, etc., and then the electrical parts are attached. The technique is also known. This method is superior in that the number of parts can be reduced compared to the case where a P board is used, and there is no need for a connection part with the electronic parts to be driven.

しかしながらこの方法においてもPボードの場
合と同様に基板上の電気回路に対して電気部品を
装着した後に個々の電気部品について良、不良の
テスト及び電気部品の装着時の接続部の良、不良
のテストを行うことができなかつた。さらにまた
共通の配線に対して複数個の電気部品を接続する
ためには多層配線が必要となり製造工程を複雑に
していた。
However, in this method as well, as in the case of P-boards, after the electrical components are mounted on the electrical circuit on the board, each electrical component is tested to see if it is good or bad, and the connections are tested to see if the connections are good or bad when the electrical components are mounted. I couldn't do the test. Furthermore, in order to connect a plurality of electrical components to a common wiring, multilayer wiring is required, complicating the manufacturing process.

第2図にこの従来装置の多層配線部分の製造方
法の概略を示す。
FIG. 2 schematically shows a method for manufacturing the multilayer wiring portion of this conventional device.

第2図Aに示されたように基盤1上に共通配線
15をウエツトエツチング法等により導電性(例
えば銅、ITO等)により形成する。
As shown in FIG. 2A, a common wiring 15 is formed on the substrate 1 using a conductive material (for example, copper, ITO, etc.) by wet etching or the like.

次に絶縁膜を銅図Bに示すパターンに形成す
る。ここで16は共通配線15と枝分かれ配線1
7との接続を行うコンタクトホールであります。
次の同図Cに示すように枝分かれ配線17を形成
し、この枝分かれ配線17に、電気部品を装着す
るものであります。
Next, an insulating film is formed in the pattern shown in Figure B. Here, 16 is the common wiring 15 and the branch wiring 1
This is a contact hole for connection with 7.
As shown in the following figure C, a branched wiring 17 is formed, and electrical components are attached to this branched wiring 17.

このような多層配線部分において枝分かれ配線
17がコンタクトホール16で共通配線15と接
続するためにはコンタクトホール16の寸法に限
定が必要となる。しかしながら、装着する電気部
品の端子の数が多くなつた場合又は、電気部品の
数が増した場合、コンタクトホール16の寸法の
小さくしなければならず、コンタクト不良が発生
した、特に印刷法にて絶縁層を形成する場合はコ
ストを安くできるという利点はあるがコンタクト
ホールが形成できないという技術的な問題があつ
た。
In order to connect the branched wiring 17 to the common wiring 15 through the contact hole 16 in such a multilayer wiring part, it is necessary to limit the size of the contact hole 16. However, when the number of terminals of the electrical components to be installed increases, or when the number of electrical components increases, the dimensions of the contact hole 16 must be reduced, and contact failure occurs, especially when using the printing method. Forming an insulating layer has the advantage of reducing costs, but has the technical problem of not being able to form contact holes.

「発明の構成」 本発明は前述の如き配線基板の新規な構造に関
するものであり、特に一部の多層配線部品を有す
る配線基板で前述のような問題点が改善された物
であります。
"Structure of the Invention" The present invention relates to a novel structure of a wiring board as described above, and in particular, it is a wiring board having some multilayer wiring components, which improves the problems described above.

すなわち絶縁基板上に複数の共通配線が設けら
れており、その共通配線より枝分かれした配線と
この枝分かれした配線に電気部品が装着可能な構
成を有するものであり、電気部品装着後に個々の
部品の検査を行うことができるものであります。
In other words, a plurality of common wirings are provided on an insulating board, and the configuration is such that wiring branches from the common wiring and electrical components can be attached to these branched wirings, and each individual component can be inspected after the electrical components are mounted. It is something that can be done.

以下に一例を示す図面を用いて本発明を説明す
る。
The present invention will be explained below using drawings showing an example.

第1図に本発明の新規な配線基板の作製方法の
一例を示す。
FIG. 1 shows an example of the method for manufacturing the novel wiring board of the present invention.

絶縁性表面を有する基板上1上に第1の配線群
2を導電性材料で形成する。(同図A)この時第
1の配線群2は1つの電気部品3(例えばICチ
ツプ)に対しては1かたまりの配線群となつてお
り、隣の電気部品が接続される第1の配線群2′
とは接続されていない。この状態でもし電気部品
を第1の配線群2に装着した場合、個々の電気部
品について検査を行うことができる。もし不良で
あればこの段階で不良の電気部品を取りはずし新
たに電気部品を付け再度検査することが可能とな
る。次にこの第1の配線群の少なくとも一部をお
おつて層間絶縁膜4を形成する(同図B)。その
次にこの絶縁膜4上を越えて第1の配線群と同じ
ピツチと巾で第2配線群5を形成し、第1の配線
群2と2′とを相互接続し共通配線群を完成させ
る。このようにして共通配線群と共通配線群より
枝分かれした配線群とを有する配線基盤を構成す
ることができる。
A first wiring group 2 is formed of a conductive material on a substrate 1 having an insulating surface. (Figure A) At this time, the first wiring group 2 is a single wiring group for one electrical component 3 (for example, an IC chip), and the first wiring group 2 is connected to the adjacent electrical component. group 2'
is not connected. If electrical components are attached to the first wiring group 2 in this state, each electrical component can be inspected. If it is defective, it is possible to remove the defective electrical component at this stage, attach a new electrical component, and re-inspect. Next, an interlayer insulating film 4 is formed covering at least a portion of this first wiring group (FIG. 3B). Next, a second wiring group 5 is formed over this insulating film 4 with the same pitch and width as the first wiring group, and the first wiring groups 2 and 2' are interconnected to complete a common wiring group. let In this way, a wiring base having a common wiring group and wiring groups branched from the common wiring group can be constructed.

本発明は共通配線群、すなわち電気部品が接続
されている配線群が複数個相互に接続されて形成
している物を最初から共用させて形成するのでは
なく最初は個々の電気部品に対して1つの配線群
を形成し、次に必要部分に絶縁膜を形成し、最後
に1つの電気部品に対する1つの配線群を相互接
続することにより共通配線群を設けるものであ
り、このような構成をとることにより特に電気回
路に装着される電気部品の検査を1つづつ行うこ
とができるという特徴を持つ。
The present invention does not form a common wiring group, that is, a wiring group to which electrical components are connected, which is formed by interconnecting a plurality of wiring groups, from the beginning. A common wiring group is provided by forming one wiring group, then forming an insulating film on the necessary parts, and finally interconnecting one wiring group for one electric component. In particular, this feature allows inspection of electrical components installed in an electrical circuit one by one.

以下に実施例を示し本発明を詳述する。 The present invention will be explained in detail with reference to Examples below.

実施例 1 本実施例は、本発明を液晶表示装置に応用した
例を示す。
Example 1 This example shows an example in which the present invention is applied to a liquid crystal display device.

第3図に本実施例の基板の作製方法の概略を示
す。
FIG. 3 shows an outline of the method for manufacturing the substrate of this example.

本実施例では使用する基板1として青板硝子を
使用した。この硝子基板は後述のように液晶表示
装置のセルをも兼ねるので高平坦性の硝子を使用
した。
In this example, blue plate glass was used as the substrate 1 used. Since this glass substrate also serves as a cell of a liquid crystal display device as will be described later, highly flat glass was used.

この硝子基板上に公知のスパツタ法、蒸着法等
によりITO(酸化インジユーム、スズ)導電膜を
形成し、そのITO膜を基板1の大部分を占める液
晶表示領域は、マトリクス構成となるように電極
6をパターニング、残りの基板の端部に液晶表示
駆動回路を構成する第1の電極群7を同時に形成
した。
An ITO (indium oxide, tin) conductive film is formed on this glass substrate by a well-known sputtering method, evaporation method, etc., and the ITO film is used as electrodes in a matrix configuration for the liquid crystal display area that occupies most of the substrate 1. 6 was patterned, and a first electrode group 7 constituting a liquid crystal display drive circuit was simultaneously formed on the remaining end of the substrate.

本実施例ではウエツトエツチング法にて、電極
6及び第1の電極群7を形成した。
In this example, the electrode 6 and the first electrode group 7 were formed by wet etching.

第3図Aにはこの状態の基板1の端部付近の概
略図を示すものであり、第1の電極群7は2つ分
しか描かれていなが、さらに多数分が設けられて
いる。
FIG. 3A shows a schematic diagram of the vicinity of the end of the substrate 1 in this state, and although only two first electrode groups 7 are shown, many more are provided.

この時第1の配線群7はまだいずれの他の配線
部分とも接続されておらず独立した状態となつて
いる。
At this time, the first wiring group 7 is not yet connected to any other wiring portion and is in an independent state.

次に第1の配線群7の電気部品接続部分8に液
晶表示装置駆動用の集積回路のチツプ9を直接フ
エイスダウンボンデイングを行う。この時チツプ
9と基板1との接着は紫外線硬化タイプな接着剤
を使用し温度150℃で、約3Kgのプレス圧を加え
3分間、波長365nmの紫外線を照射し硬化した。
この状態を第3図Bに示す。この状態では1つの
チツプ9に対して第1の電極群7が独立して設け
られている。
Next, a chip 9 of an integrated circuit for driving a liquid crystal display device is directly face-down bonded to the electrical component connecting portion 8 of the first wiring group 7. At this time, the adhesive between the chip 9 and the substrate 1 was cured by using an ultraviolet curing type adhesive at a temperature of 150°C, applying a press pressure of about 3 kg, and irradiating ultraviolet rays with a wavelength of 365 nm for 3 minutes.
This state is shown in FIG. 3B. In this state, the first electrode group 7 is independently provided for one chip 9.

この際に、この独立した第1の電極群7を検査
用の取り出し端子として、液晶表示装置駆動用の
集積回路チツプ9の検査とフエイスダウンボンデ
イングの接続部の検査を行う。良品又は接続部が
良の場合はよいが不良品又は接続部が不良の場合
は一度接着したチツプ9を除去し再度別のチツプ
を取りつけ再び検査を行う。
At this time, the independent first electrode group 7 is used as an extraction terminal for inspection to inspect the integrated circuit chip 9 for driving the liquid crystal display device and the face-down bonding connection portion. If it is a good product or the connection part is good, it is good, but if it is a defective product or the connection part is defective, the chip 9 that has been bonded once is removed, another chip is attached, and the test is performed again.

このようにすることにより液晶表示装置の製造
歩留を向上させることができた。
By doing so, it was possible to improve the manufacturing yield of the liquid crystal display device.

次に多層配線部分の層間絶縁膜10を必要部分
にスクリーン印刷法で形成した。材料はエポキシ
樹脂を用い厚さ40〜50μmで第3図Cに示すよう
な形状で印刷し180℃30分ベークして形成した。
Next, the interlayer insulating film 10 of the multilayer wiring portion was formed in the necessary portions by screen printing. The material used was epoxy resin, which was printed to a thickness of 40 to 50 μm in the shape shown in FIG. 3C, and baked at 180° C. for 30 minutes.

本実施例のような多層配線部の層間絶縁膜の形
状とすることによりコンタクトホールが存在しな
いので印刷の際のマージンを大きくとることが可
能となつた。
By using the shape of the interlayer insulating film of the multilayer interconnection part as in this embodiment, there is no contact hole, so it is possible to have a large margin during printing.

また、この層間絶縁膜のパターンとして第4図
A〜Cに示すような形状でも可である。
Further, the pattern of this interlayer insulating film may have the shapes shown in FIGS. 4A to 4C.

つまり最低限必要部分には層間絶縁膜が設けら
れていればよい。
In other words, it is sufficient that the interlayer insulating film is provided in the minimum required portion.

また、この層間絶縁膜の形成工程を、終えた後
に集積回路チツプ9を実装する工程、検査をする
工程を行つてもよい。
Further, after the step of forming the interlayer insulating film is completed, the step of mounting the integrated circuit chip 9 and the step of inspecting it may be performed.

次にこの層間絶縁膜上を渡つて、独立した第1
の配線群7に接続する第2の配線群11を形成
し、第1の配線群7を相互に接続し、共通配線を
構成させる。この様子を第3図Dに示す。
Next, the independent first
A second wiring group 11 connected to the wiring group 7 is formed, and the first wiring group 7 is connected to each other to form a common wiring. This situation is shown in FIG. 3D.

この第2の配線群11は、銅ペーストをスクリ
ーン印刷法によりパターンどおりに印刷した後、
180℃20分のベークを行つて形成した。
This second wiring group 11 is made by printing copper paste according to the pattern by screen printing method, and then
It was formed by baking at 180°C for 20 minutes.

さらに、これら基板の端部付近全面に保護膜を
形成した。
Furthermore, a protective film was formed on the entire surface near the edges of these substrates.

このようにして、硝子基板上に電気回路を有し
電気部品が装着された配線基板を完成することが
できた。
In this way, it was possible to complete a wiring board having an electrical circuit on a glass substrate and having electrical components mounted thereon.

この基板とほぼ同様の工程でもう一方の基板を
作製し、両基板に液晶表示装置として必要な処理
を施した後に2つの基板1を重ね合わせ、間にギ
ヤツプ間隔を一定に保つスペーサをはさんでその
外周をシールし液晶セルを完成し、その空間に液
晶材料を注入し液晶表示装置を完成させた。
The other substrate is manufactured using almost the same process as this substrate, and after both substrates are subjected to the necessary processing for a liquid crystal display device, the two substrates 1 are stacked, and a spacer is inserted between them to keep the gap distance constant. The outer periphery was sealed to complete the liquid crystal cell, and liquid crystal material was injected into the space to complete the liquid crystal display device.

本実施例において液晶表示装置の基板1上の電
極6のパターニングは従来より公知のエツチング
法でもよいが本出願人が出願している特願昭61−
18602号に記載のようにエキシマレーザーを用い
たパターニングを行つてもよい。
In this embodiment, the patterning of the electrode 6 on the substrate 1 of the liquid crystal display device may be performed by a conventionally known etching method, but the patent application filed by the present applicant in 1983-
Patterning may be performed using an excimer laser as described in No. 18602.

この場合はウエツト工程を用いないためその工
程コスト材料コストを削減できる。
In this case, since a wet process is not used, the process cost and material cost can be reduced.

またこの場合には第1の配線群7も第2の配線
群11同様に印刷法にて形成してもよい。
Further, in this case, the first wiring group 7 may also be formed by a printing method like the second wiring group 11.

実施例 2 本実施例では、本発明の構成をイメージセンサ
ーに応用した場合を記載する。
Example 2 This example describes a case where the configuration of the present invention is applied to an image sensor.

基板1上に所定のパターニングを施した第1の
導電膜12と、光電変換を行う半導体層13と第
2の導電膜14とを従来公知の技術を用いて形成
されたセンサーアレイの基板1の端部付近にセン
サーアレイ駆動用の電気回路を設ける。そのため
にスクリーン印刷法により銅ペーストを用いて第
1の配線群のパターンを形成する。
A first conductive film 12 patterned in a predetermined manner on a substrate 1, a semiconductor layer 13 for photoelectric conversion, and a second conductive film 14 are formed on the substrate 1 of a sensor array using a conventionally known technique. An electric circuit for driving the sensor array is provided near the end. For this purpose, a pattern of the first wiring group is formed using copper paste by a screen printing method.

この時第1の配線群7とセンサーアレイの第1
の導電膜又は第2の導電膜とは位置合わせを行つ
て一部接続させる。
At this time, the first wiring group 7 and the first wiring group 7 of the sensor array
The conductive film or the second conductive film is aligned and partially connected.

次にこの印刷された基板をベークして銅ペース
トを焼き固め配線を形成する。この時の温度はセ
ンサーに使用されている材料が影響を受けない程
度好ましくは200℃以下で焼成することが好まし
い。
Next, this printed board is baked to harden the copper paste and form wiring. The temperature at this time is preferably 200° C. or lower to the extent that the material used in the sensor is not affected.

次にこの第1の配線群7の少なくとも一部をお
おつて層間絶縁膜10を実施例1と同様の方法で
形成した後に第1の配線群7にイメージセンサー
駆動用のIC9をフエースダウンボンデイングし
て接続し、IC9及びIC9と第1の配線群7との
接続部分の検査を行つた。
Next, after forming an interlayer insulating film 10 covering at least a portion of this first wiring group 7 in the same manner as in Example 1, an IC 9 for driving an image sensor is face-down bonded to the first wiring group 7. The IC 9 and the connection portion between the IC 9 and the first wiring group 7 were inspected.

この際ICチツプ9と基板1との接続は仮接着
の状態とし、ICの検査を行い不良がなければ完
全接着を行い不良があれば一度ICチツプ9をは
ずし再度接続を行い完全接着を行つた。
At this time, the connection between the IC chip 9 and the substrate 1 was temporarily bonded, and the IC was inspected and if there were no defects, the bonding was completed. If there were any defects, the IC chip 9 was removed and the connection was made again to achieve complete bonding. .

このようにすることにより不良の場合ICチツ
プを取りはずす際に同時に第1の配線群をも誤つ
て除去する事故の発性をなくすることができ、よ
り製造を歩留を向上させることが可能となつた。
By doing this, it is possible to eliminate the possibility of accidental removal of the first wiring group at the same time when removing a defective IC chip, and it is possible to further improve manufacturing yield. Summer.

その後、第2の配線群の印刷、保護膜の印刷等
を実施例1と同じ条件にて行いイメージセンサー
を完成させた。
Thereafter, printing of a second wiring group, printing of a protective film, etc. were performed under the same conditions as in Example 1 to complete an image sensor.

本発明はその他の電気、電子部品に巾広く応用
できることは言うまでもないが、前述の実施例
1、2に示すようにCOG(チツプオングラス)、
COB(チツプオンボード)等の技術を用いてICチ
ツプを直接に基板上に設ける際に応用すると製造
コスト、製造工程の削減に顕著な効果を得ること
が可能となつた。
It goes without saying that the present invention can be widely applied to other electrical and electronic components, but as shown in Examples 1 and 2 above, COG (chip-on-glass),
Applying technology such as COB (chip on board) to the mounting of IC chips directly on a substrate has made it possible to achieve remarkable effects in reducing manufacturing costs and manufacturing processes.

〔効果〕〔effect〕

本発明の構成を有することにより従来では不可
能であつた電気回路に装着された電気部品の検査
を製造が完成する以前に行い、その良、不良の判
定を行うことができ、製品の歩留りを格段に向上
させることができた。
By having the configuration of the present invention, it is possible to inspect the electrical components installed in the electrical circuit before the manufacturing is completed, which was impossible in the past, and determine whether the components are good or defective, thereby improving the yield of the product. I was able to improve it significantly.

また、共通配線と枝分かれ配線とを接続するコ
ンタクトホールを全くなくすることができるか、
その大きさを大きくすることができるのでその製
造工程での位置合わせの精度に余裕が生じる。
Also, is it possible to completely eliminate contact holes that connect common wiring and branch wiring?
Since the size can be increased, there is a margin for alignment accuracy in the manufacturing process.

また、配線の位置合わせ精度に余裕が生じるた
め各配線をすべてスクリーン印刷にて行うことが
でき、その製造コストが格段に下げることができ
た。
Furthermore, since there is a margin in the alignment accuracy of the wiring, all wiring can be done by screen printing, making it possible to significantly reduce the manufacturing cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第3図は本発明の概略製造工程の様子
を示す。第2図は従来の配線基板の多層配線部の
様子。第4図は本発明の層間絶縁膜のパターンの
例を示す。 1……基板、2,7……第1の配線群、5,1
1……第2の配線群、10……層間絶縁膜、9…
…ICチツプ。
FIGS. 1 and 3 schematically show the manufacturing process of the present invention. Figure 2 shows the multilayer wiring section of a conventional wiring board. FIG. 4 shows an example of the pattern of the interlayer insulating film of the present invention. 1... Board, 2, 7... First wiring group, 5, 1
DESCRIPTION OF SYMBOLS 1... Second wiring group, 10... Interlayer insulating film, 9...
...IC chip.

Claims (1)

【特許請求の範囲】 1 絶縁表面を有する基板上に複数の電気部品に
入力信号を与えるための複数の第1の配線を形成
する工程と前記第1の配線の少なくとも1部分を
おおつて絶縁層を形成する工程と前記絶縁層上及
び該層より延在して複数の第2の配線を形成し前
記第1の配線と電気的に接続することにより共通
配線を形成する工程と前記複数の第2の配線を形
成し共通配線を完成する以前に電気部品を基板上
の所定の位置に装着し電気部品又は電気部品の接
続部の検査を行う工程を有することを特徴とする
絶縁基板上の配線形成方法。 2 前記特許請求の範囲第1項において第1の配
線、第2の配線、及び絶縁層はすべて印刷法によ
つて形成されることを特徴とする絶縁基板上の配
線形成方法。 3 前記特許請求の範囲第1項において第1の配
線はフオトリソグラフイを用いた方法により形成
され、第2の配線及び絶縁層は印刷によつて形成
されることを特徴とする絶縁基板上の配線形成方
法。 4 絶縁表面を有する基板上に複数の電気部品に
入力信号を与えるための複数の第1の配線を形成
する工程と前記第1の配線の少なくとも1部分を
覆つて絶縁層を形成する工程と、前記絶縁層上及
び該層より延在して、複数の第2の配線を形成
し、前記第1の配線と電気的に接続することによ
り共通配線を形成する工程と、前記複数の第2の
配線を形成し共通配線を完成する以前に、電気部
品を基板上の所定の位置に仮止めし電気部品また
は電気部品の接続部の検査を行う工程と、前記電
気部品を完全に装着する工程を有することを特徴
とする絶縁基板上の配線形成方法。 5 前記特許請求の範囲第4項において、第1の
配線、第2の配線、及び絶縁層はすべて印刷法に
よつて形成されることを特徴とする絶縁基板上の
配線形成方法。 6 前記特許請求の範囲第4項において、第1の
配線はフオトリソグラフイを用いた方法により形
成され、第2の配線及び絶縁層は、印刷法によつ
て形成されることを特徴とする絶縁基板上の配線
形成方法。
[Claims] 1. A step of forming a plurality of first wirings for supplying input signals to a plurality of electrical components on a substrate having an insulating surface, and forming an insulating layer covering at least a portion of the first wirings. forming a common wiring by forming a plurality of second wirings on and extending from the insulating layer and electrically connecting to the first wiring; 2. Wiring on an insulating substrate characterized by having a step of mounting an electrical component on a predetermined position on the substrate and inspecting the electrical component or the connection part of the electrical component before forming the second wiring and completing the common wiring. Formation method. 2. The method for forming wiring on an insulating substrate according to claim 1, wherein the first wiring, the second wiring, and the insulating layer are all formed by a printing method. 3. In claim 1, the first wiring is formed by a method using photolithography, and the second wiring and the insulating layer are formed by printing, on an insulating substrate. Wiring formation method. 4. A step of forming a plurality of first wirings for providing input signals to a plurality of electrical components on a substrate having an insulating surface, and a step of forming an insulating layer covering at least a portion of the first wirings, forming a plurality of second wirings on and extending from the insulating layer, and forming a common wiring by electrically connecting with the first wiring; Before forming the wiring and completing the common wiring, there are two steps: temporarily fixing the electrical components in a predetermined position on the board, inspecting the electrical components or the connections of the electrical components, and completely mounting the electrical components. A method for forming wiring on an insulating substrate, comprising: 5. The method for forming wiring on an insulating substrate according to claim 4, wherein the first wiring, the second wiring, and the insulating layer are all formed by a printing method. 6. The insulating material according to claim 4, wherein the first wiring is formed by a method using photolithography, and the second wiring and the insulating layer are formed by a printing method. A method of forming wiring on a board.
JP63025913A 1988-02-03 1988-02-05 Wiring construction on glass substrate Granted JPH01201989A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP63025913A JPH01201989A (en) 1988-02-05 1988-02-05 Wiring construction on glass substrate
US07/303,241 US4934045A (en) 1988-02-05 1989-01-30 Method of producing electric circuit patterns
US07/495,758 US5072519A (en) 1988-02-03 1990-03-19 Method of producing electric circuit patterns
US07/495,757 US5025555A (en) 1988-02-05 1990-03-19 Method of producing electric circuit patterns

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63025913A JPH01201989A (en) 1988-02-05 1988-02-05 Wiring construction on glass substrate

Publications (2)

Publication Number Publication Date
JPH01201989A JPH01201989A (en) 1989-08-14
JPH059957B2 true JPH059957B2 (en) 1993-02-08

Family

ID=12179016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63025913A Granted JPH01201989A (en) 1988-02-03 1988-02-05 Wiring construction on glass substrate

Country Status (1)

Country Link
JP (1) JPH01201989A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100644804B1 (en) * 1999-11-16 2006-11-13 삼성전자주식회사 Liquid crystal display device and method for assembling the thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5427957A (en) * 1977-08-03 1979-03-02 Canon Kk Multiilayer wiring
JPS582037A (en) * 1981-06-29 1983-01-07 Oki Electric Ind Co Ltd Mounting method for ic and the like

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5427957A (en) * 1977-08-03 1979-03-02 Canon Kk Multiilayer wiring
JPS582037A (en) * 1981-06-29 1983-01-07 Oki Electric Ind Co Ltd Mounting method for ic and the like

Also Published As

Publication number Publication date
JPH01201989A (en) 1989-08-14

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