JPH01201988A - Printed-wiring board - Google Patents
Printed-wiring boardInfo
- Publication number
- JPH01201988A JPH01201988A JP63025912A JP2591288A JPH01201988A JP H01201988 A JPH01201988 A JP H01201988A JP 63025912 A JP63025912 A JP 63025912A JP 2591288 A JP2591288 A JP 2591288A JP H01201988 A JPH01201988 A JP H01201988A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring group
- electrical parts
- common
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000009413 insulation Methods 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 abstract description 3
- 238000007689 inspection Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 21
- 239000004973 liquid crystal related substance Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000007639 printing Methods 0.000 description 6
- 230000002950 deficient Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000005357 flat glass Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4685—Manufacturing of cross-over conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
- H01R12/50—Fixed connections
- H01R12/59—Fixed connections for flexible printed circuits, flat or ribbon cables or like structures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
- H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
- H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
「技術分野」
本発明は、電気部品等を設ける配線基板に関し特に電気
部品等を複数個装着後に、個々にテストを行うことが可
能な配線基板の構造に関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a wiring board on which electrical components, etc. are mounted, and particularly relates to a structure of a wiring board that allows testing of a plurality of electrical components, etc., individually after mounting them. .
「従来の技術」
従来、電気部品等を電気回路が描かれた基板上に装着し
、液晶表示装置、イメージセンサ−、サーマルプリント
ヘッド、その他の電子部品を駆動するための回路を持つ
配線基板としてはPボードが一般に使用されていた。"Conventional Technology" Conventionally, electrical components and the like are mounted on a board on which electrical circuits are drawn, and it is used as a wiring board with circuits for driving liquid crystal display devices, image sensors, thermal print heads, and other electronic components. P-boards were generally used.
このPボードはエポキシ又はガラスエポキシ樹脂基板上
にエツチング処理等によって形成された銅配線とその銅
配線上にあけられた電気部品の足挿入用の穴よりなるも
ので、この穴に電気部品の足を挿入しはんだ付は等を施
して電気回路に接続してゆくものであった。This P-board consists of copper wiring formed on an epoxy or glass epoxy resin substrate by etching, etc., and holes drilled on the copper wiring for inserting the feet of electrical components. This involved inserting the wire, soldering it, etc., and connecting it to the electrical circuit.
このPボードに設けられた電気回路は電気部品を装着す
る以前に、はぼ共通の配線部分が完成しており、電気部
品を装着した後に個々の電気部品のテスト及び個々の電
気部品との接続部のテストを行うことができなかった。In the electric circuit installed on this P board, the common wiring part has been completed before the electric parts are installed, and after the electric parts are installed, the individual electric parts are tested and the connections with the individual electric parts are completed. It was not possible to test the section.
又、Pボードの電気回路を設は特定の電子部品を駆動さ
せる時などはPボードと電子部品の間を接続することが
必要となるため、接続部が増し、不良接続等の新たな問
題が生じてきた。In addition, when setting up an electrical circuit on the P-board, it is necessary to connect the P-board and electronic components when driving a specific electronic component, which increases the number of connections and creates new problems such as poor connections. It has arisen.
これに対して、電気部品等を装着する電気回路をイメー
ジセンサ−1液晶表示装置、サーマルヘッド等の電子部
品を構成している基板上の一部に直接電気回路を描き、
そして電気部品を装着する技術も知られている。この方
式はPボードを使う場合に比べて部品点数を減らすこと
ができ、駆動する電子部品との接続部が不要等の点にお
いてすぐれている。On the other hand, an electric circuit for mounting electric parts, etc. is drawn directly on a part of the board that constitutes the electronic parts such as the image sensor-1 liquid crystal display device and the thermal head.
Techniques for attaching electrical components are also known. This method is superior in that the number of parts can be reduced compared to the case where a P board is used, and there is no need for a connection part with the electronic parts to be driven.
しかしながらこの方法においてもPボードの場合と同様
に基板上の電気回路に対して電気部品を装着した後に個
々の電気部品について良、不良のテスト及び電気部品の
装着時の接続部の良、不良のテストを行うことができな
かった。さらにまた共通の配線に対して複数個の電気部
品を接続するためには多層配線が必要となり製造工程を
複雑にしていた。However, in this method as well, as in the case of P-boards, after the electrical components are mounted on the electrical circuit on the board, each electrical component is tested to see if it is good or bad, and the connections are tested to see if the connections are good or bad when the electrical components are mounted. Couldn't do the test. Furthermore, in order to connect a plurality of electrical components to a common wiring, multilayer wiring is required, complicating the manufacturing process.
第2図にこの従来装置の多層配線部分の製造方法の概略
を示す。FIG. 2 schematically shows a method for manufacturing the multilayer wiring portion of this conventional device.
第2図(A)に示されたように基板(1)上に共通配線
θつをウェットエツチング法等により導電性(例えば銅
、IT○等)により形成する。As shown in FIG. 2A, common wiring lines θ are formed on the substrate (1) using a conductive material (for example, copper, IT◯, etc.) by wet etching or the like.
次に絶縁膜を同図(B)に示すパターンに形成する。こ
こで00は共通配線(151と枝分かれ配線qでとの接
続を行うコンタクトホールであります。 次に同図(C
)に示すように枝分かれ配線0′l)を形成し、この枝
分かれ配線07)に、電気部品を装着するものでありま
す。Next, an insulating film is formed in the pattern shown in FIG. Here, 00 is a contact hole that connects the common wiring (151) with the branch wiring q.
), a branched wiring 0'l) is formed, and electrical components are attached to this branched wiring 07).
このような多層配線部分において枝分かれ配線θ力がコ
ンタクトホール06)で共通配線q5)と接続するため
にはコンタクトホール06)の寸法に限定が必要となる
。しかしながら、装着する電気部品の端子の数が多くな
った場合又は、電気部品の数が増した場合、コンタクト
ホール06)の寸法を小さくしなければならず、コンタ
クト不良が発生した、特に印刷法にて絶縁層を形成する
場合はコストを安くできるという利点はあるがコンタク
トホールが形成できないという技術的な問題があった。In order to connect the branch wiring θ force to the common wiring q5) through the contact hole 06) in such a multilayer wiring part, it is necessary to limit the dimensions of the contact hole 06). However, when the number of terminals of the electrical components to be installed increases, or when the number of electrical components increases, the dimensions of the contact hole 06) must be made smaller, resulting in poor contact, especially in printing methods. Forming an insulating layer using the same method has the advantage of reducing costs, but there is a technical problem in that contact holes cannot be formed.
「発明の構成」
本発明は前述の如き配線基板の新規な構造に関するもの
であり、特に一部の多層配線部品を有する配線基板で前
述のような問題点が改善された物であります。"Structure of the Invention" The present invention relates to a novel structure of a wiring board as described above, and in particular, it is a wiring board having some multilayer wiring components, which improves the problems described above.
すなわち絶縁基板上に複数の共通配線が設けられており
、その共通配線より枝分かれした配線とこの枝分かれし
た配線に電気部品が装着可能な構成を有するものであり
、電気部品装着後に個々の部品の検査を行うことができ
るものであります。In other words, a plurality of common wirings are provided on an insulating board, and the configuration is such that wiring branches from the common wiring and electrical components can be attached to these branched wirings, and each individual component can be inspected after the electrical components are mounted. It is something that can be done.
以下に一例を示す図面を用いて本発明を説明する。The present invention will be explained below using drawings showing an example.
第1図に本発明の新規な配線基板の作製方法の一例を示
す。FIG. 1 shows an example of the method for manufacturing the novel wiring board of the present invention.
絶縁性表面を有する基板上(1)上に第1の配線群(2
)を導電性材料で形成する。(同図(A))この時第1
の配線群(2)は1つの電気部品(3)(例えばICチ
ップ)に対しては1かたまりの配線群となっており、隣
の電気部品が接続される第1の配線群(2′)とは接続
されていない。この状態でもし電気部品を第1の配線群
(2)に装着した場合、個々の電気部品について検査を
行うことができる。もし不良であればこの段階で不良の
電気部品を取りはずし新たに電気部品を付は再度検査す
ることが可能となる。 次にこの第1の配線群の少なく
とも一部をおおって層間絶縁膜(4)を形成する(同図
(B))。その次にこの絶縁膜(4)上を越えて第1の
配線群と同じピッチと巾で第2配線群(5)を形成し、
第1の配線群(2)と(2”)とを相互接続し共通配線
群を完成させる。このようにして共通配線群と共通配線
群より枝分かれした配線群とを有する配線基板を構成す
ることができる。A first wiring group (2) is placed on a substrate (1) having an insulating surface.
) is made of conductive material. (Same figure (A)) At this time, the first
The wiring group (2) is a single wiring group for one electrical component (3) (for example, an IC chip), and is the first wiring group (2') to which the adjacent electrical component is connected. is not connected. If electrical components are attached to the first wiring group (2) in this state, each electrical component can be inspected. If it is defective, it is possible to remove the defective electrical component at this stage, attach a new electrical component, and inspect it again. Next, an interlayer insulating film (4) is formed to cover at least a portion of this first wiring group (FIG. 3(B)). Next, a second wiring group (5) is formed over the insulating film (4) with the same pitch and width as the first wiring group,
The first wiring group (2) and (2'') are interconnected to complete a common wiring group. In this way, a wiring board having a common wiring group and wiring groups branched from the common wiring group is constructed. Can be done.
本発明は共通配線群、すなわち電気部品が接続されてい
る配線群が複数個相互に接続されて形成している物を最
初から共用させて形成するのではなく最初は個々の電気
部品に対して1つの配線群を形成し、次に必要部分に絶
縁膜を形成し、最後に1つの電気部品に対する1つの配
線群を相互接続することにより共通配線群を設けるもの
であり、このような構成をとることにより特に電気回路
に装着される電気部品の検査を1つづつ行うことができ
るという特徴を持つ。The present invention does not form a common wiring group, that is, a wiring group to which electrical components are connected, which is formed by interconnecting a plurality of wiring groups, from the beginning. A common wiring group is provided by forming one wiring group, then forming an insulating film on the necessary parts, and finally interconnecting one wiring group for one electric component. In particular, this feature allows inspection of electrical components installed in an electrical circuit one by one.
以下に実施例を示し本発明を詳述する。The present invention will be explained in detail by way of examples below.
〔実施例1〕
本実施例は、本発明を液晶表示装置に応用した例を示す
。[Example 1] This example shows an example in which the present invention is applied to a liquid crystal display device.
第3図に本実施例の基板の作製方法の概略を示す。FIG. 3 shows an outline of the method for manufacturing the substrate of this example.
本実施例では使用する基板(1)として青板硝子を使用
した。この硝子基板は後述のように液晶表示装置のセル
をも兼ねるので高平坦性の硝子を使用した。In this example, soda lime glass was used as the substrate (1). Since this glass substrate also serves as a cell of a liquid crystal display device as will be described later, highly flat glass was used.
この硝子基板上に公知のスパッタ法、蒸着法等によりI
T○(酸化インジューム、スズ)導電膜を形成し、その
IT○膜を基板(1)の大部分を占める液晶表示領域は
、マトリクス構成となるように電極(6)をパターニン
グ、残りの基板の端部に液晶表示駆動回路を構成する第
1の電極群(7)を同時に形成した。I was deposited on this glass substrate by a known sputtering method, vapor deposition method, etc.
A T○ (indium oxide, tin) conductive film is formed, and the IT○ film is used to pattern the electrodes (6) in a matrix configuration for the liquid crystal display area that occupies most of the substrate (1). At the same time, a first electrode group (7) constituting a liquid crystal display drive circuit was formed at the end of the electrode.
本実施例ではウェットエツチング法にて、電極(6)及
び第1の電極群(7)を形成した。In this example, the electrode (6) and the first electrode group (7) were formed by wet etching.
第3図(A)にはこの状態の基板(1)の端部付近の概
略回を示すものであり、第1の電極群(7)は2っ分し
か描かれてないが、さらに多数骨が設けられている。Figure 3 (A) shows a rough view of the vicinity of the end of the substrate (1) in this state, and although only two portions of the first electrode group (7) are drawn, there are many more bones. is provided.
この時第1の配線群(7)はまだいずれの他の配線部分
とも接続されておらず独立した状態となっている。At this time, the first wiring group (7) is not yet connected to any other wiring portion and is in an independent state.
次に第1の配線群(7)の電気部品接続部分(8)に液
晶表示装置駆動用の集積回路のチップ(9)を直接フェ
イスダウンボンディングを行う。この時チップ(9)と
基板(1)との接着は紫外線硬化タイプの接着剤を使用
し温度150°Cで、約3Kgのプレス圧を加え3分間
、波長365nmの紫外線を照射し硬化した。 この状
態を第3図(B)に示す。この状態では1つのチップ(
9)に対して第1の電極群(7)が独立して設けられて
いる。Next, a chip (9) of an integrated circuit for driving a liquid crystal display device is directly face-down bonded to the electrical component connecting portion (8) of the first wiring group (7). At this time, the adhesive between the chip (9) and the substrate (1) was cured using an ultraviolet curing type adhesive at a temperature of 150° C. by applying a press pressure of about 3 kg and irradiating ultraviolet rays with a wavelength of 365 nm for 3 minutes. This state is shown in FIG. 3(B). In this state, one chip (
9), a first electrode group (7) is provided independently.
この際に、この独立した第1の電極群(7)を検査用の
取り出し端子として、液晶表示装置駆動用の集積回路チ
ップ(9)の検査とフェイスダウンボンディングの接続
部の検査を行う。良品又は接続部が良の場合はよいが不
良品又は接続部が不良の場合は一度接着したチップ(9
)を除去し再度別のチップを取りつけ再び検査を行う。At this time, the independent first electrode group (7) is used as an extraction terminal for inspection, and the integrated circuit chip (9) for driving the liquid crystal display device and the face-down bonding connection portion are inspected. If it is a good product or the connection part is good, it is fine, but if it is a defective product or the connection part is defective, the chip that has been bonded once (9
), attach another chip, and test again.
このようにすることにより液晶表示装置の製造歩留を向
上させることができた。By doing so, it was possible to improve the manufacturing yield of the liquid crystal display device.
次に多層配線部分の層間絶縁膜00)を必要部分にスク
リーン印刷法で形成した。材料はエポキシ樹脂を用い厚
さ40〜50μmで第3図(C)に示すような形状で印
刷し180°C30分ベータして形成した。Next, an interlayer insulating film 00) for the multilayer wiring portion was formed on the necessary portions by screen printing. The material used was epoxy resin, which was printed to a thickness of 40 to 50 .mu.m in the shape shown in FIG. 3(C), and then incubated at 180 DEG C. for 30 minutes.
本実施例のような多層配線部の層間絶縁膜の形状とする
ことによりコンタクトホールが存在しないので印刷の際
のマージンを大きくとることが可能となった。By using the shape of the interlayer insulating film of the multilayer interconnection part as in this embodiment, there is no contact hole, so it is possible to have a large margin during printing.
また、この眉間絶縁膜のパターンとして第4図(A)〜
(C)に示すような形状でも可である。In addition, the pattern of this glabellar insulating film is shown in Fig. 4 (A) ~
A shape as shown in (C) is also possible.
つまり最低限必要部分には層間絶縁膜が設けられていれ
ばよい。In other words, it is sufficient that the interlayer insulating film is provided in the minimum required portion.
また、この眉間絶縁膜の形成工程を、終えた後に集積回
路チップ(9)を実装する工程、検査をする工程を行っ
てもよい。Further, after the formation process of the glabella insulating film is completed, the process of mounting the integrated circuit chip (9) and the process of inspecting it may be performed.
次にこの眉間絶縁膜上を渡って、独立した第1の配線群
(7)に接続する第2の配線群O1)を形成し、第1の
配線群(7)を相互に接続し、共通配線を構成させる。Next, a second wiring group O1) that connects to the independent first wiring group (7) is formed across this glabella insulating film, and the first wiring group (7) is connected to each other, and a common Configure the wiring.
この様子を第3図(D)に示す。This situation is shown in FIG. 3(D).
この第2の配線群(11)は、銅ペーストをスクリーン
印刷法によりパターンどおりに印刷した後、180°C
20分のベークを行って形成した。This second wiring group (11) is printed at 180°C after printing copper paste according to the pattern by screen printing method.
Bake for 20 minutes to form.
さらに、これら基板の端部付近全面に保護膜を形成した
。Furthermore, a protective film was formed on the entire surface near the edges of these substrates.
このようにして、硝子基板上に電気回路を有し電気部品
が装着された配線基板を完成することができた。In this way, it was possible to complete a wiring board having an electrical circuit on a glass substrate and having electrical components mounted thereon.
この基板とほぼ同様の工程でもう一方の基板を作成し、
両基板に液晶表示装置として必要な処理を施した後に2
つの基板(1)を重ね合わせ、間にギャップ間隔を一定
に保つスペーサをはさんでその外周をシールし液晶セル
を完成し、その空間に液晶材料を注入し液晶表示装置を
完成させた。Create another board using almost the same process as this board,
After applying the necessary processing for a liquid crystal display device to both substrates,
A liquid crystal cell was completed by stacking two substrates (1) and sealing the outer periphery with a spacer to maintain a constant gap between them, and a liquid crystal display device was completed by injecting a liquid crystal material into the space.
本実施例において液晶表示装置の基板(1)上の電極(
6)のパターニングは従来より公知のエツチング法−で
もよいが本出願人が出願している特願昭61−1862
02号に記載のようにエキシマレーザ−を用いたパター
ニングを行ってもよい。In this example, the electrode (
The patterning in 6) may be performed by a conventionally known etching method, but the method described in Japanese Patent Application No. 61-1862 filed by the present applicant
Patterning may be performed using an excimer laser as described in No. 02.
この場合はウェット工程を用いないためその工程コスト
材料コストを削減できる。In this case, since no wet process is used, the process cost and material cost can be reduced.
またこの場合には第1の配線群(7)も第2の配線群(
l 1)同様に印刷法にて形成してもよい。In addition, in this case, the first wiring group (7) is also connected to the second wiring group (7).
l1) It may also be formed by a printing method in the same way.
〔実施例2〕
本実施例では、本発明の構成をイメージセンサ−に応用
した場合を記載する。[Embodiment 2] In this embodiment, a case will be described in which the configuration of the present invention is applied to an image sensor.
基板(1)上に所定のパターニングを施した第1の導電
膜02)と、光電変換を行う半導体層03)と第2の導
電膜04)とを従来公知の技術を用いて形成されたセン
サーアレイの基板(1)の端部付近にセンサーアレイ駆
動用の電気回路を設ける。そのためにスクリーン印刷法
により銅ペーストを用いて第1の配線群のパターンを形
成する。A sensor in which a first conductive film 02) which is patterned in a predetermined manner on a substrate (1), a semiconductor layer 03) that performs photoelectric conversion, and a second conductive film 04) are formed using a conventionally known technique. An electric circuit for driving the sensor array is provided near the end of the array substrate (1). For this purpose, a pattern of the first wiring group is formed using copper paste by a screen printing method.
この時第1の配線群(7)とセンサーアレイの第1の導
電膜又は第2の導電膜とは位置合わせを行って一部接続
させる。At this time, the first wiring group (7) and the first conductive film or the second conductive film of the sensor array are aligned and partially connected.
次にこの印刷された基板をベータして銅ペーストを焼き
固め配線を形成する。この時の温度はセンサーに使用さ
れている材料が影響を受けない程度好ましくは200°
C以下で焼成することが好ましい。Next, this printed board is beta-baked and the copper paste is baked to form wiring. The temperature at this time is preferably 200° so that the material used in the sensor is not affected.
It is preferable to fire at C or lower.
次にこの第1の配線群(7)の少なくとも一部をおおっ
て眉間絶縁膜00)を実施例1と同様の方法で形成した
後に第1の配線群(7)にイメージセンサ−駆動用のI
C(9)をフェースダウンボンディングして接続し、I
C(9)及びIC(9)と第1の配線群(7)との接続
部分の検査を行った。Next, after forming a glabellar insulating film 00) covering at least a part of this first wiring group (7) in the same manner as in Example 1, I
Connect C(9) by face down bonding and connect I
The connection portion between C (9) and IC (9) and the first wiring group (7) was inspected.
この際ICチップ(9)と基板(1)との接続は仮接着
の状態とし、ICの検査を行い不良がなければ完 。At this time, the connection between the IC chip (9) and the board (1) is temporarily bonded, and the IC is inspected and if there are no defects, the connection is complete.
全接着を行い不良があれば一部ICチップ(9)をはず
し再度接続を行い完全接着を行った。After complete adhesion, if any defects were found, some IC chips (9) were removed and reconnected to achieve complete adhesion.
このようにすることにより不良の場合ICチップを取り
はずす際に同時に第1の配線群をも誤って除去する事故
の発生をなくすることができ、より製造の歩留を向上さ
せることが可能となった。By doing this, it is possible to eliminate the accident of accidentally removing the first wiring group at the same time when removing the IC chip in the case of a defect, and it is possible to further improve the manufacturing yield. Ta.
その後、第2の配線群の印刷、保護膜の印刷等を実施例
1と同じ条件にて行いイメージセンサ−を完成させた。Thereafter, printing of a second wiring group, printing of a protective film, etc. were performed under the same conditions as in Example 1 to complete an image sensor.
本発明はその他の電気、電子部品に巾広く応用できるこ
とは言うまでもないが、前述の実施例1.2に示すよう
にCOC(チップオングラス)、CO3(チップオンボ
ード)等の技術を用いてICチップを直接に基板上に設
ける際に応用すると製造コスト、製造工程の削減に顕著
な効果を得ることが可能となった。It goes without saying that the present invention can be widely applied to other electrical and electronic components, but as shown in Example 1.2 above, IC When applied when a chip is directly mounted on a substrate, it has become possible to obtain a remarkable effect in reducing manufacturing costs and manufacturing steps.
本発明の構成を有することにより従来では不可能であっ
た電気回路に装着された電気部品の検査を製造が完成す
る以前に行い、その良、不良の判定を行うことができ、
製品の歩留りを格段に向上させることができた。By having the configuration of the present invention, it is possible to inspect electrical components installed in an electrical circuit before the manufacturing is completed, which was impossible in the past, and determine whether the electrical components are good or defective.
We were able to significantly improve product yield.
また、共通配線と技分かれ配線とを接続するコンタクト
ホールを全くな(することができるか、その大きさを大
きくすることができるのでその製造工程での位置合わせ
の精度に余裕が生じる。Further, since the contact hole connecting the common wiring and the divided wiring can be completely omitted or its size can be increased, there is a margin in the precision of positioning in the manufacturing process.
また、配線の位置合わせ精度に余裕が生じるため各配線
をすべてスクリーン印刷にて行うことができ、その製造
コストを格段に下げることができIn addition, since there is margin for wiring alignment accuracy, all wiring can be done by screen printing, significantly reducing manufacturing costs.
第1図、第3図は本発明の概略製造工程の様子を示す。 第2図は従来の配線基板の多層配線部の様子。 第4図は本発明の眉間絶縁膜のパターンの例を示す。 1・・・・・基板 2.7・・・第1の配線群 5.11・・第2の配線群 10・・・・層間絶縁膜 9・・・・・ICチップ FIGS. 1 and 3 schematically show the manufacturing process of the present invention. Figure 2 shows the multilayer wiring section of a conventional wiring board. FIG. 4 shows an example of the pattern of the glabellar insulating film of the present invention. 1... Board 2.7...First wiring group 5.11...Second wiring group 10... Interlayer insulation film 9...IC chip
Claims (1)
配線より技分かれした電気部品接続用の複数の配線とを
有する配線基板において前記複数の共通配線および枝分
かれした配線は、共通配線の一部と枝分かれした配線と
を兼ねる第1の配線と共通配線の一部のみを構成する第
2の配線とを必要部分に絶縁処理を施して電気的に接続
して構成されることを特徴とする配線基板。1. In a wiring board having a plurality of common wirings provided on an insulating substrate and a plurality of wirings for connecting electrical components separated from the common wirings, the plurality of common wirings and branched wirings are part of the common wiring. A wiring board characterized in that a first wiring that also serves as a branched wiring and a second wiring that constitutes only a part of a common wiring are electrically connected by applying insulation treatment to necessary parts. .
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63025912A JPH01201988A (en) | 1988-02-05 | 1988-02-05 | Printed-wiring board |
US07/303,241 US4934045A (en) | 1988-02-05 | 1989-01-30 | Method of producing electric circuit patterns |
US07/495,757 US5025555A (en) | 1988-02-05 | 1990-03-19 | Method of producing electric circuit patterns |
US07/495,758 US5072519A (en) | 1988-02-03 | 1990-03-19 | Method of producing electric circuit patterns |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63025912A JPH01201988A (en) | 1988-02-05 | 1988-02-05 | Printed-wiring board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01201988A true JPH01201988A (en) | 1989-08-14 |
Family
ID=12178989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63025912A Pending JPH01201988A (en) | 1988-02-03 | 1988-02-05 | Printed-wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01201988A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5427957A (en) * | 1977-08-03 | 1979-03-02 | Canon Kk | Multiilayer wiring |
-
1988
- 1988-02-05 JP JP63025912A patent/JPH01201988A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5427957A (en) * | 1977-08-03 | 1979-03-02 | Canon Kk | Multiilayer wiring |
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