JPH02311826A - Manufacture of liquid crystal electrooptic device - Google Patents

Manufacture of liquid crystal electrooptic device

Info

Publication number
JPH02311826A
JPH02311826A JP1135038A JP13503889A JPH02311826A JP H02311826 A JPH02311826 A JP H02311826A JP 1135038 A JP1135038 A JP 1135038A JP 13503889 A JP13503889 A JP 13503889A JP H02311826 A JPH02311826 A JP H02311826A
Authority
JP
Japan
Prior art keywords
wiring group
wiring
liquid crystal
forming
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1135038A
Other languages
Japanese (ja)
Inventor
Akira Mase
晃 間瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP1135038A priority Critical patent/JPH02311826A/en
Publication of JPH02311826A publication Critical patent/JPH02311826A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To inspect electric components, one by one, after they are mounted on an electric circuit by forming one wiring group for each individual electric component, forming an insulating film at a necessary part, and connecting one wiring group for one electric component mutually and thus forming a common wiring group lastly. CONSTITUTION:A 1st wiring group 2 is formed of a conductive material on a substrate 1 which has an insulating surface. At this time, the 1st wiring group 2 is one wiring group for one electric component 3 and not connected to a wiring group 2' to which an adjacent electric component is connected. Then the inter-layer insulating film 4 is formed covering part of the 1st wiring group, a 2nd wiring group 5 is formed beyond on the insulating film 4, and the 1st wiring groups 2 and 2' are connected mutually to complete the common wiring group. Consequently, the electric components mounted on the circuit can be inspected before the device is completed, so the yield of the product is improved.

Description

【発明の詳細な説明】 「技術分野」 本発明は、電気部品等を設ける配線基板に関し特に液晶
電気光学装置において基板上に電気部品等を複数個装着
後に、個々にテストを行うことが可能な新規な配線基板
を製造する方法に関するものである。
Detailed Description of the Invention [Technical Field] The present invention relates to a wiring board on which electrical parts, etc. are mounted, and in particular, to a liquid crystal electro-optical device, in which it is possible to individually test a plurality of electrical parts, etc. after mounting them on the board. The present invention relates to a method of manufacturing a novel wiring board.

「従来の技術」 従来、電気部品等を電気回路が描かれた基板上に装着し
、液晶表示装置、イメージセンサ−、サーマルプリント
ヘッド、その他の電子部品を駆動するための回路を持つ
配線基板としてはPボードが一般に使用されていた。
"Conventional Technology" Conventionally, electrical components and the like are mounted on a board on which electrical circuits are drawn, and it is used as a wiring board with circuits for driving liquid crystal display devices, image sensors, thermal print heads, and other electronic components. P-boards were generally used.

このPボードはエポキシ又はガラスエポキシ樹脂基板上
にエツチング処理等によって形成された銅配線とその銅
配線上にあけられた電気部品の足挿入用の穴よりなるも
ので、この穴に電気部品の足を挿入しはんだ付は等を施
して電気回路に接続してゆ(ものであった。
This P-board consists of copper wiring formed on an epoxy or glass epoxy resin substrate by etching, etc., and holes drilled on the copper wiring for inserting the feet of electrical components. Insert it, solder it, etc., and connect it to the electrical circuit.

このPボードに設けられた電気回路は電気部品を装着す
る以前に、はぼ共通の配線部分が完成しており、電気部
品を装着した後に個々の電気部品のテスト及び個々の電
気部品との接続部のテストを行うことができなかった。
In the electric circuit installed on this P board, the common wiring part has been completed before the electric parts are installed, and after the electric parts are installed, the individual electric parts are tested and the connections with the individual electric parts are completed. It was not possible to test the section.

又、Pボードの電気回路を設は特定の電子部品を駆動さ
せる時などはPボードと電子部品の間を接続することが
必要となるため、接続部が増し、不良接続等の新たな問
題が生じてきた。
In addition, when setting up an electrical circuit on the P-board, it is necessary to connect the P-board and electronic components when driving a specific electronic component, which increases the number of connections and creates new problems such as poor connections. It has arisen.

これに対して、電気部品等を装着する電気回路をイメー
ジセンサ−1液晶表示装置、サーマルヘッド等の電子部
品を構成している基板上の一部に直接電気回路を描き、
そして電気部品を装着する技術も知られている。この方
式はPボードを使う場合に比べて部品点数を減らすこと
ができ、駆動する電子部品との接続部が不要等の点にお
いてすぐれている。
On the other hand, an electric circuit for mounting electric parts, etc. is drawn directly on a part of the board that constitutes the electronic parts such as the image sensor-1 liquid crystal display device and the thermal head.
Techniques for attaching electrical components are also known. This method is superior in that the number of parts can be reduced compared to the case where a P board is used, and there is no need for a connection part with the electronic parts to be driven.

しかしながらこの方法においても、複数の電気部品に対
して共通の配線を用いているため、Pボードの場合と同
様に基板上の電気回路に対して電気部品を装着した後に
個々の電気部品について良、不良のテスト及び電気部品
の装着時の接続部の良、不良のテストを行うことができ
ながった。さらにまた共通の配線に対して複数個の電気
部品を接続するためには多層配線が必要となり製造工程
を複雑にしていた。
However, even in this method, common wiring is used for multiple electrical components, so after the electrical components are attached to the electrical circuit on the board, as in the case of the P board, each electrical component is It was not possible to test for defects and to check whether the connections were good or bad when installing electrical parts. Furthermore, in order to connect a plurality of electrical components to a common wiring, multilayer wiring is required, complicating the manufacturing process.

第2図にこの従来装置の多層配線部分の製造方法の概略
を示す。
FIG. 2 schematically shows a method for manufacturing the multilayer wiring portion of this conventional device.

第2図(A)に示されたように基板(1)上に共通配線
θつをウェットエツチング法等により導電性物質(例え
ば銅、ITO等)により形成する。
As shown in FIG. 2A, common wiring lines θ are formed on the substrate (1) using a conductive material (for example, copper, ITO, etc.) by wet etching or the like.

次に絶縁膜を同図(B)に示すパターンに形成する。こ
こで06)は共通配jlfA05)と技分かれ配線07
)との接続を行うコンタクトホールであります。 次に
同図(C)に示すように枝分かれ配線θ′7)を形成し
、この枝分かれ配線面に、電気部品を装着するものであ
ります。
Next, an insulating film is formed in the pattern shown in FIG. Here, 06) is the common wiring jlfA05) and the technique-divided wiring 07
) is a contact hole for connection. Next, as shown in the same figure (C), branch wiring θ'7) is formed, and electrical components are attached to this branch wiring surface.

このような多層配線部分において枝分かれ配線(+7)
がコンタクトホール0ωで共通配線a5)と接続するた
めにはコンタクトホール00の寸法に限定が必要となる
。しかしながら、装着する電気部品の端子の数が多くな
った場合又は、電気部品の数が増した場合、コンタクト
ホール0ωの寸法を小さくしなければならず、コンタク
ト不良が発生した、特に印刷法にて絶縁層を形成する場
合はコストを安くできるという利点はあるがコンタクト
ホールが形成できないという技術的な問題があった。
Branch wiring (+7) in such a multilayer wiring part
In order to connect to the common wiring a5) through the contact hole 0ω, it is necessary to limit the dimensions of the contact hole 00. However, when the number of terminals of the electrical components to be installed increases, or when the number of electrical components increases, the size of the contact hole 0ω must be made smaller, and contact failure occurs, especially when using the printing method. When forming an insulating layer, there is an advantage that the cost can be reduced, but there is a technical problem that a contact hole cannot be formed.

「発明の構成」 本発明は、前述の如き配線基板を有する液晶電気光学装
置の作製方法についての新規な構造に関するものであり
、特に一部の多層配線部品を有する配線基板で前述のよ
うな問題点が改善された物であります。
``Structure of the Invention'' The present invention relates to a novel structure for a method of manufacturing a liquid crystal electro-optical device having a wiring board as described above, and particularly relates to a method for manufacturing a liquid crystal electro-optical device having a wiring board as described above. This is an improved item.

すなわち絶縁基板上に複数の共通配線が設けられており
、その共通配線より技分かれした配線とこの技分かれし
た配線に電気部品が装着可能な構成を有するものであり
、電気部品装着後に個々の部品の検査を行うことができ
るものであります。
In other words, a plurality of common wirings are provided on an insulating substrate, and the configuration is such that electrical parts can be mounted on the wiring divided from the common wiring and the wiring divided into technical parts. It is possible to carry out inspections.

さらに、基板を貼り合わせた後にjIA縁層形層形成品
の検査も行うことができるため、絶縁層形成時、或いは
部品の検査時において基板間に数μmの大きさの粒子等
の異物が入り込むことがなく、従って液晶電気光学装置
の作製工程において歩留りを大きく上昇させるものであ
ります。
Furthermore, since JIA edge layered products can be inspected after the substrates are bonded together, it is possible to prevent foreign matter such as particles several micrometers in size from entering between the substrates when forming the insulation layer or inspecting the parts. Therefore, it greatly increases the yield in the manufacturing process of liquid crystal electro-optical devices.

以下に一例を示す図面を用いて本発明を説明する。The present invention will be explained below using drawings showing an example.

第1図に本発明の液晶電気光学装置に関しての新規な配
線基板の作製方法の一例を示す。
FIG. 1 shows an example of a method for manufacturing a novel wiring board for the liquid crystal electro-optical device of the present invention.

絶縁性表面を有する基板上(1)上に第1の配線群(2
)を導電性材料で形成する。(同図(A))この時第1
の配線群(2)は1つの電気部品(3)(例えばICチ
ップ)に対しては1かたまりの配線群となっており、隣
の電気部品が接続される第1の配線群(2″)とは接続
されていない。
A first wiring group (2) is placed on a substrate (1) having an insulating surface.
) is made of conductive material. (Same figure (A)) At this time, the first
The wiring group (2) is a single wiring group for one electrical component (3) (for example, an IC chip), and is the first wiring group (2'') to which the adjacent electrical component is connected. is not connected.

この段階で、2枚の基板の貼り合わせ工程を行う。この
工程は一方の基板にスクリーン印刷等の方法を用いて接
着剤を塗布し、基板の電極面を内側にして貼り合わせる
工程をいう。ただし、貼り合わせの前にスペーサーを散
布する工程を行うことはいうまでもない。
At this stage, a process of bonding the two substrates is performed. This process is a process in which an adhesive is applied to one substrate using a method such as screen printing, and the substrates are bonded together with the electrode surface facing inside. However, it goes without saying that a step of dispersing spacers is performed before bonding.

こうして基板上に微粒子等の異物が入り込まないように
した状態で電気部品を第1の配線群(2)に装着し、個
々の電気部品について検査を行うことができる。もし不
良であればこの段階で不良の電気部品を取りはずし新た
に電気部品を付は再度検査することが可能となる。
In this way, electrical components can be mounted on the first wiring group (2) while preventing foreign matter such as particles from entering the board, and each electrical component can be inspected. If it is defective, it is possible to remove the defective electrical component at this stage, attach a new electrical component, and inspect it again.

そのうえ、検査は基板を貼り合わせた後に行うので、検
査中における基板上へのゴミの混入を防ぐことができる
Moreover, since the inspection is performed after the substrates are bonded together, it is possible to prevent dust from getting onto the substrates during the inspection.

次にこの第1の配線群の少なくとも一部をおおって眉間
絶縁膜(4)を形成する(同図(B))。その次にこの
絶縁膜(4)上を越えて第1の配線群と同じピッチと巾
で第2配線群(5)を形成し、第1の配線群(2)と(
2″)とを相互接続し共通配線群を完成させる。このよ
うにして共通配線群と共通配線群より枝分かれした配線
群とを有する配線基板を構成することができる。なお、
眉間絶縁膜(4)、第2配線群(5)の形成は、既に基
板を貼り合わせてしまっているため、上下の基板の境目
に段差が生じており一般に印刷法を用いることはできな
いが、ディスペンス法を用いる或いは特に眉間絶縁膜を
形成する場合には一般に市販されている絶縁物質、例え
ばシールなどを貼付するだけでも良い。
Next, a glabellar insulating film (4) is formed to cover at least a portion of this first wiring group (FIG. 3(B)). Next, a second wiring group (5) is formed over this insulating film (4) with the same pitch and width as the first wiring group, and the first wiring group (2) and (
2") to complete a common wiring group. In this way, a wiring board having a common wiring group and wiring groups branched from the common wiring group can be configured.
Generally speaking, printing cannot be used to form the eyebrow insulating film (4) and the second wiring group (5) because the substrates have already been bonded together, so there is a level difference at the boundary between the upper and lower substrates. When a dispensing method is used or when forming an insulating film between the eyebrows, it is sufficient to simply apply a commercially available insulating material such as a sticker.

ここでディスペンス法とは液状物質を上方より滴下する
、或いは塗布することを意味する。
Here, the dispensing method means dropping or applying a liquid substance from above.

本発明は共通配線群、すなわち電気部品が接続されてい
る配線群が複数個相互に接続されて形成している物を最
初から共用させて形成するのではなく、最初は個々の電
気部品に対して1つの配線群を形成し、次に必要部分に
絶縁膜を形成し、最後に1つの電気部品に対する1つの
配線群を相互接続することにより共通配線群を設けるも
のであり、このような構成をとることにより特に電気回
路に装着される電気部品の検査を1つづつ行うことがで
きるという特徴を持ち、さらには、基板を貼り合わせた
後に部品の検査工程を行うため、基板と基板の間に異物
が侵入するのを防ぐものである。
The present invention does not form a common wiring group, that is, a wiring group to which electrical components are connected, which is formed by interconnecting a plurality of wiring groups, from the beginning. A common wiring group is provided by forming one wiring group, then forming an insulating film on the necessary parts, and finally interconnecting one wiring group for one electric component. By using this method, it is possible to inspect each electrical component installed in an electrical circuit one by one.Furthermore, since the component inspection process is performed after the boards are bonded together, there is a This prevents foreign matter from entering.

以下に実施例を示し本発明を詳述する。EXAMPLES The present invention will be explained in detail with reference to Examples below.

(実施例1〕 第3図に本実施例の液晶電気光学装置の作製方法の概略
を示す。
(Example 1) FIG. 3 schematically shows a method for manufacturing a liquid crystal electro-optical device of this example.

本実施例では使用する基板(1)として青板硝子を使用
した。この硝子基板は後述のように液晶表示装置のセル
をも兼ねるので高平坦性の硝子を使用した。
In this example, soda lime glass was used as the substrate (1). Since this glass substrate also serves as a cell of a liquid crystal display device as will be described later, highly flat glass was used.

この硝子基板上に公知のスパッタ法、蒸着法等によりI
TO(酸化インジューム、スズ)導電膜を形成し、その
ITO膜を基板(1)の大部分を占める液晶表示領域は
、マトリクス構成となるように電極(6)をパターニン
グ、残りの基板の端部に液晶表示駆動回路を構成する第
1の配線群(7)を同時に形成した。
I was deposited on this glass substrate by a known sputtering method, vapor deposition method, etc.
A TO (indium oxide, tin) conductive film is formed, and the ITO film is used to form a liquid crystal display area that occupies most of the substrate (1). Electrodes (6) are patterned to form a matrix configuration, and the edges of the remaining substrate are patterned. At the same time, a first wiring group (7) constituting a liquid crystal display drive circuit was formed at the same time.

本実施例ではウェットエツチング法にて、電極(6)及
び第1の配線群(7)を形成した。
In this example, the electrode (6) and the first wiring group (7) were formed by wet etching.

第3図(A)にはこの状態の基板(1)の端部付近の概
略図を示すものであり、第1の配線群(7)は2つ分し
か描かれてないが、さらに多数分が設けられている。
Figure 3 (A) shows a schematic diagram of the vicinity of the end of the board (1) in this state, and although only two first wiring groups (7) are drawn, many more wiring groups are shown. is provided.

この時第1の配線群(7)はまだいずれの他の配線部分
とも接続されておらず独立した状態となっている。
At this time, the first wiring group (7) is not yet connected to any other wiring portion and is in an independent state.

ここで、この基板上に液晶を配向させるための薄膜を形
成する。この工程は、ポリアミック酸のN−メチル−2
−ピロリドン溶液をオフセット印刷法を用いて基板上に
塗布し、280°Cで150分加熱することによりポリ
イミド薄膜を得た。
Here, a thin film for orienting the liquid crystal is formed on this substrate. This process involves N-methyl-2 of polyamic acid.
- A polyimide thin film was obtained by applying a pyrrolidone solution onto a substrate using an offset printing method and heating it at 280°C for 150 minutes.

そして、綿布によるラビング工程を行い、スペーサー散
布を行った他の基板と貼り合わせる。
Then, a rubbing process is performed using cotton cloth, and the substrate is bonded to another substrate on which spacers have been sprayed.

次に第1の配線群(7)の電気部品接続部分(8)に液
晶表示装置駆動用の集積回路のチップ(9)を直接フェ
イスダウンボンディングを行う。この時チップ(9)と
基板(1)との接着は紫外線硬化タイプの接着剤を使用
し温度150 ’Cで、約3Kgのプレス圧を加え3分
間、波長365n*の紫外線を照射し硬化した。 この
状態を第3図(B)に示す、この状態では1つのチップ
(9)に対して第1の配線群(7)が独立して設けられ
ている。
Next, a chip (9) of an integrated circuit for driving a liquid crystal display device is directly face-down bonded to the electrical component connecting portion (8) of the first wiring group (7). At this time, the chip (9) and the substrate (1) were bonded together using an ultraviolet curing type adhesive at a temperature of 150'C with a press pressure of approximately 3 kg and irradiated with ultraviolet rays with a wavelength of 365n* for 3 minutes to cure. . This state is shown in FIG. 3(B). In this state, the first wiring group (7) is independently provided for one chip (9).

この際に、この独立した第1の配線群(7)を検査用の
取り出し端子として、液晶表示装置駆動用の集積回路チ
ップ(9)の検査とフェイスダウンボンディングの接続
部の検査を行う。良品又は接続部が良の場合はよいが不
良品又は接続部が不良の場合は一度接着したチップ(9
)を除去し再度側のチップを取りつけ再び検査を行う。
At this time, the independent first wiring group (7) is used as an extraction terminal for testing, and the integrated circuit chip (9) for driving the liquid crystal display device and the face-down bonding connection portion are tested. If it is a good product or the connection part is good, it is fine, but if it is a defective product or the connection part is defective, the chip that has been bonded once (9
), reinstall the chip on the side, and perform the inspection again.

このようにすることにより、絶縁層の作製工程や、電気
部品の検査工程よりも前に基板の貼り合わせ工程を行っ
たため、基板間に入り込むゴミの数が減少し、液晶表示
装置の製造歩留を向上させることができた。
By doing this, the board bonding process is performed before the insulating layer fabrication process and the electrical component inspection process, which reduces the number of dust that gets between the substrates and improves the manufacturing yield of liquid crystal display devices. was able to improve.

次に多層配線部分の眉間絶縁膜0IIDを必要部分にデ
ィスペンス法で形成した。材料はエポキシ樹脂を用い厚
さ50−100μmで第3図(C)に示すような形状に
作製して、180℃で30分ベータして形成した。
Next, an inter-glabellar insulating film 0IID for the multilayer wiring portion was formed in the necessary portions by a dispensing method. The material was made of epoxy resin to a thickness of 50-100 .mu.m in the shape shown in FIG. 3(C), and was formed by heating at 180.degree. C. for 30 minutes.

本実施例のような多層配線部の眉間絶縁膜の形状とする
ことによりコンタクトホールが存在しないので印刷の際
のマージンを大きくとることが可能となった。
By adopting the shape of the glabellar insulating film of the multilayer wiring part as in this embodiment, there is no contact hole, so it is possible to have a large margin during printing.

また、この眉間絶縁膜のパターンとして第4図(A)〜
(C)に示すような形状でも可である。
In addition, the pattern of this glabellar insulating film is shown in Fig. 4 (A) ~
A shape as shown in (C) is also possible.

つまり最低限必要部分には層間絶縁膜が設けられていれ
ばよい。
In other words, it is sufficient that the interlayer insulating film is provided in the minimum required portion.

また、この層間絶縁膜の形成工程を、終えた後に基板の
貼り合わせ工程を行い、その後に集積回路チップ(9)
を実装する工程、検査をする工程を行ってもよい。
Further, after completing this interlayer insulating film formation process, a substrate bonding process is performed, and then an integrated circuit chip (9) is formed.
You may also perform a process of mounting and a process of inspecting.

次にこの層間絶縁膜上を渡って、独立した第1の配線群
(7)に接続する第2の配線群(11)を形成し、第1
の配線群(7)を相互に接続し、共通配線を構成させる
。この様子を第3図(D)に示す。
Next, a second wiring group (11) connected to the independent first wiring group (7) is formed across this interlayer insulating film, and the second wiring group (11) is connected to the first independent wiring group (7).
The wiring group (7) is connected to each other to form a common wiring. This situation is shown in FIG. 3(D).

この第2の配線群00も、銅ペーストをディスペンス法
によりパターンどおりに塗布した後、180°C20分
のベークを行って形成した。
This second wiring group 00 was also formed by applying copper paste according to the pattern by a dispensing method, and then baking at 180° C. for 20 minutes.

さらに、これら基板の端部付近全面に保護膜を形成した
Furthermore, a protective film was formed on the entire surface near the edges of these substrates.

そして、貼り合わせた基板゛の間に公知の技術である真
空注入法を用いて液晶を注入して、硝子基板上に電気回
路を有し電気部品が装着された液晶セルを完成すること
ができた。(一対の基板を貼り合わせ、その間に液晶を
存在せしめたものを「セル」と称する) 本実施例において液晶表示装置の基板(す上の電極(6
)のバターニングは従来より公知のエツチング法でもよ
いが本出願人が出願している特願昭61−186202
号に記載のようにエキシマレーザ−を用いたバターニン
グを行ってもよい。
Then, by injecting liquid crystal between the bonded substrates using a well-known vacuum injection method, a liquid crystal cell with an electric circuit and electrical components mounted on the glass substrate can be completed. Ta. (A pair of substrates bonded together and with liquid crystal present between them is called a "cell.") In this example, the electrodes (6
) may be done by a conventionally known etching method, but the method described in Japanese Patent Application No. 186202/1986 filed by the present applicant
Buttering may be performed using an excimer laser as described in the above.

この場合はウェット工程を用いないためその工程コスト
材料コストを削減できる。
In this case, since no wet process is used, the process cost and material cost can be reduced.

(効果) 本発明の構成を有することにより従来では不可能であっ
た電気回路に装着された電気部品の検査を液晶電気光学
装置の製造が完成する以前に行い、その良、不良の判定
を行うことができ、製品の歩留りを格段に向上させるこ
とができた。
(Effects) By having the configuration of the present invention, it is possible to inspect the electrical components installed in the electrical circuit, which was impossible in the past, before the manufacturing of the liquid crystal electro-optical device is completed, and determine whether the device is good or bad. We were able to significantly improve product yield.

また、共通配線と枝分かれ配線とを接続するコンタクト
ホールを全くなくすることができるか、その大きさを大
きくすることができるのでその製造工程での位置合わせ
の精度に余裕が生じる。
Further, since the contact hole connecting the common wiring and the branch wiring can be completely eliminated or its size can be increased, there is a margin in the accuracy of positioning in the manufacturing process.

さらに、電気部品の検査を基板を貼り合わせた後に行う
ことができるので、検査中に基板間にゴミの入り込むこ
とがなくなり、製品の歩留りを大幅に向上させることが
できた。
Furthermore, since the electrical components can be inspected after the boards are bonded together, there is no possibility of dust getting between the boards during the inspection, and product yields can be significantly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第3図は本発明の概略製造工程の様子を示す。 第2図は従来の配線基板の多層配線部の様子。 第4図は本発明の眉間絶縁膜のパターンの例を示す。 1・・・・・基板 2.7・・・第1の配線群 5.11・・第2の配線群 10・・・・層間絶縁膜 9・・・・・ICチップ FIGS. 1 and 3 schematically show the manufacturing process of the present invention. Figure 2 shows the multilayer wiring section of a conventional wiring board. FIG. 4 shows an example of the pattern of the glabellar insulating film of the present invention. 1... Board 2.7...First wiring group 5.11...Second wiring group 10... Interlayer insulation film 9...IC chip

Claims (2)

【特許請求の範囲】[Claims] 1.絶縁表面を有する基板上に複数の電気部品に入力信
号を与えるための複数の第1の配線を形成する工程と前
記第1の配線の少なくとも1部分をおおって絶縁層を形
成する工程と前記絶縁層上及び該層より延在して複数の
第2の配線を形成し前記第1の配線と電気的に接続する
ことにより共通配線を形成する工程を有し、前記絶縁層
の形成工程は一対の基板を貼り合わせる工程より後に行
うことを特徴とする液晶電気光学装置の作製方法。
1. a step of forming a plurality of first wirings for providing input signals to a plurality of electrical components on a substrate having an insulating surface; a step of forming an insulating layer covering at least a portion of the first wirings; and a step of forming an insulating layer over at least a portion of the first wirings; forming a common wiring by forming a plurality of second wirings on and extending from the layer and electrically connecting them to the first wiring; A method for manufacturing a liquid crystal electro-optical device, the method being carried out after the step of bonding substrates together.
2.前記特許請求の範囲第1項において第1の配線はフ
ォトリソグラフィを用いた方法により形成され、絶縁層
はディスペンス或いは絶縁物質を貼付することによって
形成されることを特徴とする液晶電気光学装置の作製方
法。
2. Manufacturing a liquid crystal electro-optical device according to claim 1, wherein the first wiring is formed by a method using photolithography, and the insulating layer is formed by dispensing or pasting an insulating material. Method.
JP1135038A 1989-05-29 1989-05-29 Manufacture of liquid crystal electrooptic device Pending JPH02311826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1135038A JPH02311826A (en) 1989-05-29 1989-05-29 Manufacture of liquid crystal electrooptic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1135038A JPH02311826A (en) 1989-05-29 1989-05-29 Manufacture of liquid crystal electrooptic device

Publications (1)

Publication Number Publication Date
JPH02311826A true JPH02311826A (en) 1990-12-27

Family

ID=15142493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1135038A Pending JPH02311826A (en) 1989-05-29 1989-05-29 Manufacture of liquid crystal electrooptic device

Country Status (1)

Country Link
JP (1) JPH02311826A (en)

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