JPH0589030A - Input/output controller - Google Patents

Abstract

PURPOSE:To detect a defect, which can not be detected by an abnormality detection part, during DMA transfer and to improve the reliability of the device by comparing data in a main storage device and a data buffer after the DMA transfer is completed. CONSTITUTION:An input/output device 3 decodes a DMA transfer command from a CPU 1 and based on parameter information to be continuously received, data are read from the input/output device 3 only for a data length designated from a designated address, written in a data buffer 32 and transferred to a main storage address by the DMA transfer. After the data transfer is completed, the final data in the data buffer 32 and the final data in a main storage device 2 are read out and compared. When those data are coincident, the command is normally finished and when they are not coincident, abnormal end is judged. Thus, the defect not detected at the abnormality detection part can be detected during the DMA transfer and the reliability is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is an input / output control device suitable for use in a data processing device for transferring data between a main memory device and an input / output device by DMA (direct memory access) by a command issued from a CPU. Regarding

[0002]

2. Description of the Related Art There are two types of transfer of input / output data in a data processing device: program transfer and DMA transfer. In the former case, the CPU controls data transfer, and in the latter case, the DMA transfer control device provided independently of the CPU controls. The latter is commands and parameters issued from the CPU (address and data transfer length)
DM data transfer between I / O device and main memory according to
This is a method in which the A transfer control device directly performs the operation without passing through the CPU, and is frequently used because it reduces the load on the CPU and enables high-speed transfer as compared with the program transfer.

After the completion of the DMA transfer, an error is detected by an abnormality detecting section provided in the DMA control section or the data bus control section. If no error is detected here, it is regarded as normal termination and the command processing is terminated. .. In other words, the transferred data itself was not read again to confirm that the data was transferred reliably.

[0004]

According to the above-described conventional example, the main storage device and the data between the main storage device and the input / output device are intervened due to a defect or the like which cannot be detected by the abnormality detection unit during the DMA transfer. If the contents of the data buffer to be
Accurate error detection is not possible.

The present invention has been made in view of the above circumstances, and at least a part of the transferred data is read again to confirm that the data has been transferred reliably. Improves the error detection rate during illegal data transfer in DMA transfer processing between
It is an object of the present invention to provide an input / output control device with further improved reliability.

[0006]

An input / output control device of the present invention is a data processing device for performing data transfer between a main memory device and an input / output device by DMA (direct memory access) by a command issued from a CPU, A data buffer in which data of a designated transfer length is temporarily stored, a first data reading circuit for directly reading the data stored in this data buffer, and data stored in the main memory device is stored in the data buffer. A second data read circuit that directly reads the data without passing through, and at least a part of the transferred data remaining in the data buffer via the first and second data read circuits after the completion of the DMA transfer and the main storage device. Read the data in the corresponding range,
It is characterized by comprising a comparison circuit for comparing these, and performing normal or abnormal processing according to the result of comparison by the comparison circuit.

[0007]

INDUSTRIAL APPLICABILITY The present invention is applied to DMA transfer in which data transfer between a main memory device and an input / output device is carried out via a data buffer incorporated in the input / output control device. , A data read circuit for directly reading the data buffer and a data read circuit for directly reading the data transferred to the main storage device without passing through the data buffer are added, and through this data read circuit,
A part or all of the transferred data remaining in the data buffer after the end of the DMA transfer and the data in the corresponding range of the main storage device are directly read and the data compare check is performed to improve the abnormality detection rate of the DMA transfer. .. As a result, the reliability is further improved.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 is a CPU which serves as a control center of the data processing device, and issues commands to the input / output control device 3 in relation to the present invention. Reference numeral 2 is a main storage device, which stores programs and data, and is read / written by the CPU 1 and the input / output control device 3. Reference numeral 3 is an input / output control device, which controls data transfer between an input / output device such as a large-capacity disk connected to the main storage device. Input / output control device 3
Is composed of an input / output control unit 31 including a command processing circuit, a data read circuit, and a comparison circuit, and a data buffer 32. The input / output control unit 31 controls the data transfer via the data buffer 32 during the DMA transfer.
Direct reading of data stored in the data buffer 32,
The data stored in the main memory 2 can be directly read, and after the DMA transfer is completed, at least a part of the transferred data remaining in the data buffer and the data in the corresponding range of the main memory are read out. To compare. The data buffer 32 holds transfer data between the input / output control device 3 and the main storage device 2 during DMA transfer. Reference numeral 4 denotes an input / output device, which is controlled by the input / output control device 3.

FIG. 2 is a flow chart showing the operation of the embodiment of the present invention.

The operation of the embodiment of the present invention shown in FIG. 1 will be described in detail below with reference to FIG. First, the input / output control device 3 receives a DMA transfer command from the CPU 1. The input / output control device 3 interprets the command, and based on the parameter information received subsequently, reads the data from the input / output device 3 by the specified data length from the specified address, writes the data in the data buffer 32, and writes the data. DMA data transfer is executed to store the data at the designated main memory address. When the DMA transfer is completed, it is checked whether or not an error is detected. If an error is detected here, the above detection processing is performed as in the conventional case. If no error is detected, proceed to the next process.

Here, the transfer data itself is read again, and a routine process for checking whether or not the data has been reliably transferred is entered. In the embodiment of the present invention, for simplification of description,
An example in which only the final data of data transfer is compare-checked will be described. Not limited to this example, even with arbitrary address data,
Alternatively, a method in which all of them are compare-checked may be used. That is, when the data transfer is completed, the final data in the data buffer 32 and the final data in the main memory 2 are read and compared. Here, the address in the data buffer 32 and the address in the main memory 2 of the final data are obtained by the transfer start address + data transfer length.
At this time, if the data match, the command is terminated normally and the command is terminated. If the data do not match, the command is abnormally terminated, assuming that some abnormality has occurred.

[0013]

As described above, according to the present invention, DM
By comparing the data in the main storage device and the data buffer after the A transfer is completed, it is possible to detect a defect that cannot be found by the abnormality detecting unit during the DMA transfer, and it is possible to construct a more reliable data processing device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

 1 ... CPU 2 ... Main storage device 3 ... I / O control device 4 ... I / O device 31 ... I / O control unit 32 ... Data buffer

Claims (1)

[Claims] 1. A data processing device for transferring data between a main memory device and an input / output device by DMA (Direct Memory Access) by a command issued from a CPU, and temporarily stores data for a specified transfer length. A data buffer, a first data reading circuit for directly reading the data stored in the data buffer, and a second data reading circuit for directly reading the data stored in the main storage device without passing through the data buffer. , D
After the MA transfer is completed, at least a part of the transferred data remaining in the data buffer and the data in the corresponding range of the main storage device are read out through the first and second data reading circuits, and are compared. An input / output control device comprising a circuit and performing normal or abnormal processing according to the result of comparison by the comparison circuit.