JPH09231140A - Memory check device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a memory error in short time by executing judgment based on a check code corresponding to written data. SOLUTION: The check code is added to write data by a first memory error check part 11. When writing or reading is executed, a control signal is outputted from a DMA memory check cycle control part 16 to an address preservation part 15. When the control signal is outputted from the DMA memory check cycle control part 16, the address preservation part 15 outputs address data preserved at the time of previous data writing to a two port memory 12. When previous address data is inputted, the two port memory 12 outputs data corresponding to address data to a second memory error check part 13 through the second port. When the second memory check part 13 detects the error, it is judged that the cause of the error exists at the time of writing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory check device, and more particularly to a memory check device in a DMA control circuit.

[0002]

2. Description of the Related Art Conventionally, a memory check method in a DMA control circuit is similar to a memory check method performed by a CPU, and when a memory content is read out, a parity bit or an ECC of data stored in the memory is checked. It was done by doing.

FIG. 4 is a diagram showing the configuration of a memory check device in a conventional DMA control circuit. For example, when write data is output to the DMA control circuit 2 from a peripheral device, a communication controller or the like via the I / O port 1, the DMA control circuit 2 outputs the write data to the data bus 3 and Address data indicating the address of the memory 5 to which the data is written is output to the address bus 4.

The address data output to the address bus 4 is stored in the address storage unit 6 and also output to the memory 5 in accordance with the cycle determined by the DMA memory check cycle control unit 8.

On the other hand, the write data output to the data bus 3 is written to the memory 5 according to the cycle determined by the DMA memory check cycle control unit 8 together with the ECC of the write data calculated by the memory error check unit 7. .

Then, the DMA control circuit 2 is supplied from the peripheral device, the communication controller or the like via the I / O port 1.
When the read command is output to, the DMA control circuit 2 outputs the address data of the memory 5 corresponding to the read data to the memory 5 via the address bus 4.

Then, data to which ECC or the like stored in the memory 5 corresponding to the address data is added is
The data is output to the data bus 3, and the memory error check unit 7 performs a memory check.

[0008]

Therefore, if the memory error check unit 7 performs a memory check,
Even if an error was detected, it was not possible to determine whether the cause occurred during writing in the DMA control circuit or the cause occurred during reading.

In general, when the read command and the write command have a short access time to each other, the timings of both can be measured relatively easily by using a measuring instrument. It is possible to judge whether or not it is caused by the write command.

However, in the case of a memory error after a lapse of time, even if a measuring instrument is used, the time is too long and only one of a read instruction and a write instruction can be traced. As a result, a memory error occurs. There is a problem in that it cannot be detected in a short time.

There is also a problem that it is not possible to determine whether the memory error is due to a read operation or a write operation. Further, there is a similar problem when the CPU 9 writes and reads the memory 5. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory check device capable of detecting a memory error in a short time.

[0012]

Therefore, first, in order to achieve the above object, the invention according to claim 1 adds a check code for detecting a data abnormality to data written in a memory having a plurality of ports. Check code adding means, data writing means for writing the data to the memory through a specific port, and the same cycle in which the data is written to the memory by the data writing means. A first data reading means for reading previously written data;
A first judgment is made based on the check code corresponding to the previously written data added by the check code adding means to determine whether or not the previously written data read by the data reading means is abnormal. And a determination means.

According to a second aspect of the present invention, in the memory check device according to the first aspect, second data reading means for reading data from a specific port of the memory,
In the same cycle as the cycle in which the data is read from the memory by the second data reading means, the data second read means that reads the previously written data from the memory and the read by the second data read means A second judging means for judging whether or not there is an abnormality in the outputted previously written data is added based on a check code corresponding to the previously written data added by the check code adding means. It is characterized by

Further, in the invention according to claim 3, a check code adding means for adding a check code for detecting a data abnormality to data written in a memory having a plurality of ports, and data from a specific port of the memory. In the same cycle in which the data is read from the memory by the data reading unit, the data reading unit that reads the previously written data from the memory, and the data reading unit that reads the previously written data from the memory. And a determination means for determining whether or not there is an abnormality in the previously written data based on the check code corresponding to the previously written data added by the check code adding means. .

Further, the invention according to claim 4 is the invention according to claim 2.
In the memory check device described above, it is judged whether or not there is an abnormality in the data read by the second data reading means based on a check code corresponding to the read data added by the check code adding means. It is characterized in that a third determining means for performing is added.

Further, the invention according to claim 5 is the invention according to claim 3.
In the memory check device described above, it is determined whether or not there is an abnormality in the data read by the data reading means, based on a check code corresponding to the read data added by the check code adding means. It is characterized in that the determination means of is added.

Next, the operation of the invention according to each claim will be described. In the invention according to claim 1, the check code adding means adds a check code for detecting a data abnormality to the data written in the memory, and the data writing means writes the data in the memory through a specific port. Write.

Further, in the same cycle as the cycle in which the data is written in the memory by the data writing means by the first data reading means, the previously written data is read from the memory and the first judging means Since it is determined based on the check code corresponding to the previously written data added by the check code adding means whether or not there is an abnormality in the previously written data read by the first data reading means, It is possible to quickly detect whether or not the data writing is normal.

According to a second aspect of the present invention, in the memory check device according to the first aspect, is there any abnormality in the previously written data read by the first data reading means by the first determining means? Whether or not it is determined based on the check code corresponding to the previously written data added by the check code adding means, and
Whether the previously written data read by the second data reading means is abnormal or not is determined by the check means according to the check code corresponding to the previously written data added by the check code adding means. Therefore, it is possible to provide a highly reliable memory check device.

According to a third aspect of the present invention, the data reading unit reads data from a specific port of the memory, and the data reading unit reads data from the memory in the same cycle. , The previously written data is read from the memory.

Then, the check code corresponding to the previously written data added by the check code adding means determines whether or not the previously written data read by the data reading means is abnormal by the judging means. Since it is determined based on, it is possible to quickly detect whether or not the data writing is normal.

According to a fourth aspect of the present invention, in the memory check device according to the second aspect, it is checked by the third judging means whether or not there is an abnormality in the data read by the second data reading means. Since the judgment is made based on the check code corresponding to the read data added by the code adding means, it is possible to detect an abnormality in the read data.

According to a fifth aspect of the present invention, in the memory check device according to the third aspect, the check code adding means determines whether or not the data read by the data reading means is abnormal by the second determining means. Since the determination is made based on the check code corresponding to the read data added by, the abnormality of the read data can be detected.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a memory check device according to an embodiment of the present invention. Note that the same parts as those in FIG.

As shown in the figure, a DMA control circuit 2 is connected to an I / O port 1 which is connected to peripheral equipment, a communication controller and the like. This DMA control circuit 2
It is connected to the data bus 3 and the address bus 4.

The data bus 3 has a DMA control circuit 2
Besides, the CPU 9 and the first memory error check unit 1
The 1 and 2 port memories 12 are connected. Further, the 2-port memory 12 and the second memory error check unit 13 are also connected by the data bus 3 between the 2-port memory 12 and the second memory error check unit 13.

In addition to the DMA control circuit 2, a CPU 9, a 2-port memory 12, an address storage unit 15, and a DMA memory check cycle control unit 16 are connected to the address bus 4.

When the write data is input from the I / O port 1, the DMA control circuit 2 outputs the write data to the data bus 3 and also the address data indicating the address of the 2-port memory 12 to which the write data is written. Is output to the address bus 4.

When a read command is input via the I / O port 1, the DMA control circuit 2 outputs address data indicating the address of the data read from the 2-port memory 12 to the address bus 4. .

The first memory error check unit 11 is
A check code used for memory check is added to the data written in the port memory 12. The memory check code is, for example, an ECC or a parity bit.

Further, the first memory error check unit 11
Performs an error check on the data read by the DMA control circuit 2 or the CPU 9. The 2-port memory 12 stores the write data output to the data bus 3 and the check code added by the first memory error check unit 11. The 2-port memory 12
If there is no area to which the check code is added, another memory may be prepared.

The second memory error check unit 13 is D
In the cycle determined by the MA memory check cycle control unit 16, the data written in the previous cycle is checked based on the check code added by the first memory error check unit 11.

The address storage unit 15 includes the DMA control circuit 2
Address data indicating the written address is stored in the 2-port memory 12. The DMA memory check cycle control unit 16 determines a write cycle and a read cycle of the DMA control circuit 2, and when the DMA control circuit 2 writes or reads, the DMA memory check cycle control unit 16 stores it in the address storage unit 15. By outputting the control signal, the address data, which is stored in the address storage unit 15 and indicates the previously written address, is transferred to the 2
Output to the port memory 12.

Next, the operation of the memory check device configured as described above will be described. First, when write data or a read command is input via the I / O port 1, the DMA control circuit 2 stops the operation of the CPU 9 and opens the internal bus 3 and the address bus 4.

When write data is input, DMA
The control circuit 2 outputs the write data to the data bus 3 and outputs the address data indicating the address of the 2-port memory 12 to which the write data is written to the address bus 4.

The write data output to the data bus 3 is stored in the corresponding address via the first port of the 2-port memory 12 after a check code is added by the first memory error check unit 11. It

At the same time, the address data output to the address bus 4 is stored in the address storage unit 15. The timing of storing the data output from the DMA control circuit 2, the address data, and the address data in the address storage unit 15 is determined by the DMA memory check cycle control unit 1
6.

In the next cycle, when the DMA control circuit 2 writes to or reads from the 2-port memory 12, the DMA memory check cycle control unit 16 outputs a control signal to the address storage unit 15.

When the control signal is output from the DMA memory check cycle control unit 16, the address storage unit 15 receives the control signal.
The address data stored at the time of the previous data writing is output to the 2-port memory 12 via the check address bus 14.

When the previous address data is input via the check address bus 14, the 2-port memory 12 transfers the data corresponding to this address data to the second address data.
Output to the second memory error check unit 13 via the port.

Then, the second memory error check unit 1
According to 3, if an error is detected, it can be determined that there is an error cause during writing. Also,
At the same time, in this cycle, the data stored in the 2-port memory 12 designated by the DMA control circuit 2 is read or the data is written into the 2-port memory 12 via the first port.

FIG. 2 is a diagram showing check timings by the second memory error check unit 13 when writing is continuously performed from the DMA control circuit 2 to the 2-port memory 12.

That is, in this case, the 2-port memory 12
At the same time that the data is written in, the data written in the previous cycle is checked in the second memory error check unit 13.

FIG. 3 is a diagram showing the check timing by the second memory error check unit 13 when the DMA control circuit 2 continuously reads from the 2-port memory 12.

In such a case, in response to the read instruction from the DMA control circuit 2, the 2-port memory 1
The data read from No. 2 is checked by the first memory error check unit 11.

At this time, when the first memory error check unit 11 detects a memory error, it can be determined that the cause of the memory error is at the time of reading.

At the same time, the data previously written in the 2-port memory 12 from the 2-port memory 12 is output to the second memory error check unit 13. And the second
The memory error check unit 13 determines whether an error has occurred in the data written in the 2-port memory 12 last time.

Therefore, in the memory check for this read instruction, the first memory error check unit 1
From the check result in 1 and the check result in the second memory error check unit 13, the 2-port memory 12
It is possible to determine whether or not there is a defect, or whether there is a defect in the data bus 3 connecting the DMA control circuit 2, the 2-port memory 12 and the first memory error check unit 11.

In the above description, the case where the DMA control circuit 2 writes / reads data to / from the 2-port memory 12 has been described.
It goes without saying that the memory check can be similarly performed when writing and reading data from the U9 to the 2-port memory 12.

Further, as an application of the above-mentioned memory check device, when an error is detected by the first memory error check unit 11 or the second memory error check unit 13, the control of the DMA memory check cycle control unit 16 is performed. By stopping the, it is possible to know the address at which the error occurred.

Further, if necessary, the address in which this error has occurred is saved in the address saving unit 15 or the CP
You may make it notify U9 the information of the address where this error occurred.

Therefore, according to the memory check device of the present embodiment, the error judgment of the written data is performed in the cycle after the cycle in which the DMA control circuit 2 writes the two-port memory 12. Therefore, it is possible to immediately confirm whether or not the data writing is normal.

When the 2-port memory 12 is read from the DMA control circuit 2, the first memory error check unit 11 and the second memory error check unit 1 are used.
Since the memory check is performed in 3, it is possible to provide a highly reliable memory check device.

[0054]

As described above in detail, according to the present invention,
A memory error can be detected in a short time.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a memory check device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the memory check device according to the same embodiment.

FIG. 3 is a diagram for explaining the operation of the memory check device in the same embodiment.

FIG. 4 is a diagram showing a configuration of a memory check device using a conventional DMA control circuit.

[Explanation of symbols]

 1 ... I / O port, 2 ... DMA control circuit, 3 ... Data bus, 4 ... Address bus, 9 ... CPU, 11 ... First memory error check unit, 12 ... 2-port memory, 13 ... Second memory error Check unit, 14 ... Check address bus, 15 ... Address storage unit, 16 ... DMA memory check cycle control unit.

Claims (5)

[Claims] 1. A check code adding means for adding a check code for detecting a data abnormality to data written in a memory having a plurality of ports, and a data writing for writing the data in the memory via a specific port. Means, first data reading means for reading previously written data from the memory in the same cycle in which data is written to the memory by the data writing means, and first data reading means A first judgment is made on the basis of a check code corresponding to the previously written data added by the check code adding means as to whether or not there is an abnormality in the read previously written data.
A memory check device, comprising: 2. A second data reading means for reading data from a specific port of the memory, and the same cycle in which the data is read from the memory by the second data reading means in the same cycle from the previous time. Data second reading means for reading the written data, and a previous time added by the check code adding means for determining whether or not an abnormality has occurred in the previously written data read by the second data reading means. Second determination based on the check code corresponding to the written data
2. The memory check device according to claim 1, further comprising: 3. A check code adding means for adding a check code for detecting a data abnormality to data written in a memory having a plurality of ports, a data reading means for reading data from a specific port of the memory, In the same cycle as the cycle in which the data is read from the memory by the data reading means, there is an abnormality in the data reading means for reading the previously written data from the memory and the previously written data read by the data reading means. A memory check device, comprising: a first judging means for judging whether or not the occurrence of the above occurs based on a check code corresponding to the previously written data added by the check code adding means. 4. A method for determining whether or not an abnormality has occurred in the data read by the second data reading means, based on a check code corresponding to the read data added by the check code adding means. 3. The memory check device according to claim 2, further comprising a determination means of 3. 5. A second judgment for judging whether or not there is an abnormality in the data read by said data reading means, based on a check code corresponding to the read data added by said check code adding means. 4. The memory check device according to claim 3, further comprising means.