JPH0588787A - Duplex data processor - Google Patents

Duplex data processor

Info

Publication number
JPH0588787A
JPH0588787A JP3250726A JP25072691A JPH0588787A JP H0588787 A JPH0588787 A JP H0588787A JP 3250726 A JP3250726 A JP 3250726A JP 25072691 A JP25072691 A JP 25072691A JP H0588787 A JPH0588787 A JP H0588787A
Authority
JP
Japan
Prior art keywords
data processing
bus
information
processing unit
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3250726A
Other languages
Japanese (ja)
Inventor
Akira Sekiguchi
章 関口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3250726A priority Critical patent/JPH0588787A/en
Publication of JPH0588787A publication Critical patent/JPH0588787A/en
Pending legal-status Critical Current

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  • Power Sources (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To shorten time required for obtaining the state information of the data processor on the other side through a bus intersection circuit connecting the bus of the duplexed data processor. CONSTITUTION:The electric power source disconnection information of a data processor 10 is directly written and stored in a register 28 of a data processor 20 on the other side by an electric power source disconnection detection circuit 27, and the internal state information is directly written and stored through a bus 15 by a central processing unit 11. A register 18 stores the electric power source disconnection information and the state information on the other side, and the central processing unit 11 executes the prescribed processing by directly reading the storage information of the register 18 through the bus 15 and recognizing the state on the other side. Thus, it is not necessary to provide the conventional bus intersection circuit and a means requiring the time for interrupt procedure when the duplex data processor acquires the state on the other side.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、バスにより接続される
中央処理装置、主記憶装置、および入出力制御装置、並
びにこれら装置へ給電する電源装置を有するデータ処理
装置を二重化し、このデータ処理装置両者のバス間をバ
ス交差回路が接続して相互にデータを転送する二重化デ
ータ処理装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention duplicates a data processing device having a central processing unit, a main storage unit, an input / output control unit connected by a bus, and a power supply unit for supplying power to these units, and the data processing unit is duplicated. The present invention relates to a dual data processing device in which a bus crossing circuit connects the buses of both devices and transfers data to each other.

【0002】[0002]

【従来の技術】従来、この種の二重化データ処理装置
は、耐故障性およびシステム構成管理上、一方のデータ
処理装置の中央処理装置が他方のデータ処理装置の状態
を両者のバス間を接続するバス交差回路を介して相手の
データ処理装置の各装置に送出したオーダーに返送され
るステータス情報により認識し、特に電源断のような重
要障害では個別通知線からの割込み動作によるなど、相
手のデータ処理装置の状態を知ることが必須事項となっ
ている。
2. Description of the Related Art Conventionally, a dual data processor of this type has a bus for connecting the central processing unit of one data processing unit and the other data processing unit to each other in terms of fault tolerance and system configuration management. Recognize by the status information returned to the order sent to each device of the other data processing device via the crossing circuit, and in particular, in the case of a critical failure such as power failure, an interrupt operation from the individual notification line, etc. It is essential to know the state of the device.

【0003】[0003]

【発明が解決しようとする課題】上述の従来の二重化デ
ータ処理装置は、相手のデータ処理装置の状態を認識す
るためにバス交差回路を介して両者の中央処理装置を稼
働させ、または個別に割り込み動作するような構成とな
っているので、バス交差回路による一時待ち合せ、また
は競合の動作など、接続してデータ情報を得るまでに要
する時間が大きく、データ処理装置の処理性能が低下す
る原因になるという問題点があった。
SUMMARY OF THE INVENTION In the above-mentioned conventional duplex data processing device, in order to recognize the state of the other data processing device, both central processing devices are operated via a bus crossing circuit or individually interrupted. Since it is configured to operate, it takes a long time to connect and obtain data information, such as temporary queuing by a bus crossing circuit or competition operation, which causes a decrease in the processing performance of the data processing device. There was a problem.

【0004】本発明の目的は、重要障害が発生したとき
発生側の中央処理装置を稼働してデータ情報をバスを介
してレジスタに一時蓄積し、相手側の中央処理装置を駆
動してこのレジスタが蓄積保持するデータ情報を処理さ
せることにより、上記問題点を解決する二重化データ処
理装置を提供することにある。
An object of the present invention is to operate a central processing unit on the side of occurrence when a serious failure occurs to temporarily store data information in a register via a bus, and drive the central processing unit on the other side to register this register. An object of the present invention is to provide a duplicated data processing device that solves the above-mentioned problems by processing the data information accumulated and held by the.

【0005】[0005]

【課題を解決するための手段】本発明による二重化デー
タ処理装置は、バスにより接続される中央処理装置、主
記憶装置、および入出力制御装置、並びにこれら装置へ
給電する電源装置を有するデータ処理装置を二重化し、
このデータ処理装置両者のバス間をバス交差回路が結合
して相互にデータを転送する二重化データ処理装置にお
いて、それぞれのデータ処理装置の電源断を検出する電
源断検出回路と、この検出回路から電源断の検出通知を
受け電源断情報として書き込むと共に、この通知元のデ
ータ処理装置の中央処理装置からバスを介して直接、こ
のデータ処理装置の状態情報を書き込み、これらを格納
する二つのレジスタとを有し、かつ前記中央処理装置が
相手側のデータ処理装置の電源断情報および状態情報を
格納するレジスタから、格納する情報を直接バスを介し
て所定時期に読み取り、所定の処理を実行する手段を有
する。
A duplex data processing apparatus according to the present invention is a data processing apparatus having a central processing unit, a main storage unit, an input / output control unit connected by a bus, and a power supply unit for supplying power to these units. Dualize
In a duplicated data processing device in which a bus crossing circuit is coupled between the buses of both data processing devices to transfer data to each other, a power failure detection circuit for detecting power failure of each data processing device and a power supply from this detection circuit. In addition to receiving a power failure detection notification as a power failure information, the central processing unit of the data processing apparatus that is the source of this notification writes the status information of this data processing apparatus directly via the bus, and stores two registers for storing these status information. The central processing unit has means for reading the stored information directly from the register for storing the power-off information and the status information of the data processing unit of the other party at a predetermined time and executing the predetermined processing. Have.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例を示す機能ブロック図であ
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a functional block diagram showing an embodiment of the present invention.

【0007】図示するようにデータ処理装置10,20
の両者が一組みの二重化データ処理装置を構成する。
As shown, the data processing device 10, 20
Both constitute a set of duplicated data processing device.

【0008】それぞれのデータ処理装置10,20は、
中央処理装置11,21、主記憶装置12,22、入出
力制御装置13,23および二重化構造のためのバス交
差回路14,24を有し、これらがバス15,25で接
続される。バス交差回路14,24はバス交差線30で
結合され、相互間データ転送を実施する。
The respective data processing devices 10 and 20 are
It has central processing units 11 and 21, main storage units 12 and 22, input / output control units 13 and 23, and bus crossing circuits 14 and 24 for a duplicated structure, which are connected by buses 15 and 25. The bus crossing circuits 14 and 24 are connected by a bus crossing line 30 and perform data transfer between them.

【0009】データ処理装置10,20は更に、装置内
給電用の電源装置16,26、相手のデータ処理装置2
0,10の電源装置26,16の電流断を検出する電源
断検出回路17,27、およびこの検出回路17,27
の電源断検出情報を受けて格納すると共に、相手のデー
タ処理装置20,10のバス25,15を介し中央処理
装置21,11からデータ情報を書き込み、一時蓄積格
納するレジスタ18,28を有する。
The data processing devices 10 and 20 are further provided with power supply devices 16 and 26 for supplying power to the devices, and a partner data processing device 2.
Power failure detection circuits 17 and 27 for detecting current interruptions of the power supply devices 26 and 16 of 0 and 10, and the detection circuits 17 and 27
It has the registers 18 and 28 for receiving and storing the power-off detection information of (1) and writing the data information from the central processing units (21, 11) via the buses (25, 15) of the partner data processing units (20, 10) and temporarily storing the data information.

【0010】すなわち、レジスタ18は相手のデータ処
理装置20の電源装置26が電源断になったときのビッ
ト情報を電源断検出回路17から受信し格納すると共
に、電源断のデータ処理装置20のデータ情報を中央処
理装置21からの書き込み動作により格納できる。
That is, the register 18 receives and stores the bit information when the power supply device 26 of the partner data processing device 20 is powered off from the power failure detection circuit 17 and stores the data of the data processing device 20 which is powered off. Information can be stored by a write operation from the central processing unit 21.

【0011】一方、中央処理装置11は入出力制御装置
13などにバス15を介してオーダーを送出し、返送さ
れるステータス情報を受信するので、このステータス情
報および自身の状態を相手のデータ処理装置20のレジ
スタ28にバス15を介して書き込み格納する。
On the other hand, the central processing unit 11 sends an order to the input / output control unit 13 and the like via the bus 15 and receives the status information returned, so that the status information and its own status are used as the counterpart data processing apparatus. 20 registers 20 are written and stored via the bus 15.

【0012】同様にレジスタ18は相手のデータ処理装
置20の中央処理装置21からステータス情報の書き込
み格納を受けている。
Similarly, the register 18 receives writing and storing of status information from the central processing unit 21 of the partner data processing unit 20.

【0013】中央処理装置11は定期的にバス15を介
してレジスタ18の格納内容を読み取るので、相手のデ
ータ処理装置20の状態を正常性と共に確認し、処理を
継続できる。
Since the central processing unit 11 periodically reads the contents stored in the register 18 via the bus 15, the state of the partner data processing unit 20 can be confirmed together with the normality and the processing can be continued.

【0014】このような動作は、相手のデータ処理装置
20の中央処理装置21およびレジスタ28も同様であ
る。
Such an operation is also the same for the central processing unit 21 and the register 28 of the partner data processing unit 20.

【0015】上述の実施例では電源断検出回路およびレ
ジスタのそれぞれを通知および格納する相手のデータ処
理装置に有すると図示し説明したが、原則的には何れに
備えてもよく、また、外部の共通制御装置として有して
もよい。ただし、実施例のように読み取る側の装置にレ
ジスタが備えられれば、外部状態の格納がない場合もこ
の状態を読み取りできるという利点がある。
In the above-described embodiment, the power cutoff detection circuit and the register are shown and described as being provided in the data processing device of the other party for notifying and storing, but in principle, they may be provided in any of them, and external You may have as a common control apparatus. However, if the device on the reading side is provided with a register as in the embodiment, there is an advantage that this state can be read even if the external state is not stored.

【0016】また、中央処理装置がレジスタから定期的
に格納情報を読み取ると説明したが、別に定める時期に
読み取る構成であってもよい。
Further, although it has been described that the central processing unit periodically reads the stored information from the register, the central processing unit may read the stored information at a predetermined time.

【0017】以上、説明したように、本実施例では、相
手側の中央処理装置の処理量が増大するが、一般的な稼
働/待機方式による場合では待機時の処理量が稼働時に
比較して非常に小さいので、総合的にデータ処理装置と
しての処理能力を向上できる。
As described above, in the present embodiment, the processing amount of the central processing unit on the other side increases, but in the case of the general operation / standby method, the processing amount at the time of standby is larger than that at the time of operation. Since it is very small, the processing capacity of the data processing device can be improved overall.

【0018】[0018]

【発明の効果】以上説明したように、本発明は、一方の
データ処理装置の電源断情報および中央処理装置がバス
を介して直接書き込む状態情報を格納するレジスタを備
え、このレジスタに直接バスを接続する他方のデータ処
理装置の中央処理装置が格納するデータ情報を所定の時
期に読み取って処理し、それぞれが相手側のデータ処理
装置の稼働状態を認識することにより、バス交差回路を
介しての一時待ち合わおよび割り込み動作における競合
処理など、相手側のデータ処理装置の状態情報取得まで
の時間を排除できるので、データ処理性能を向上させる
効果がある。
As described above, the present invention is provided with a register for storing the power-off information of one data processing unit and the status information directly written by the central processing unit via the bus. The data information stored in the central processing unit of the other data processing device to be connected is read and processed at a predetermined time, and each recognizes the operating state of the data processing device on the other side, so Since it is possible to eliminate the time until the acquisition of the status information of the data processing device on the other side, such as the conflict processing in the temporary waiting and the interrupt operation, it is possible to improve the data processing performance.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す機能ブロック図であ
る。
FIG. 1 is a functional block diagram showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10,20 データ処理装置 11,21 中央処理装置 12,22 主記憶装置 13,23 入出力制御装置 14,24 バス交差回路 15,25 バス 16,26 電源装置 17,27 電源断検出回路 18,28 レジスタ 30 バス交差線 10,20 Data processing device 11,21 Central processing device 12,22 Main memory device 13,23 Input / output control device 14,24 Bus crossing circuit 15,25 Bus 16,26 Power supply device 17,27 Power failure detection circuit 18,28 Register 30 Bus crossing line

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 バスにより接続される中央処理装置、主
記憶装置、および入出力制御装置、並びにこれら装置へ
給電する電源装置を有するデータ処理装置を二重化し、
このデータ処理装置両者のバス間をバス交差回路が結合
して相互にデータを転送する二重化データ処理装置にお
いて、それぞれのデータ処理装置の電源断を検出する電
源断検出回路と、この検出回路から電源断の検出通知を
受け電源断情報として書き込むと共に、この通知元のデ
ータ処理装置の中央処理装置からバスを介して直接、こ
のデータ処理装置の状態情報を書き込み、これらを格納
する二つのレジスタとを有し、かつ前記中央処理装置が
相手側のデータ処理装置の電源断情報および状態情報を
格納するレジスタから、格納する情報を直接バスを介し
て所定時期に読み取り、所定の処理を実行する手段を有
することを特徴とする二重化データ処理装置。
1. A data processing device having a central processing unit, a main storage device, an input / output control device connected by a bus, and a power supply device for supplying power to these devices is duplicated.
In a duplicated data processing device in which a bus crossing circuit is coupled between the buses of both data processing devices to transfer data to each other, a power-off detection circuit for detecting power-off of each data processing device and a power supply from this detection circuit. In addition to writing the power failure information as a power failure information, the central processing unit of the data processing device that is the source of the notification writes the status information of this data processing device directly through the bus, and two registers for storing these. The central processing unit has means for reading the stored information directly from the register for storing the power-off information and the status information of the partner data processing apparatus at a predetermined time through the bus and executing the predetermined processing. A duplicated data processing device having.
JP3250726A 1991-09-30 1991-09-30 Duplex data processor Pending JPH0588787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3250726A JPH0588787A (en) 1991-09-30 1991-09-30 Duplex data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3250726A JPH0588787A (en) 1991-09-30 1991-09-30 Duplex data processor

Publications (1)

Publication Number Publication Date
JPH0588787A true JPH0588787A (en) 1993-04-09

Family

ID=17212138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3250726A Pending JPH0588787A (en) 1991-09-30 1991-09-30 Duplex data processor

Country Status (1)

Country Link
JP (1) JPH0588787A (en)

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