JPH0586853B2 - - Google Patents
Info
- Publication number
- JPH0586853B2 JPH0586853B2 JP59098090A JP9809084A JPH0586853B2 JP H0586853 B2 JPH0586853 B2 JP H0586853B2 JP 59098090 A JP59098090 A JP 59098090A JP 9809084 A JP9809084 A JP 9809084A JP H0586853 B2 JPH0586853 B2 JP H0586853B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- gold
- germanium
- nickel
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 38
- 229910052759 nickel Inorganic materials 0.000 claims description 19
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 claims description 18
- 239000010936 titanium Substances 0.000 claims description 15
- 229910052719 titanium Inorganic materials 0.000 claims description 15
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 14
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 229910000927 Ge alloy Inorganic materials 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 13
- 239000010931 gold Substances 0.000 description 13
- 229910052737 gold Inorganic materials 0.000 description 13
- 238000005275 alloying Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、微細形状が形成可能であり、かつ超
低抵抗率を有するｎ型半導体へのオーム性電極の
製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing an ohmic electrode for an n-type semiconductor, which can form a fine shape and has ultra-low resistivity.
従来のｎ型半導体、特にGaAsなどの化合物半
導体へのオーム性電極としては、金−ゲルマニウ
ム膜上をニツケル膜で被覆した構成の電極が良く
用いられているが、この電極の製造工程中には、
熱処理あるいは合金化と称する電極金属とGaAs
結晶との合金化の過程を必要とする。ところが、
電極金属が金−ゲルマニウム膜及び該膜上をニツ
ケル膜で被覆した構成のものでは、この熱処理合
金化の過程で電極金属が凝集を起こし、所望の形
状の電極を形成できないという欠点、及び該熱処
理合金化の過程で、合金化が不均一に起こり、オ
ーム性コンタクト抵抗率が十分小さくならないと
う欠点があつた。また、同種の理由により電極の
横方向の抵抗が大きいという欠点もあつた。さら
に、熱処理を450℃程度の高温で行なわなければ
ならないという欠点もあつた。
As an ohmic electrode for conventional n-type semiconductors, especially compound semiconductors such as GaAs, an electrode consisting of a gold-germanium film covered with a nickel film is often used, but during the manufacturing process of this electrode, ,
Electrode metal and GaAs through heat treatment or alloying
Requires a process of alloying with crystals. However,
In the structure in which the electrode metal is a gold-germanium film and the film is covered with a nickel film, the electrode metal aggregates during the heat treatment alloying process, making it impossible to form an electrode in the desired shape. During the alloying process, alloying occurred non-uniformly and the ohmic contact resistivity was not sufficiently reduced. Furthermore, for the same reason, there was also the drawback that the lateral resistance of the electrode was large. Another drawback was that heat treatment had to be carried out at a high temperature of about 450°C.
合金化の不均一を防ぎ、電極金属の凝縮を防ぐ
には、ｎ型半導体と、金−ゲルマニウム及びニツ
ケル膜との間に両者と反応しないが、その一部分
を通す物質の膜を形成し、合金化を均一に、かつ
おだやかに行なわせれば良い。しかし、該物質と
して金属のような緻密な物質を用いると、拡散が
大きく制限され、合金化が十分行なわれない。一
方、電極の横方向の抵抗を低くするためには、該
金−ゲルマニウム及びニツケル膜の上に金膜を被
覆するのが良いが、この構成では熱処理を行なう
と金過剰になり、オーム性コンタクト抵抗率が大
きくなるという欠点があつた。 In order to prevent non-uniform alloying and to prevent condensation of the electrode metal, a film of a substance that does not react with the n-type semiconductor and the gold-germanium and nickel films but allows a portion of them to pass through is formed between the n-type semiconductor and the gold-germanium and nickel films. It is best to make the process uniform and gentle. However, when a dense substance such as a metal is used as the substance, diffusion is greatly restricted and alloying is not performed sufficiently. On the other hand, in order to lower the lateral resistance of the electrode, it is better to coat the gold-germanium and nickel films with a gold film, but with this configuration, heat treatment results in excess gold, resulting in an ohmic contact. The drawback was that the resistivity increased.
本発明は、上記従来のオーム性電極形成の欠
点、電極金属が凝集を起こし、所望形状にできな
い点，オーム性コンタクト抵抗率が十分小さくな
らない点、横方向の抵抗が大きい点のいずれをも
解決するものである。
The present invention solves all of the above-mentioned drawbacks of conventional ohmic electrode formation, such as the fact that the electrode metal aggregates and cannot be formed into a desired shape, the ohmic contact resistivity not being sufficiently small, and the lateral resistance being large. It is something to do.
本発明は、これらの欠点を解決するために、金
−ゲルマニウム膜及びニツケル膜の上をチタン膜
及び全膜で被覆し、低温で熱処理を行なう。
In order to solve these drawbacks, the present invention covers the gold-germanium film and the nickel film with a titanium film and the entire film, and heat-treats the film at a low temperature.
以下図を用いて本発明を説明する。第１図は本
発明の一実施例であつて、１はｎ型半導体、２は
金−ゲルマニウム膜、３はニツケル膜、４はチタ
ン膜、５は低抵抗金属膜である。第２図は、その
具体例として、不純物濃度３×1018cm-3のｎ型
GaAs上に設けた900Åの厚さの金−ゲルマニウ
ム合金膜２上に、100Åの厚さのニツケル膜３を
設け、その上に1000Åのチタン膜４を設け、その
上に2000Åの金膜５を設けて、熱処理合金化した
もので、そのオーム性抵抗率の熱処理温度依存性
を示したものである。360℃以下では金−ゲルマ
ニウム合金の融点で以下であるため、430℃以上
ではチタン膜が破れて金過剰になる事及び、
GaAsとの界面のチタンを通した合金化が過剰に
なるために、抵抗率がやや高くなつているが、
370℃乃至400℃の範囲では従来のｎ型GaAsへの
オーム性電極に比べ数倍乃至１桁程度低くなつて
おり、先に説明した本発明の作用効果をよく反映
している。
The present invention will be explained below using the figures. FIG. 1 shows an embodiment of the present invention, in which 1 is an n-type semiconductor, 2 is a gold-germanium film, 3 is a nickel film, 4 is a titanium film, and 5 is a low-resistance metal film. Figure 2 shows, as a specific example, an n-type device with an impurity concentration of 3×10 18 cm -3.
A nickel film 3 with a thickness of 100 Å is provided on a gold-germanium alloy film 2 with a thickness of 900 Å provided on GaAs, a titanium film 4 with a thickness of 1000 Å is provided on top of the nickel film 3, and a gold film 5 with a thickness of 2000 Å is provided on top of that. The graph shows the dependence of the ohmic resistivity on the heat treatment temperature. At temperatures below 360℃, the melting point of the gold-germanium alloy is below, so at temperatures above 430℃, the titanium film will break and gold will become excessive.
The resistivity is slightly higher due to excessive alloying through titanium at the interface with GaAs.
In the range of 370° C. to 400° C., the temperature is several times to one order of magnitude lower than that of conventional ohmic electrodes for n-type GaAs, which reflects well the effects of the present invention described above.
第３図は本発明の他の実施例であつて、第１図
と反応箇所は同一番号であり、６はｎ型半導体
層、７はｐ型半導体層、８はクロム膜、９は金膜
である。本発明のオーム性電極は、従来のものに
比べ低温での熱処理が可能であり、従つて、本実
施例でｐ型及びｎ型半導体へのオーム性電極を同
時に熱処理して、低抵抗化することが可能であ
る。 FIG. 3 shows another embodiment of the present invention, in which the reaction parts have the same numbers as in FIG. 1, 6 is an n-type semiconductor layer, 7 is a p-type semiconductor layer, 8 is a chromium film, and 9 is a gold film. It is. The ohmic electrode of the present invention can be heat-treated at a lower temperature than conventional ones. Therefore, in this example, the ohmic electrodes for p-type and n-type semiconductors are heat-treated at the same time to reduce the resistance. Is possible.
これは、ｎ型，ｐ型半導体を用いるバイポーラ
トランジスタ、ダイオード、pn接合型電界効果
トランジスタなどへ適用可能であり、工程が簡単
化できるという利点がある。 This method can be applied to bipolar transistors, diodes, pn junction field effect transistors, etc. using n-type and p-type semiconductors, and has the advantage of simplifying the process.
本発明者が、前記物質及び金膜被覆方法につい
て実験的に究明したところ以下の事実が判明し
た。すなわち、本発明のごとく、ｎ型GaAs結晶
表面に金−ゲルマニウム合金膜を設け、その上に
ニツケル膜を設けその上にチタン膜を設け、さら
にその上に金膜を設けて、熱処理合金化すると、
まずチタンの一部が金−ゲルマニウム層及びニツ
ケル膜を通して拡散し、GaAs層との界面に析出
する。その後に、金−ゲルマニウム及びニツケル
が、このチタン層を通して、おだやかに、かつ均
一に拡散する事により、凝縮が無く、抵抗率の低
いオーム性電極が形成される。 The present inventor has experimentally investigated the above-mentioned substance and gold film coating method, and has found the following facts. That is, as in the present invention, a gold-germanium alloy film is provided on the surface of an n-type GaAs crystal, a nickel film is provided on top of the gold-germanium alloy film, a titanium film is provided on top of the gold film, a gold film is further provided on top of the gold film, and the alloy is heat treated. ,
First, a portion of titanium diffuses through the gold-germanium layer and the nickel film and precipitates at the interface with the GaAs layer. Thereafter, the gold-germanium and nickel diffuse slowly and uniformly through this titanium layer, forming a condensation-free, low resistivity ohmic electrode.
一方、チタン膜の大部分は、金−ゲルマニウム
及びニツケル膜と、金膜とを分離する膜として残
り、熱処理合金化を行なつても、金−ゲルマニウ
ム及びニツケル合金層が金過剰になるのを防いで
いるのみならず、残つた金膜は電極の横方向の抵
抗を低くする役目をする。 On the other hand, most of the titanium film remains as a film that separates the gold film from the gold-germanium and nickel films, and even after heat treatment and alloying, the gold-germanium and nickel alloy layers do not become too gold. In addition to protecting the electrodes, the remaining gold film also serves to lower the lateral resistance of the electrode.
発明者は、以上の効果が、各金属膜厚及び熱処
理合金化温度と深い相関関係にあると考えて、注
意深い検討を行なつた結果、金−ゲルマニウム膜
厚100Å〜2000Å，ニツケル膜厚10Å〜500Å，チ
タン膜厚100Å〜4000Å，低抵抗金属を1000Å以
上とすれば、前記効果が得られる事を確認した。 The inventor believes that the above effects are deeply correlated with the thickness of each metal film and the heat treatment alloying temperature, and as a result of careful study, the inventors found that the thickness of the gold-germanium film is 100 Å to 2000 Å, and the thickness of the nickel film is 10 Å to 200 Å. It was confirmed that the above effect can be obtained by setting the thickness of the titanium film to 500 Å, the thickness of the titanium film from 100 Å to 4000 Å, and the thickness of the low-resistance metal to 1000 Å or more.
本発明の効果は、電気的特性はもとより、微細
な幾何学的形状を形成することができるなど、前
記従来の欠点をその原因から取り除くことに成功
したことは勿論であるが、本発明に於いて、金−
ゲルマニウム及びニツケル膜厚を薄くした場合
に、熱処理合金化した時侵食されるGaAs結晶の
深さを、従来のものよりも大幅に小さくする事が
可能である事も特筆すべきである。前記侵食が及
ぼすデバイス製造上の問題は特にエピタキシヤル
層を使用するデバイスでは重大な影響を与えてい
た。 The effects of the present invention include not only the electrical properties but also the ability to form fine geometrical shapes, which are of course successful in eliminating the above-mentioned conventional drawbacks. It's gold-
It is also noteworthy that when the germanium and nickel films are made thinner, the depth of the GaAs crystal that is eroded during heat treatment alloying can be made much smaller than in the conventional case. The device manufacturing problems caused by the erosion have a particularly serious impact on devices using epitaxial layers.
また、従来のｎ型GaAsへのオム性電極に比べ
て低温で熱処理が可能なため、ｐ型GaAsへのオ
ーム性電極と同時に熱処理を行うことが容易にな
つたことも重要な点である。 Another important point is that it is now easier to heat-treat the ohmic electrode on p-type GaAs at the same time as the ohmic electrode on p-type GaAs because it can be heat-treated at a lower temperature than the conventional ohmic electrode on n-type GaAs.
例えば、ヘテロ接合バイポーラトランジスタを
製作する場合、素子の高速特性を実現するために
はベース抵抗を低減する必要があるが、そのため
には極めて細いエミツタ電極を形成する必要があ
る。またその場合、同時にエミツタ抵抗も低減す
る必要があり、コンタクト抵抗率及びメタル自体
の抵抗も十分低くなければはらない。この場合、
本発明を適用すれば、以上説明したように極めて
細く、かつ抵抗率の低いオーム性抵抗を形成する
事ができ、従つて素子の特性を著しく向上させる
事ができるという利点がある。
For example, when manufacturing a heterojunction bipolar transistor, it is necessary to reduce the base resistance in order to achieve high-speed characteristics of the device, but to do so, it is necessary to form an extremely thin emitter electrode. In that case, it is also necessary to reduce the emitter resistance, and the contact resistivity and the resistance of the metal itself must also be sufficiently low. in this case,
By applying the present invention, as explained above, it is possible to form an ohmic resistor that is extremely thin and has a low resistivity, which has the advantage that the characteristics of the device can be significantly improved.
以上のような効果は、FET，レーザダイオー
ド，フオトダイオード等の素子においても同様で
ある。 The above-mentioned effects are the same in elements such as FETs, laser diodes, and photodiodes.
第１図は本発明の電極構成の一実施例を示す
図、第２図は本発明の具体例として、３×1018cm
−３ドープのｎ型GaAsに対するオーム性コンタク
ト抵抗率の熱処理温度依存性を示す図、第３図は
本発明のｎ型及びｐ型半導体に対するオーム性コ
ンタクトの同時熱処理の一実施例を示す図であ
る。
１，６……ｎ型半導体、２……金−ゲルマニウ
ム膜、３……ニツケル膜、４……チタン膜、５…
…低抵抗金属膜、７……ｐ型半導体、８……クロ
ム膜、９……金膜。
Figure 1 is a diagram showing an example of the electrode configuration of the present invention, and Figure 2 is a diagram showing an example of the electrode configuration of the present invention.
FIG . 3 is a diagram showing the dependence of ohmic contact resistivity on heat treatment temperature for doped n-type GaAs; FIG. be. 1, 6...n-type semiconductor, 2...gold-germanium film, 3...nickel film, 4...titanium film, 5...
...Low resistance metal film, 7...p-type semiconductor, 8...chromium film, 9...gold film.
Claims (1)
合金膜上をニツケル膜で被覆し、該ニツケル膜上
をチタン膜で被覆し、該チタン膜上を低抵抗金属
膜で被覆した後、熱処理を行なつて、ｎ型半導体
へオーム性電極を形成する方法において、前記金
−ゲルマニウム膜厚を100Å乃至2000Å，前記ニ
ツケル膜厚を10Å乃至500Å，前記チタン膜厚を
100Å乃至4000Å、前記低抵抗金属を1000Å以上
とし、前記熱処理を370乃至400℃で行なうことを
特徴とする半導体オーム性電極の形成方法。1. After covering the gold-germanium alloy film provided on the n-type GaAs crystal with a nickel film, covering the nickel film with a titanium film, and covering the titanium film with a low-resistance metal film, heat treatment is performed. In the method for forming an ohmic electrode on an n-type semiconductor, the thickness of the gold-germanium film is 100 Å to 2000 Å, the thickness of the nickel film is 10 Å to 500 Å, and the thickness of the titanium film is 100 Å to 2000 Å.
100 Å to 4000 Å, the low resistance metal has a thickness of 1000 Å or more, and the heat treatment is performed at 370 to 400°C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9809084A JPS60242619A (en) | 1984-05-16 | 1984-05-16 | Formation of semiconductor ohmic electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9809084A JPS60242619A (en) | 1984-05-16 | 1984-05-16 | Formation of semiconductor ohmic electrode |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60242619A JPS60242619A (en) | 1985-12-02 |
| JPH0586853B2 true JPH0586853B2 (en) | 1993-12-14 |
Family
ID=14210641
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9809084A Granted JPS60242619A (en) | 1984-05-16 | 1984-05-16 | Formation of semiconductor ohmic electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60242619A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2761735B2 (en) * | 1988-10-04 | 1998-06-04 | 株式会社村田製作所 | Heat resistant ohmic electrode and method of manufacturing the heat resistant ohmic electrode |
| US5179041A (en) * | 1989-06-16 | 1993-01-12 | Sumitomo Electric Industries, Ltd. | Method for manufacturing an electrode structure for III-V compound semiconductor element |
| JPH0387067A (en) * | 1989-06-16 | 1991-04-11 | Sumitomo Electric Ind Ltd | Electrode structure of iii-v compound semiconductor element and formation thereof |
| JPH04298028A (en) * | 1991-03-26 | 1992-10-21 | Murata Mfg Co Ltd | Method of forming ohmic electrode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5880872A (en) * | 1981-11-09 | 1983-05-16 | Nippon Telegr & Teleph Corp <Ntt> | Semicondutor device |
| JPS58210665A (en) * | 1982-06-02 | 1983-12-07 | Hitachi Ltd | Semiconductor device |
-
1984
- 1984-05-16 JP JP9809084A patent/JPS60242619A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5880872A (en) * | 1981-11-09 | 1983-05-16 | Nippon Telegr & Teleph Corp <Ntt> | Semicondutor device |
| JPS58210665A (en) * | 1982-06-02 | 1983-12-07 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60242619A (en) | 1985-12-02 |
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