JPS5880872A - Semicondutor device - Google Patents

Semicondutor device

Info

Publication number
JPS5880872A
JPS5880872A JP17828781A JP17828781A JPS5880872A JP S5880872 A JPS5880872 A JP S5880872A JP 17828781 A JP17828781 A JP 17828781A JP 17828781 A JP17828781 A JP 17828781A JP S5880872 A JPS5880872 A JP S5880872A
Authority
JP
Japan
Prior art keywords
layer
alloy
titanium
molybdenum
tin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17828781A
Other languages
Japanese (ja)
Other versions
JPS6211793B2 (en
Inventor
Shuichi Kanamori
金森 周一
Yoshiki Wada
和田 嘉記
Tadashi Matsumoto
忠 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP17828781A priority Critical patent/JPS5880872A/en
Publication of JPS5880872A publication Critical patent/JPS5880872A/en
Publication of JPS6211793B2 publication Critical patent/JPS6211793B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To remarkably reduce the thermal unstability of a semicondutor device at a high temperature by sufficiently reducing the thickness of an Au-Ge-Ni alloy layer with the remaining thickness necessary to electrically ohmically contact and isolating through a thick conductor layer and a diffused barrier layer, thereby minimizing the invasion of electrode metal into the semiconductor. CONSTITUTION:When Au is used for a condutor layer 7, a 3-layer structure of titanium (Ti)-nitrided titanium (TiN)/titanium (Ti) or molybdenum (Mo)/nitrided molybdenum (MoN)/molybdenum (Mo) is considered as a diffused barrier layer 6, and when aluminum (Al) is used as the condutor layer, the barrier layer can be formed in a 2-layer structure of TiN/Ti or MoN/Mo. Then, electrodes are formed by adhering by a vacuum deposition method Au-Ge alloy containing approx. 12wt% of Ge and Ni in thicknesses of 450 and 50Angstrom , and are heat treated at 500 deg.C for 30sec. in a hydrogen furnace, thereby forming an ohmic contact layer of Au-Ge-Ni alloy. Subsequently, Ti, TiN, Ti are respectively sequentially formed by a sputtering method in thicknesses of 100, 200 and 500Angstrom , and the conductor layer of the Au is eventually formed by an electrically plating method in approx. 1mum thick.

Description

【発明の詳細な説明】 不発明はガリウム砒素半導体装置において、耐熱性に優
れたオーミック接触用電極構成に関するものである0 カリウム砒素(GaAs )半導体装置の例えば電界幼
果トランジスタCFET)などのn形Ga Aaへのオ
ーミック接触用材料としての金・ゲルマニウム・ニッケ
ル(Au −Go −Ni )合金層オーミック接触抵
抗が低く、ボンティングが容易で耐熱性、耐食性。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode structure for ohmic contact with excellent heat resistance in a gallium arsenide semiconductor device. A gold-germanium-nickel (Au-Go-Ni) alloy layer as an ohmic contact material for GaAa has low ohmic contact resistance, easy bonding, heat resistance, and corrosion resistance.

安定性に優れているため&C現在最も広く用iられてい
るO Au−Ga−Ni合金を用%Aたオーミック接触
は、n形GaA−に対して共晶組成に近いAu−Go金
合金蒸着したのち、つづけてN1t−蒸着し、水素雰囲
気中で熱処理をして形成されるが一均一で接触抵抗の低
い合金層管形成するためK tX、 Au g対する−
の量、Au−Goに対するNlの厚さ、熱1slfF尋
が微妙に影響することが知られている。An−Go−N
i合金がGa Asとオーミック接触を形成する際には
、実際K u Ni −As −Ga e Au −G
aなどの合金層が界面に形成されると言われており電極
金属のGa As基板への侵食t−最小限におさえるた
めにAu−G・−N1合金層の厚さはあま9厚くできな
い。GaAsFETの高周波化にともない電極パターン
が微細化されつつあり第1図に示すように、ドレイン1
.ゲート2.ソース3の相互の間隙はきわめて狭いもの
となってきている04はGaAaj&板を示す。しがも
高(力化のために紘電極をToま9薄くできないために
1 ドレインlおよびソース3の電極金属主としてAu
のGaAs中への侵入による耐圧低下中短絡不良が起こ
p易<、m造時における歩留9低下。
Due to its excellent stability, the most widely used ohmic contact at present is the Au-Ga-Ni alloy. After that, N1t is deposited and heat treated in a hydrogen atmosphere to form a uniform alloy layer tube with low contact resistance.
It is known that the amount of Nl, the thickness of Nl relative to Au-Go, and the heat of 1 slfF fathom have a subtle effect. An-Go-N
When the i-alloy forms ohmic contact with GaAs, in fact K u Ni - As - Ga e Au - G
It is said that an alloy layer such as a is formed at the interface, and the thickness of the Au-G--N1 alloy layer cannot be made too thick in order to minimize corrosion of the electrode metal to the GaAs substrate. As the frequency of GaAsFET becomes higher, the electrode pattern is becoming finer, and as shown in Figure 1, the drain 1
.. Gate 2. The mutual gap between the sources 3 has become extremely narrow. 04 indicates the GaAaj & plate. However, the electrode metal of the drain l and source 3 is mainly Au.
Short-circuit failure occurs during breakdown voltage drop due to intrusion into GaAs. Yield decreases by 9 when manufacturing.

使PF3時における信頼度低下の嵌置となってき九〇こ
のように、n杉Ga Asに対するオーミック!l菖用
亀懐に単層の金属を使用することは伽Asl’ETの^
周波比、1IiII′wL力化の双方を同時に満足させ
る上で大@な障害となっていた◎ 不@明はこnらの問題を解決するために電極に独特の工
夫をこらし、電気的特性音確保しながら1しかも耐熱性
に優C%高い信頼性が期待できるオーミック接触用亀1
am造を提供しようとするものでるり、以下図1klt
−用いて本発明の詳細な説明する0 第2図はGa Ass F E Tのソースまたはドレ
イン電極における不発明の実施例を示したもので1L図
中2にアルミニウムなどによるゲート電極、4tmGa
As基板、5は薄いAu−Ge−Ni合金にょるオーミ
ック接触層、6は単層または多層金属による拡散障一層
、7は導体層である。
It becomes the insertion of reliability deterioration at the time of PF3.90 In this way, ohmic for nsugi Ga As! The use of a single layer of metal for the turtle shell for irises is a good thing for Asl'ET.
This was a major obstacle in satisfying both the frequency ratio and 1IiII'wL power at the same time. ◎ To solve these problems, Fujiaki devised a unique method for the electrode and improved its electrical characteristics. Ohmic contact turtle 1 that can be expected to have high reliability while ensuring sound and excellent heat resistance.
Ruri is trying to provide AM construction, the figure below is 1klt
- Detailed explanation of the present invention using Figure 2 shows an embodiment of the non-inventive source or drain electrode of a Ga Ass FET.
An As substrate, 5 an ohmic contact layer made of a thin Au-Ge-Ni alloy, 6 a diffusion barrier layer made of a single or multilayer metal, and 7 a conductor layer.

、パ。, Pa.

拡散障壁NIAGは、導体層7にムut−用いる場合に
はチタン(Ti)/m化チタン(’I’IN)/チタン
(Ti)17tはモリブデン(Mo ) /窒化モリブ
デン(MoN)/モリブテン(Mo )の3層構造が例
として考えらnる。
When the diffusion barrier NIAG is used in the conductor layer 7, titanium (Ti)/titanium nitride ('I'IN)/titanium (Ti) 17t is molybdenum (Mo)/molybdenum nitride (MoN)/molybdenum ( The three-layer structure of Mo) can be considered as an example.

tた、導体層にアルミニウム(At)k用いる場合には
、拡散障壁層はTiN/TieたはMoN/ Moの2
層構造とすること1できる。いすnの場合も、それ程高
い耐熱性が要求されない場合に鉱、拡散障壁層6にTl
、Moなどの単層金輌tJ+Ivhることもできる。
In addition, when aluminum (At) is used for the conductor layer, the diffusion barrier layer is made of TiN/Tie or MoN/Mo2.
It is possible to have a layered structure. In the case of Isun, if high heat resistance is not required, Tl is added to the diffusion barrier layer 6.
, a single layer metal such as Mo can also be used.

つぎに、W、他形成の手順の一例としては、まず12w
t%楊度のGo f含むAu−Ge合金とN1Yr真空
蒸着法によりそれぞれ450λ、50Aの厚さに付着さ
せ、水素炉中で500℃、30秒の熱処理七粁ないtA
u−Go−Ni合金のオーミック接触層を形成する。
Next, as an example of the procedure for forming W and others, first, 12w
An Au-Ge alloy containing t% of GoF and N1Yr were deposited to a thickness of 450λ and 50A by vacuum evaporation method, respectively, and heat-treated at 500℃ for 30 seconds in a hydrogen furnace for 7 minutes.
Form an ohmic contact layer of u-Go-Ni alloy.

つづいて、スパッタリング法によりTi 、 TIN 
、 Ti會それぞれ厚さ100λ、200λ、5oO^
に順次形成させる。このときTiNはターゲットにTi
を用いアルゴン、窒素混合ガス中で反応性スパッタリン
グ法にエリ形成させることもできる。最後にAuの導体
層t−電気めっき法により約1/Jm形成する0Au−
Ge−Ni合金層形成のための熱処理は金めつき工程終
了後に行なうことも可能であり、これにょ9工Sは著し
く簡略化される◎ 以上のように1本発明のオーミック接触用電極の構造上
の特徴は、従来導体層も兼ねていた厚いAu−G・−N
1合金層の厚さを、電気的なオ、−ミツ2.り恢触tと
るに必要な厚さを残して十分薄くシ、厚i導体層と拡散
障壁層を介して分離したことI/cT。
Subsequently, Ti, TIN was formed by sputtering method.
, Ti thickness 100λ, 200λ, 5oO^ respectively
are formed sequentially. At this time, TiN is the target
The edge can also be formed by reactive sputtering in a mixed gas of argon and nitrogen. Finally, a conductor layer t of Au is formed by about 1/Jm by electroplating.
The heat treatment for forming the Ge-Ni alloy layer can also be performed after the gold plating process is completed, and this greatly simplifies the 9-step process. As described above, the structure of the ohmic contact electrode of the present invention The above feature is due to the thick Au-G/-N layer, which conventionally also served as a conductor layer.
1. The thickness of the alloy layer is determined by the electrical resistance.2. The I/cT is made thin enough, leaving the necessary thickness for the reconstitution, and is separated through a thick conductor layer and a diffusion barrier layer.

9、これにより電極金属の半導体中への侵入を最小@に
とどめ%高温における熱的不安定性を着しく減少するこ
とができる〇 本発明のオーミック接触用電極構成はGI Am FE
TやICのソースおよびドレイン電極のはか、ガンダイ
オード、インバットダイオード、などにも応用すること
が可能である。また1本電極構成扛、オーミック接触用
Au−G・−N1合金層と導体層と拡散wm層によ多分
離してiるために1導体層の材料゛選択の自由度が大で
あり s GaAs I Ct−ゲート電極を含めア/
I/ i =ラム系の2謙で統一することも可能である
9. This makes it possible to minimize the penetration of the electrode metal into the semiconductor and significantly reduce thermal instability at high temperatures. The ohmic contact electrode configuration of the present invention is GI Am FE
It can also be applied to source and drain electrodes of transistors and ICs, Gunn diodes, invat diodes, and the like. In addition, since the single electrode structure is multi-separated into the Au-G/-N1 alloy layer for ohmic contact, the conductor layer, and the diffusion layer, there is a great degree of freedom in selecting the material for the single conductor layer. GaAs I Ct - including gate electrode
It is also possible to unify I/i = 2 ken of Ram system.

以上説明したように1本発明にょるオーイック厚い導体
層と拡散障壁層で分離した構造としているためrcs*
極金属の半導体中への侵入が殆んどなく耐圧劣化や短絡
不良などを起こすことがなくなるために高温熱処1II
rcよる歩留りが同上するはρ島、夾便用時における0
1軸性が著しく同上する利点がある。
As explained above, since the structure according to the present invention is separated by the thick conductor layer and the diffusion barrier layer, the rcs*
High-temperature heat treatment 1II is used because there is almost no penetration of polar metal into the semiconductor and no breakdown voltage deterioration or short circuit failure occurs.
The yield by rc is the same as the above, ρ island, 0 when using consignment.
It has the advantage of being significantly uniaxial.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来vGaAs F)CTの断面概略図、籐2
図aGaAsFETのソースまた蝶ドレイン電極におり
る不発−の実施例を示す。
Figure 1 is a cross-sectional schematic diagram of a conventional vGaAs F) CT, rattan 2
Figure a shows an example of a misfire that falls on the source or drain electrode of a GaAs FET.

Claims (1)

【特許請求の範囲】[Claims] n杉ガリウム゛砒素基板に対してオーミック接触用Au
−Ge−Ni合金層を接触させ、さらにオーζツク峯触
層の上部に辱い導体層t*しかつ、オーミック恢触鳩と
前記の導体層の間に電化チタンまたは富化モリブデンを
含む拡散障壁層をもつ構造の電極を有すること1を特徴
とする半導体装置0
Au for ohmic contact with n-sugi gallium arsenide substrate
- The Ge-Ni alloy layer is in contact with the conductor layer t* on top of the ohmic contact layer, and the diffusion containing electrified titanium or enriched molybdenum is provided between the ohmic contact layer and the conductor layer. Semiconductor device 0 characterized by having an electrode having a structure with a barrier layer 1
JP17828781A 1981-11-09 1981-11-09 Semicondutor device Granted JPS5880872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17828781A JPS5880872A (en) 1981-11-09 1981-11-09 Semicondutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17828781A JPS5880872A (en) 1981-11-09 1981-11-09 Semicondutor device

Publications (2)

Publication Number Publication Date
JPS5880872A true JPS5880872A (en) 1983-05-16
JPS6211793B2 JPS6211793B2 (en) 1987-03-14

Family

ID=16045824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17828781A Granted JPS5880872A (en) 1981-11-09 1981-11-09 Semicondutor device

Country Status (1)

Country Link
JP (1) JPS5880872A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60120560A (en) * 1983-12-05 1985-06-28 Fujitsu Ltd Semiconductor device
JPS60242619A (en) * 1984-05-16 1985-12-02 Nippon Telegr & Teleph Corp <Ntt> Formation of semiconductor ohmic electrode
JPS6360526A (en) * 1986-08-30 1988-03-16 Sharp Corp Manufacture of semiconductor device
KR20140135786A (en) * 2012-02-24 2014-11-26 스카이워크스 솔루션즈, 인코포레이티드 Improved structures, devices and methods related to copper interconnects for compound semiconductors

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60120560A (en) * 1983-12-05 1985-06-28 Fujitsu Ltd Semiconductor device
JPH0216589B2 (en) * 1983-12-05 1990-04-17 Fujitsu Ltd
JPS60242619A (en) * 1984-05-16 1985-12-02 Nippon Telegr & Teleph Corp <Ntt> Formation of semiconductor ohmic electrode
JPH0586853B2 (en) * 1984-05-16 1993-12-14 Nippon Telegraph & Telephone
JPS6360526A (en) * 1986-08-30 1988-03-16 Sharp Corp Manufacture of semiconductor device
KR20140135786A (en) * 2012-02-24 2014-11-26 스카이워크스 솔루션즈, 인코포레이티드 Improved structures, devices and methods related to copper interconnects for compound semiconductors

Also Published As

Publication number Publication date
JPS6211793B2 (en) 1987-03-14

Similar Documents

Publication Publication Date Title
JP2509713B2 (en) Silicon carbide semiconductor device and manufacturing method thereof
US6043513A (en) Method of producing an ohmic contact and a semiconductor device provided with such ohmic contact
DE2215526A1 (en) Metal contact for semiconductors - with consecutive chromium, chromium/nickel, nickel and gold layers, is junction-free
JPH0463548B2 (en)
JPS5880872A (en) Semicondutor device
US3942244A (en) Semiconductor element
JPH08298267A (en) Semiconductor device and manufacture thereof
US5045497A (en) Method of making a schottky electrode
JPS6016463A (en) Ohmic electrode
JPH0864801A (en) Silicon carbide semiconductor element and its manufacture
JPS61256766A (en) Electrode for compound semiconductor
JPS61183961A (en) Manufacture of electrode
JPH05335348A (en) Semiconductor device
JPH0518251B2 (en)
US11894432B2 (en) Back side contact structure for a semiconductor device and corresponding manufacturing process
JPH03211880A (en) Forming method for schottky junction
JPS61187364A (en) Ohmic electrode
JPS59165460A (en) Semiconductor device and manufacture thereof
JPH01166556A (en) N-type gaas ohmic electrode and formation thereof
JPS62118525A (en) Manufacture of semiconductor device
JPS6194347A (en) Forming method of wiring metal
JPS61203672A (en) Formation of electrode
JPS6267878A (en) Mes field effect transistor
JPS61174671A (en) Schottky junction type semiconductor device and manufacture thereof
JPS63199415A (en) Manufacture of semiconductor element