JPH0554269B2 - - Google Patents

Info

Publication number
JPH0554269B2
JPH0554269B2 JP59055293A JP5529384A JPH0554269B2 JP H0554269 B2 JPH0554269 B2 JP H0554269B2 JP 59055293 A JP59055293 A JP 59055293A JP 5529384 A JP5529384 A JP 5529384A JP H0554269 B2 JPH0554269 B2 JP H0554269B2
Authority
JP
Japan
Prior art keywords
shot
film
semiconductor device
forming
tungsten
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59055293A
Other languages
Japanese (ja)
Other versions
JPS60200575A (en
Inventor
Hajime Matsura
Hiroshi Nakamura
Toshio Nonaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP5529384A priority Critical patent/JPS60200575A/en
Publication of JPS60200575A publication Critical patent/JPS60200575A/en
Publication of JPH0554269B2 publication Critical patent/JPH0554269B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】[Detailed description of the invention]

(技術分野) 本発明はGaAs系シヨツトキダイオードや
GaSa系シヨツトキゲート電界効果トランジスタ
などのシヨツトキ障壁半導体装置及びその製造方
法に関する。 (技術的背景) GaAs系n型半導体の耐熱性シヨツトキ金属と
してはWやWSiなどが知られる。スパツタ法形成
によるWシヨツトキ金属はダイオード特性におけ
るn値が1に近く且つシート抵抗も低いものとし
て知られているが、バリア高さは比較的低い。更
に800℃程度以上の高温アニールによつて前記n
値が極端に増加し、従つてシヨツトキ金属形成後
活性化アニールを必要とする装置では適用し難
い。WSiシヨツトキ金属は例えば1984年応用物理
第53巻第1号34ページで報告されているように、
耐熱性すなわち高温アニールに対する安定性に比
較的優れているが、シート抵抗は高い。その他
TiWやTiWSi等のシヨツトキ金属も知られてい
るが、一般に耐熱性に欠けるかシート抵抗が大き
いという欠点がある。 (発明の目的) この発明の目的は、良好なシヨツトキ特性を有
し且つ耐熱性に優れた、更にはシート抵抗が比較
的低いGaAs系シヨツトキ半導体装置を提供する
ことにある。 (発明の概要) この発明は、n型GaAs系半導体基板に100Å
以下のAl膜を形成しその上に高融点金属を形成
したのち、高温アニールすることにより、シヨツ
トキ障壁を得るようにしたものである。 (実施例) 第1図は本発明の一実施例を説明するためのシ
ヨツトキゲート型GaAsFETの構造断面図であ
り、以下図面に沿つて説明する。 第1図に示すように、半絶縁性のGaAs基板1
にn領域2を選択的に形成し、その上にスパツタ
法により20Å程度厚さのAl膜を披着し、続いて
W膜を1000Å程度厚さ披着した後、選択的に形成
された図示しないイオン阻止能のある金属をマス
クとしてサイドエツチングされるようにAl膜と
W膜とをエツチングしてn領域2上にAl膜3お
よびW膜4を形成する。しかる後、前記マスクに
より選択的にn+領域5を形成して前記マスクを
除去する。 しかる後、基板1の表面に図示しない1200Å程
度厚さのSiO2膜を保護膜としてAs圧雰囲気中で
900℃15分の活性化アニールを行つた後、この
SiO2膜を除去する。このアニールによつてAlが
W膜4中に拡散し、Al膜3はW中にAlが含まれ
た層に変化する。 次にn+領域上にオーミツク電極6a,6b、
SiO2膜7、配線材8a,8bを順次形成するこ
とにより第1図に示すシヨツトキゲート型
GaAsFETを得る。尚、第1図において、W中に
Alが含まれた層3とW膜4とがゲート電極とな
り、オーミツく電極6a,6bがソースおよびド
レイン電極となる。 次にその特性について第2図を用いて説明す
る。 第2図は、本発明によるシヨツトキ半導体装置
のアニール後のシヨツトキ接合部における電流電
圧(I−V)特性を示す図であり、この例では、
シヨツトキ半導体装置の接合部の面積は8×10-5
cm2であり、Al膜厚は20Åであり、W膜厚は1000
Åであり、n層はドーズ量1.8×1012cm-2で60keV
のSiイオン注入で形成したものである。この第2
図から明らかなように、900℃15分間のアニール
後においても、n値は1.02、バリア高さφBは0.83
であり非常に良好なシヨツトキ特性が得られてい
ることがわかり、また、シート抵抗は16μΩcm程
度で比較的小さい。 表は本発明によるAlW金属、及び従来使用さ
れてきた金属のシヨツトキ特性をアニール前とア
ニール後とに分け、n値とバリア高さφBについ
てそれらの値を示したものである。
(Technical field) The present invention relates to GaAs-based shot diodes and
The present invention relates to a shot barrier semiconductor device such as a GaSa-based shot gate field effect transistor and a method for manufacturing the same. (Technical background) W, WSi, and the like are known as heat-resistant shot metals for GaAs-based n-type semiconductors. W shot metal formed by the sputtering method is known to have an n value close to 1 in diode characteristics and a low sheet resistance, but the barrier height is relatively low. Furthermore, the above n
The value increases dramatically and is therefore difficult to apply in devices that require activation annealing after shot metal formation. For example, as reported in Applied Physics Vol. 53, No. 1, p. 34, 1984, WSi shot metal is
Although it has relatively excellent heat resistance, that is, stability against high-temperature annealing, its sheet resistance is high. others
Shock metals such as TiW and TiWSi are also known, but they generally have the disadvantage of lacking heat resistance or having high sheet resistance. (Object of the Invention) An object of the present invention is to provide a GaAs-based shot semiconductor device that has good shot characteristics, excellent heat resistance, and relatively low sheet resistance. (Summary of the Invention) This invention provides an n-type GaAs semiconductor substrate with a thickness of 100 Å.
A shot barrier is obtained by forming the following Al film, forming a high melting point metal on top of it, and then annealing it at a high temperature. (Embodiment) FIG. 1 is a cross-sectional view of the structure of a shot gate type GaAsFET for explaining an embodiment of the present invention, which will be explained below along with the drawings. As shown in Figure 1, a semi-insulating GaAs substrate 1
After selectively forming the n-region 2, an Al film with a thickness of about 20 Å was deposited on it by sputtering, and then a W film with a thickness of about 1000 Å was deposited on it by sputtering. The Al film 3 and the W film 4 are formed on the n region 2 by etching the Al film and the W film so as to perform side etching using a metal having an ion blocking ability as a mask. Thereafter, n + regions 5 are selectively formed using the mask, and the mask is removed. After that, a SiO 2 film (not shown) with a thickness of about 1200 Å was used as a protective film on the surface of the substrate 1 in an As pressure atmosphere.
After activation annealing at 900℃ for 15 minutes, this
Remove the SiO2 film. By this annealing, Al diffuses into the W film 4, and the Al film 3 changes into a layer containing Al in W. Next, ohmic electrodes 6a, 6b are placed on the n + region.
By sequentially forming the SiO 2 film 7 and the wiring materials 8a and 8b, a shot gate type as shown in FIG.
Obtain GaAsFET. In addition, in Figure 1, in W
The layer 3 containing Al and the W film 4 serve as a gate electrode, and the ohmic electrodes 6a and 6b serve as source and drain electrodes. Next, its characteristics will be explained using FIG. 2. FIG. 2 is a diagram showing the current-voltage (I-V) characteristics at the shot junction after annealing of the shot semiconductor device according to the present invention; in this example,
The area of the junction of the Schottky semiconductor device is 8×10 -5
cm 2 , the Al film thickness is 20 Å, and the W film thickness is 1000 Å.
Å, and the n-layer is 60keV at a dose of 1.8×10 12 cm -2
It was formed by Si ion implantation. This second
As is clear from the figure, even after annealing at 900°C for 15 minutes, the n value is 1.02 and the barrier height φ B is 0.83.
It was found that very good shot characteristics were obtained, and the sheet resistance was relatively small at about 16 μΩcm. The table shows the shot characteristics of the AlW metal according to the present invention and conventionally used metals before and after annealing, and shows the values of n value and barrier height φ B.

【表】 尚、*aは本発明者らの実験データであり、*
bは前記文献からの引用による。 この表からわかるように、Alを20Å厚さに形
成し、その上にWを1000Å厚さに形成したものは
他の金属によるシヨツトキ障壁の場合と比べ、ア
ニール前後でn値は1に近く安定でバリア高さ
φBも高く安定であり、他の金属よりも良好なシ
ヨツトキ特性が得られることがわかる。 但し、AlWのシヨツトキ電極におけるAl厚さ
を120Åと厚くした場合、Alの厚さを20Å程度と
した場合に比べn値及びバリア高さφBの値が逆
に劣化してしまいシヨツトキ特性が悪くなる。こ
れは、W膜中にAlが拡散しきらず、Alの薄膜が
残るためである。また、350℃程度のかなり低い
熱処理によつても金属層は部分的に凝縮したりあ
るいは基板面から剥離を生ずる。 以上のことより、形成すべきAl金属の膜厚は
GaAs系基板表面にほぼ均一に形成され、また、
W膜中にAlが拡散しきらずAlの薄膜が残ること
がないように、100Å以下の厚さが有効である。 (発明の効果) この発明は以上説明したように、n型のGaAs
系基板上に選択的に100Å以下の厚さのAl膜、そ
の上に高融点金属膜を順次形成したのち、高温ア
ニールすることによりシヨツトキ障壁を得るもの
である。したがつて、例えば800℃以上のアニー
ル後においてもn値、バリア高さ、シート抵抗等
のシヨツトキ特性が良好なシヨツトキ障壁半導体
装置を得ることができる。
[Table] Note that *a is the experimental data of the present inventors, *
b is a quotation from the above-mentioned document. As can be seen from this table, when Al is formed to a thickness of 20 Å and W is formed to a thickness of 1000 Å on top of it, the n value is stable near 1 before and after annealing, compared to the case of a shot barrier made of other metals. It can be seen that the barrier height φB is also high and stable, and better shot characteristics than other metals can be obtained. However, when the Al thickness in the AlW shot electrode is increased to 120 Å, the n value and the barrier height φ B value are adversely deteriorated compared to when the Al thickness is about 20 Å, resulting in poor shot properties. Become. This is because Al is not completely diffused into the W film and a thin film of Al remains. Further, even if heat treatment is performed at a fairly low temperature of about 350° C., the metal layer may partially condense or peel off from the substrate surface. From the above, the thickness of the Al metal film to be formed is
It is formed almost uniformly on the surface of the GaAs-based substrate, and
A thickness of 100 Å or less is effective to prevent Al from being completely diffused into the W film and leaving a thin Al film. (Effects of the Invention) As explained above, this invention has an n-type GaAs
A shot barrier is obtained by selectively forming an Al film with a thickness of 100 Å or less on a system substrate, and then sequentially forming a high-melting point metal film on top of that, followed by high-temperature annealing. Therefore, it is possible to obtain a shot barrier semiconductor device with good shot characteristics such as n value, barrier height, sheet resistance, etc. even after annealing at, for example, 800° C. or higher.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を説明するための
GaAs FETの構造断面図であり、第2図は本発
明によるシヨツトキ接合部の電流電圧(I−V)
特性例を示す図である。 1……半絶縁性GaAs基板、2……n領域、3
……Al膜(W中にAlが含まれている層)、4……
W膜、5……n+領域、6a,6b……ソース及
びドレイン電極、7……SiO2膜、8a,8b…
…配線材。
FIG. 1 is a diagram for explaining one embodiment of the present invention.
FIG. 2 is a structural cross-sectional view of a GaAs FET, and FIG.
It is a figure showing an example of a characteristic. 1...Semi-insulating GaAs substrate, 2...n region, 3
...Al film (layer containing Al in W), 4...
W film, 5...n + region, 6a, 6b... source and drain electrodes, 7... SiO 2 film, 8a, 8b...
...Wiring material.

Claims (1)

【特許請求の範囲】 1 タングステンをシヨツトキ電極の主たる材料
として用いるシヨツトキ半導体装置の製造方法に
おいて、 半絶縁性のGaAs基板にn型領域を形成する工
程と、 前記GaAs基板の表面上に100Å以下の厚さの
アルミニウム膜を形成する工程と、 前記アルミニウム膜上にタングステン膜を形成
する工程と、 前記アルミニウム膜およびタングステン膜をエ
ツチングして、前記n型領域上に前記アルミニウ
ム膜と前記タングステン膜が積層されたシヨツト
キ電極を形成する工程と、 750℃以上の温度でアニールして前記アルミニ
ウム膜を前記タングステン膜中に拡散させ、前記
シヨツトキ電極の上層をタンクステン層、下層を
タングステンとアルミニウムとの合金層とする工
程と を有することを特徴とするシヨツトキ半導体装置
の製造方法。 2 前記半導体装置がシヨツトキゲート電界効果
トランジスタであることを特徴とする特許請求の
範囲第1項記載のシヨツトキ半導体装置の製造方
法。
[Claims] 1. A method for manufacturing a shot semiconductor device using tungsten as the main material of a shot electrode, comprising: forming an n-type region on a semi-insulating GaAs substrate; forming a tungsten film on the aluminum film; etching the aluminum film and the tungsten film to stack the aluminum film and the tungsten film on the n-type region; a step of forming a shot-type electrode, and annealing at a temperature of 750° C. or higher to diffuse the aluminum film into the tungsten film, forming an upper layer of the shot-type electrode as a tanksten layer and a lower layer as an alloy layer of tungsten and aluminum. 1. A method for manufacturing a short-shot semiconductor device, comprising the steps of: 2. The method of manufacturing a shot-lock semiconductor device according to claim 1, wherein the semiconductor device is a shot-gate field effect transistor.
JP5529384A 1984-03-24 1984-03-24 Schottky semiconductor device and manufacture thereof Granted JPS60200575A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5529384A JPS60200575A (en) 1984-03-24 1984-03-24 Schottky semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5529384A JPS60200575A (en) 1984-03-24 1984-03-24 Schottky semiconductor device and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS60200575A JPS60200575A (en) 1985-10-11
JPH0554269B2 true JPH0554269B2 (en) 1993-08-12

Family

ID=12994527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5529384A Granted JPS60200575A (en) 1984-03-24 1984-03-24 Schottky semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS60200575A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1939832A1 (en) 2006-12-26 2008-07-02 Somfy SAS Safety sensor-transmitter for detecting wind in a home-automation system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2661235B2 (en) * 1989-02-06 1997-10-08 富士通株式会社 Method for manufacturing semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128875A (en) * 1979-03-27 1980-10-06 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55128875A (en) * 1979-03-27 1980-10-06 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1939832A1 (en) 2006-12-26 2008-07-02 Somfy SAS Safety sensor-transmitter for detecting wind in a home-automation system

Also Published As

Publication number Publication date
JPS60200575A (en) 1985-10-11

Similar Documents

Publication Publication Date Title
CA1199430A (en) Method of producing semiconductor device
US4843033A (en) Method for outdiffusion of zinc into III-V substrates using zinc tungsten silicide as dopant source
KR940022708A (en) Low resistance contact structure of the highly integrated semiconductor device and its formation method
US4574298A (en) III-V Compound semiconductor device
JP2893723B2 (en) Method of manufacturing ohmic electrode
US5143856A (en) Method of manufacturing MES FET
JP2664051B2 (en) How to increase the height of the barrier and shotkey barrier
JPH0235462B2 (en)
US4476157A (en) Method for manufacturing schottky barrier diode
JPH0554269B2 (en)
JPS609159A (en) Semiconductor device
JPS6257255A (en) Manufacture of compound semiconductor device
JP3205150B2 (en) Method for manufacturing semiconductor device
JPH0515311B2 (en)
JPS5950214B2 (en) Manufacturing method of semiconductor device
JPH0586853B2 (en)
JP3220624B2 (en) Compound semiconductor device and method of manufacturing the same
Berthoud Aluminum alloying in silicon integrated circuits
JPS61290775A (en) Semiconductor device
JP2777153B2 (en) Semiconductor device and manufacturing method thereof
JP2932305B2 (en) Method for manufacturing semiconductor device
JP2884376B2 (en) Method of forming metal oxide resistor
JPS62203370A (en) Semiconductor device
JPH0810706B2 (en) Method for manufacturing field effect transistor
JPS63246870A (en) Compound semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term