JPS60225474A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60225474A JPS60225474A JP8227384A JP8227384A JPS60225474A JP S60225474 A JPS60225474 A JP S60225474A JP 8227384 A JP8227384 A JP 8227384A JP 8227384 A JP8227384 A JP 8227384A JP S60225474 A JPS60225474 A JP S60225474A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxide film
- melting point
- high melting
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 238000002844 melting Methods 0.000 claims abstract description 16
- 230000008018 melting Effects 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 8
- 229910052785 arsenic Inorganic materials 0.000 abstract description 6
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 239000010408 film Substances 0.000 abstract 5
- 229920001187 thermosetting polymer Polymers 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 206010011878 Deafness Diseases 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、ＭＯ８型半導体装置のゲート電極構造を改
良した半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device having an improved gate electrode structure of an MO8 type semiconductor device.
従来のこの稚の装置を第１図によって説明する。 This conventional device will be explained with reference to FIG.
この図において、１はｐｆｉシリコン基板、２はフィー
ルド酸化膜、３はゲート酸化膜で、埋込みコンタクト用
の孔５を形成している。４はｎ中型不純物の拡散領域で
あり、６はゲート電極となる多結晶シリコン層のパター
ンである。In this figure, 1 is a PFI silicon substrate, 2 is a field oxide film, and 3 is a gate oxide film, forming a hole 5 for a buried contact. 4 is a diffusion region of n medium impurity, and 6 is a pattern of a polycrystalline silicon layer which becomes a gate electrode.
次忙製造方法について説明する。まず、２厘シリコン基
板１にフィールド酸化膜２′１に形成後、熱酸化処理を
施してフィールド酸化膜２で囲まれた島状のｐ型シリコ
ン基板１表面にゲート酸化膜３を形成する。次Ｋ、ゲー
ト酸化膜３の一部に埋込みコンタクト用の孔５を開孔し
、全面に砒素をドープした多結晶シリコン層を堆積し、
これｔバターニングしてゲート酸化１ｊＩａ上にゲート
電極および配線用として多結晶シリコン層６のパターン
を形成する。まＬ、多結晶シリコン層Ｓ）、′！ｒＪパ
ターンおよびフィールド酸化膜２ｖｋ：マスクとしてｎ
屋不純物、例えば砒素ｔゲート酸化膜３′４を通してｐ
Ｈシリコン基板１にイオン注入した後、熱処理を施丁。The next production method will be explained. First, a field oxide film 2'1 is formed on a two-layer silicon substrate 1, and then thermal oxidation treatment is performed to form a gate oxide film 3 on the surface of the island-shaped p-type silicon substrate 1 surrounded by the field oxide film 2. Next, a hole 5 for a buried contact is formed in a part of the gate oxide film 3, and a polycrystalline silicon layer doped with arsenic is deposited on the entire surface.
This is patterned to form a pattern of polycrystalline silicon layer 6 for gate electrodes and wiring on gate oxide 1jIa. MaL, polycrystalline silicon layer S),'! rJ pattern and field oxide film 2vk: n as a mask
impurities such as arsenic through the gate oxide film 3'4.
After ion implantation into the H silicon substrate 1, heat treatment is performed.
その時、多結晶シリコン層６のパターンに対してセルフ
拳アラインでソース、ドレイン領域としてのｎ中盤不純
物の拡散領域４が形成さｎる。At this time, an n middle impurity diffusion region 4 as a source and drain region is formed in self-alignment with respect to the pattern of the polycrystalline silicon layer 6.
これｋより、ＭＯＳデバイスが形成される。From this k, a MOS device is formed.
このようＫ、従来のゲート電極材料には多結晶シリコン
が使われているが、多結晶シリコン配線はリン、ホルン
等の不純物ｔドープしてもその抵抗値が高く、これＫよ
るＲＣ遅蔦（Ｒ：多結晶シリコン配線の抵抗、Ｃ：多結
晶シリコン配線が持つ電気容量）＆言、他の遅延要素に
比べて大きくなるなどの欠点があった。As described above, polycrystalline silicon is used as a conventional gate electrode material, but polycrystalline silicon wiring has a high resistance even when doped with impurities such as phosphorus and horn. (R: resistance of polycrystalline silicon wiring; C: electric capacity of polycrystalline silicon wiring);
この発明は、上記のような従来のものの欠点を除去する
ためになさｎたもので、半導体基板上に形成されたゲー
ト酸化膜に形成さｎるゲート電極を、従来より膜厚の薄
い多結晶シリコン層、高融点金属層、さらｋその上に金
属原子を含む金属シリサイド層を順次形成して３層構造
とすることｋより、素子の高密度化とともに高速動作を
達成し得る半導体装置な提供することを目的としている
。This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and the gate electrode formed on the gate oxide film formed on the semiconductor substrate is made of a polycrystalline film with a thinner film thickness than the conventional one. By sequentially forming a silicon layer, a high-melting point metal layer, and a metal silicide layer containing metal atoms thereon to form a three-layer structure, a semiconductor device is provided that can achieve high-speed operation as well as high-density elements. It is intended to.
以下、この発明の一実施例を図面について説明する。An embodiment of the present invention will be described below with reference to the drawings.
〔発明の実施例〕
第２図はこの発明の一実施例を示す半導体装置の要部断
面図であり、１〜５は第１図と同じものｔ示し、７は前
記ゲート酸化膜３上に形成された多結晶シリクン層、８
は前記多結晶シリコン層７上に形成されりＰｔ やＴＩ
などの高融点金属層、９は高融点金属からなる金属シ
リサイド層である。[Embodiment of the Invention] FIG. 2 is a sectional view of a main part of a semiconductor device showing an embodiment of the present invention, in which 1 to 5 are the same as in FIG. formed polycrystalline silicon layer, 8
is formed on the polycrystalline silicon layer 7 and is made of Pt or TI.
9 is a metal silicide layer made of a high melting point metal.
次忙、この発明のゲート電極構造の製造方法忙ついて説
明する。従来のように−ｐ屋シリコン基板１にフィール
ド酸化膜２を形成後、熱酸化処理を施しフィールド酸化
膜２で囲まれたｐ型シリコン基板１の表面にゲート酸化
１１３を形成し、次に、ゲート酸化膜３の一部に埋込み
コンタクト用の孔Ｓｔ−開孔し、全面に砒素をドープし
た多結晶シリコン層を従来より薄い厚さく約Ｔ）＜、、
堆積し、こｔｔ′ｌｋ：バターニングしてゲート酸化膜
３上にゲート電極および配線用の一部として多結晶シリ
コン層７のパターンを形成する。Next, a method for manufacturing a gate electrode structure according to the present invention will be explained. As in the conventional method, after forming a field oxide film 2 on a p-type silicon substrate 1, a thermal oxidation treatment is performed to form a gate oxide 113 on the surface of the p-type silicon substrate 1 surrounded by the field oxide film 2, and then, A hole St for a buried contact is opened in a part of the gate oxide film 3, and a polycrystalline silicon layer doped with arsenic is formed on the entire surface to a thickness thinner than that of the conventional one.
The polycrystalline silicon layer 7 is deposited and patterned to form a pattern of a polycrystalline silicon layer 7 on the gate oxide film 3 as part of the gate electrode and wiring.
また、多結晶シリコン層７のパターンおよびフィールド
酸化膜２ｔマ゛スクとしてｎ聾不純物、例えば砒素をゲ
ート酸化膜３′Ｉｋ通してｐ型シリコン基板１にイオン
注入した後、熱処理を施す。その結果、多結晶シリコン
層１のパターンに対してセルフ−７ラインでソース、ド
レイン領域としてのｎ生型不純物の拡散領域４が形成さ
ｊる。次ｋ、選択ＣＶＤ法を用いて多結晶シリコン層７
と拡散領域４の８１表面部を高融点金属層（例えばＴｌ
。Further, as a pattern for the polycrystalline silicon layer 7 and a field oxide film 2t mask, an n-deaf impurity such as arsenic is ion-implanted into the p-type silicon substrate 1 through the gate oxide film 3'Ik, and then heat treatment is performed. As a result, n-type impurity diffusion regions 4 as source and drain regions are formed along the self-7 line with respect to the pattern of the polycrystalline silicon layer 1. Next, polycrystalline silicon layer 7 is formed using selective CVD method.
and 81 surface portion of the diffusion region 4 is coated with a high melting point metal layer (for example, Tl
.
ｐｔ等）８で覆う、この後、薄い多結晶シリコン膜を全
面に形成し熱処理する。After that, a thin polycrystalline silicon film is formed on the entire surface and heat treated.
この熱処理により、シリサイド化反応を利用して高融点
金属面と接している部分だけに、高融点金属の金属シリ
サイド層９を形成する。ゲート酸化膜３上は未反応の多
結晶シリコンが残り、反応しない部分の多結晶シリコン
をエツチングにより除去丁ｊば、ソースおよびドレイン
領域とゲートの金属表面部を金属シリサイド層９で被覆
した構造か得らｊる。By this heat treatment, a metal silicide layer 9 of a high melting point metal is formed only in the portion that is in contact with the high melting point metal surface using a silicidation reaction. Unreacted polycrystalline silicon remains on the gate oxide film 3, and the unreacted polycrystalline silicon is removed by etching.Then, the source and drain regions and the metal surface of the gate are covered with a metal silicide layer 9. I can get it.
以上説明しｋように、この発明は、ゲート電極を多結晶
シリコン層、高融点金属層、高融点金属からなる金属シ
リサイド層の３層構造したので、低抵抗でしかもこの方
法によｊば高融点金ｓ’ｉｉｔ微細加工しなくて丁み、
さらＫ、ＡＩの７ｐイ・スパイクの防止忙もなる効果が
ある。As explained above, in this invention, the gate electrode has a three-layer structure of a polycrystalline silicon layer, a high melting point metal layer, and a metal silicide layer made of a high melting point metal. Melting point gold s'iit without fine processing,
It also has the effect of keeping K and AI busy preventing 7p spikes.
第１図は従来のＭＯ８型半導体装置の要部断面図、第２
図はこの発明の一実施例を説明するためのＭＯ８型半導
体装置の要部断面図である。
図中、１はｐ型シリコン基板、２はフィールド酸化膜、
３はゲート酸化膜、４はｎ＋ｍ不純物の拡散領域、５は
埋込みフンタクト用の孔、１は多結晶シリコン層、８は
高融点金属層、９は金属シリサイド層である。
なお、図中の同一符号は同一または相当部分な示す。
代理人 大著増地 （外２名）Figure 1 is a sectional view of the main parts of a conventional MO8 type semiconductor device, Figure 2
The figure is a sectional view of a main part of an MO8 type semiconductor device for explaining one embodiment of the present invention. In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film,
3 is a gate oxide film, 4 is an n+m impurity diffusion region, 5 is a hole for a buried hole, 1 is a polycrystalline silicon layer, 8 is a high melting point metal layer, and 9 is a metal silicide layer. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Daisho Masuji (2 others)
Claims (1)
膜上に多結晶シリコン層を形成し、この多結晶シリコン
層上に高融点金属層と高融点金属からなる金属シリサイ
ド層を順次形成して３層構造のゲート電極としたことを
特徴とする半導体装置。A gate oxide film is formed on a semiconductor substrate, a polycrystalline silicon layer is formed on this gate oxide film, and a high melting point metal layer and a metal silicide layer made of a high melting point metal are sequentially formed on this polycrystalline silicon layer. A semiconductor device characterized by having a gate electrode having a three-layer structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8227384A JPS60225474A (en) | 1984-04-23 | 1984-04-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8227384A JPS60225474A (en) | 1984-04-23 | 1984-04-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60225474A true JPS60225474A (en) | 1985-11-09 |
Family
ID=13769875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8227384A Pending JPS60225474A (en) | 1984-04-23 | 1984-04-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60225474A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5678140A (en) * | 1979-10-25 | 1981-06-26 | Gen Electric | Conductive composite structure and method of forming same |
-
1984
- 1984-04-23 JP JP8227384A patent/JPS60225474A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5678140A (en) * | 1979-10-25 | 1981-06-26 | Gen Electric | Conductive composite structure and method of forming same |
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