JPS6354231B2 - - Google Patents
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- Publication number
- JPS6354231B2 JPS6354231B2 JP8399581A JP8399581A JPS6354231B2 JP S6354231 B2 JPS6354231 B2 JP S6354231B2 JP 8399581 A JP8399581 A JP 8399581A JP 8399581 A JP8399581 A JP 8399581A JP S6354231 B2 JPS6354231 B2 JP S6354231B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas
- electron
- doped
- algaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 54
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 49
- 238000003860 storage Methods 0.000 claims description 35
- 239000012535 impurity Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000010410 layer Substances 0.000 description 137
- 230000037230 mobility Effects 0.000 description 33
- 238000010438 heat treatment Methods 0.000 description 17
- 230000007423 decrease Effects 0.000 description 13
- 230000000694 effects Effects 0.000 description 10
- 239000011651 chromium Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000002474 experimental method Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000000116 mitigating effect Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、更に詳しくは、ノ
ンドープのGaAs層とn型のAlGaAs層とのヘテ
ロ接合に発生する高電子移動度の電子蓄積層を導
電チヤネルとする電界効果型の高電子移動度トラ
ンジスタ(HEMT)の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a field effect that uses an electron storage layer with high electron mobility, which occurs at a heterojunction between a non-doped GaAs layer and an n-type AlGaAs layer, as a conductive channel. Concerning improvements in high electron mobility transistors (HEMTs).
HEMTは電子親和力の相違なる2種の半導体
間のヘテロ接合において、電子親和力の差に基づ
いて電子親和力小の半導体(AlGaAs)層中の電
子が電子親和力大の半導体層(GaAs)層側に移
動して、二次元的電子蓄積層が形成される現象を
利用した半導体装置であつて、本発明者等による
既提案のHEMT構造を第1図に例示する。第1
図において、1はクロム等をドープした半絶縁性
のGaAs基板、2はノンドープのGaAs層、3は
n型のAlGaAs層、4はAlGaAs層3に対し整流
性(シヨツトキ)接触するゲート電極、5,6は
ヘテロ接合界面まで合金化されたAuGeから成る
ソース・ドレイン用オーミツク電極で、7がヘテ
ロ接合に隣接してGaAs層2内に形成された高電
子移動度の電子蓄積層である。このHEMTの大
きな特徴は、電子蓄積層7での電子移動度が不純
物散乱による効果が電子移動度を抑制する主因と
なるような低温、例えば77〓において極めて大き
くなることである。電子蓄積層7は、ノンドープ
のGaAs層2中ではあるが、ヘテロ接合の近傍に
極く薄く、約100Å以内の範囲に発生し、この電
子蓄積層7へ電子を供給するn型不純物を含有す
るAlGaAs層3からは空間的に分離されるため、
そこでの電子移動度は不純物散乱による影響を受
けないことになる。そこでこの不純物散乱効果が
電子移動度の増大を阻むことになるような低温に
おいて特に、極めて大きな電子移動度が実現され
る。この電子移動度の改善は10倍以上に達するこ
とが実験的に確認されている。 HEMT is a heterojunction between two types of semiconductors with different electron affinities, where electrons in a semiconductor layer with a lower electron affinity (AlGaAs) move to the semiconductor layer with a higher electron affinity (GaAs) based on the difference in electron affinity. FIG. 1 shows an example of a HEMT structure, which is a semiconductor device that utilizes the phenomenon of forming a two-dimensional electron storage layer and has been proposed by the present inventors. 1st
In the figure, 1 is a semi-insulating GaAs substrate doped with chromium or the like, 2 is a non-doped GaAs layer, 3 is an n-type AlGaAs layer, 4 is a gate electrode in rectifying contact with the AlGaAs layer 3, 5 , 6 are source/drain ohmic electrodes made of AuGe alloyed up to the heterojunction interface, and 7 is an electron storage layer with high electron mobility formed in the GaAs layer 2 adjacent to the heterojunction. A major feature of this HEMT is that the electron mobility in the electron storage layer 7 becomes extremely large at low temperatures, for example 77°, where the effect of impurity scattering becomes the main cause of suppressing the electron mobility. Although the electron storage layer 7 is in the non-doped GaAs layer 2, it is extremely thin near the heterojunction and contains an n-type impurity that is generated within a range of about 100 Å and supplies electrons to the electron storage layer 7. Because it is spatially separated from the AlGaAs layer 3,
The electron mobility there will not be affected by impurity scattering. Extremely high electron mobilities are then achieved, especially at low temperatures where this impurity scattering effect prevents increases in electron mobility. It has been experimentally confirmed that this improvement in electron mobility reaches more than 10 times.
第1図に示すHEMTは、特表昭55−500196号
に開示されているような超格子構造による多数の
電子蓄積層を導電チヤネルとする装置と比較し
て、単一の電子蓄積層7を導電チヤネルとして利
用しているため良好なFET特性が得られる利点
を有する。特にAlGaAs層3のn型不純物濃度及
び厚み、シヨツトキ・ゲート4のバリア高さ、更
には2つの半導体層間の電子親和力差などのパラ
メータを適切に設定すれば、ヘテロ接合に隣接し
てAlGaAs層3内に形成される空乏層とシヨツト
キ接合により生ずる空乏層が熱平衡状態において
連結し、ゲート4下においてはn型AlGaAs層3
が全ての厚みにわたつて空乏化した状態となし得
る。この状態ではゲート電極4への印加電圧に対
し、電子蓄積層7の電子濃度が高感度に変調さ
れ、また下在のノンドープGaAs層2は高抵抗を
呈することからソース・ドレイン間のインピーダ
ンスは唯一の導電チヤネルである電子蓄積層7に
依存することになり、効果的にソース・ドレイン
間のインピーダンスはゲート入力に対し高感度に
変調されることになつて高いGmが達成されるも
のである。更に上記空乏層の延びをヘテロ接合に
達するよう十分大とすれば、ノーマリオン特性ば
かりかノーマリオフ特性のHEMTをも実現でき
る。このように第1図の構造は、ヘテロ接合界面
の高移動度電子蓄積層を利用した半導体装置の中
でも種々の優れた特徴を有しており、これによつ
て始めて実用的なHEMTが実現されたものであ
る。 The HEMT shown in Fig. 1 uses a single electron storage layer 7, compared to a device that uses a large number of electron storage layers with a superlattice structure as a conductive channel, as disclosed in Japanese Patent Publication No. 55-500196. Since it is used as a conductive channel, it has the advantage of providing good FET characteristics. In particular, if parameters such as the n-type impurity concentration and thickness of the AlGaAs layer 3, the barrier height of the shot gate 4, and the difference in electron affinity between the two semiconductor layers are appropriately set, the AlGaAs layer 3 can be placed adjacent to the heterojunction. The depletion layer formed in the inner layer and the depletion layer generated by the shottock junction are connected in a thermal equilibrium state, and the n-type AlGaAs layer 3 is formed under the gate 4.
can be in a depleted state over the entire thickness. In this state, the electron concentration in the electron storage layer 7 is modulated with high sensitivity with respect to the voltage applied to the gate electrode 4, and the underlying non-doped GaAs layer 2 exhibits high resistance, so the impedance between the source and drain is only Therefore, the impedance between the source and drain is effectively modulated with high sensitivity to the gate input, and a high Gm is achieved. Furthermore, if the extension of the depletion layer is made large enough to reach a heterojunction, a HEMT with not only normally-on characteristics but also normally-off characteristics can be realized. In this way, the structure shown in Figure 1 has various excellent features among semiconductor devices that utilize a high-mobility electron storage layer at the heterojunction interface, and it is through this that a practical HEMT was realized for the first time. It is something that
本発明者は第1図のHEMTに更に種々の検討
を加えたところ、熱処理を経た後には電子蓄積層
での電子移動度低下の傾向が認められ、これは電
子蓄積層部分へ不純物が拡散し、不純物散乱効果
による電子移動度低下を生じているものと考えら
れる。この不純物は主に、電子蓄積層へ電子を供
給するため不可欠なAlGaAs層3中のn型不純
物、例えばシリコン、であることは容易に推察さ
れ、かかる不純物の混入を防止するため、ヘテロ
接合に隣接するAlGaAs層3を厚さ50Å程度にわ
たつてノンドープとしておくことは従来より提案
されている。しかし、このノンドープAlGaAs層
は、所要の電子蓄積層を発生させるためには極く
薄い厚みに制限しなければならず、n型不純物拡
散を完全に抑制することは困難であつて、上記理
由による電子移動度の低下傾向は大勢としては避
けられないと考えられる。 The inventor further conducted various studies on the HEMT shown in Figure 1, and found that after heat treatment, the electron mobility in the electron storage layer tends to decrease, and this is due to the diffusion of impurities into the electron storage layer. , it is thought that the electron mobility decreases due to the impurity scattering effect. It is easy to infer that this impurity is mainly an n-type impurity, such as silicon, in the AlGaAs layer 3, which is essential for supplying electrons to the electron storage layer. It has been proposed in the past to leave the adjacent AlGaAs layer 3 undoped over a thickness of about 50 Å. However, this non-doped AlGaAs layer must be limited to an extremely thin thickness in order to generate the required electron storage layer, and it is difficult to completely suppress n-type impurity diffusion. The tendency for electron mobility to decrease is generally considered to be unavoidable.
一方、本発明者の実験によれば、電子蓄積層部
分にはn型不純物ばかりか、基板1を半絶縁性化
するための深い準位を形成する不純物、例えばク
ロム(Cr)、が微量検知され、これが電子移動度
を一層低下させているとの知見を得た。このCr
はノンドープGaAs層2がほぼ1μm近い厚さを有
していてもヘテロ接合界面までほぼ一様に分布し
ており、第1図の構造では基板1からの不純物の
拡散を抑えることは困難と考えられる。 On the other hand, according to experiments conducted by the present inventor, not only n-type impurities but also trace amounts of impurities that form deep levels to make the substrate 1 semi-insulating, such as chromium (Cr), have been detected in the electron storage layer. We obtained the knowledge that this further reduces the electron mobility. This Cr
Even though the non-doped GaAs layer 2 has a thickness of approximately 1 μm, it is distributed almost uniformly up to the heterojunction interface, and it is considered difficult to suppress the diffusion of impurities from the substrate 1 with the structure shown in Figure 1. It will be done.
従つて本発明は、半絶縁性GaAs基板中の深い
準位を作る不純物が電子蓄積層中へ混入するのを
防止し、もつて高い電子移動度を確保できる新規
なHEMT構造を提供することを目的とするもの
である。 Therefore, the present invention aims to provide a novel HEMT structure that can prevent impurities that create deep levels in a semi-insulating GaAs substrate from entering the electron storage layer and ensure high electron mobility. This is the purpose.
本発明による半導体装置は、半絶縁性GaAs基
板上に、低不純物濃度のGaAs層と、該GaAs層
上にヘテロ接合して設けられたn型のAlGaAs層
とを有する半導体装置であつて、前記基板と前記
GaAs層との間にノンドープの高抵抗AlGaAs層
を設けたことを特徴とするものである。 A semiconductor device according to the present invention is a semiconductor device having a GaAs layer with a low impurity concentration on a semi-insulating GaAs substrate, and an n-type AlGaAs layer provided in a heterojunction on the GaAs layer, board and said
The feature is that a non-doped high resistance AlGaAs layer is provided between the GaAs layer.
即ち、本発明によれば、例えば第1図の構造の
HEMTにおいて、ノンドープGaAs層2と基板1
との間にノンドープの高抵抗AlGaAs層を介在さ
せることにより、GaAs基板1からのCrのような
不純物が熱処理時に拡散して電子蓄積層7に達す
るのを抑制し、もつて電子蓄積層における電子移
動度の低下を防止せんとするものである。このよ
うなノンドープAlGaAs層を薄いノンドープ
GaAs層を一旦基板1上へ形成してからその上に
成長させ、更にGaAs層2をその上に成長させて
第1図の構造と類似のHEMTを作成した場合、
熱処理の後にはこのノンドープAlGaAs層中にお
いて上下のGaAs層よりも高濃度に基板からのCr
のような不純物が含有される傾向が認められ、従
つてこのノンドープAlGaAs層はCrのような不純
物の拡散を阻止するというより、むしろゲツタ作
用を有するものと推察される。いずれにしても、
かかるAlGaAs層の存在により、後述の如く、熱
処理による電子蓄積層中での電子移動度低下の傾
向は顕著に緩和されることが確認されている。 That is, according to the present invention, for example, the structure of FIG.
In HEMT, non-doped GaAs layer 2 and substrate 1
By interposing a non-doped high-resistance AlGaAs layer between the GaAs substrate 1 and the GaAs substrate 1, impurities such as Cr from the GaAs substrate 1 are prevented from diffusing and reaching the electron storage layer 7 during heat treatment, thereby preventing electrons in the electron storage layer This is intended to prevent a decrease in mobility. A thin non-doped AlGaAs layer like this
If a HEMT similar to the structure shown in Fig. 1 is created by first forming a GaAs layer on the substrate 1 and then growing it, and then growing a GaAs layer 2 on it,
After heat treatment, this non-doped AlGaAs layer contains Cr from the substrate at a higher concentration than the upper and lower GaAs layers.
It has been observed that the non-doped AlGaAs layer tends to contain impurities such as Cr, and it is therefore inferred that this non-doped AlGaAs layer has a gettering effect rather than blocking the diffusion of impurities such as Cr. In any case,
As will be described later, it has been confirmed that the presence of such an AlGaAs layer significantly alleviates the tendency for electron mobility to decrease in the electron storage layer due to heat treatment.
以下本発明実施例につき詳細に説明する。第2
図は本発明実施例の電界効果型半導体装置を示す
構造断面図である。同図において、11はCrド
ープ半絶縁性のGaAs基板、12はノンドープの
高抵抗GaAs層、13は同じくノンドープの高抵
抗AlGaAs層、14はノンドープGaAs層、15
はn型のAlGaAs層、16はn型のGaAs層、1
7はTi―Pt―Auの3層構造から成るシヨツト
キ・ゲート電極、18,19はソース・ドレイン
用のAuGeオーミツク電極、20は二酸化シリコ
ン(SiO2)膜であり、21がヘテロ接合界面の
GaAs層14側に形成される電子蓄積層である。 Embodiments of the present invention will be described in detail below. Second
The figure is a structural sectional view showing a field effect semiconductor device according to an embodiment of the present invention. In the figure, 11 is a Cr-doped semi-insulating GaAs substrate, 12 is a non-doped high resistance GaAs layer, 13 is also a non-doped high resistance AlGaAs layer, 14 is a non-doped GaAs layer, 15
is an n-type AlGaAs layer, 16 is an n-type GaAs layer, 1
7 is a shot gate electrode consisting of a three-layer structure of Ti-Pt-Au, 18 and 19 are AuGe ohmic electrodes for source and drain, 20 is a silicon dioxide (SiO 2 ) film, and 21 is a heterojunction interface.
This is an electron storage layer formed on the GaAs layer 14 side.
次に第2図の実施例装置の製造法と素子パラメ
ータとにつき詳細に説明する。 Next, the manufacturing method and device parameters of the embodiment device shown in FIG. 2 will be explained in detail.
先ず、Crドープ半絶縁性GaAs基板1を用意
し、周知の分子線エピタキシヤル成長(MBE)
技術により半導体層12〜16を基板1上へ連続
成長させる。各層厚み及び不純物濃度等のパラメ
ータは次の通りである。ノンドープGaAs層12
及びノンドープAlGaAs層13の厚みは夫々1000
Åであり、AlGaAs層13のAlAs混晶比は0.3、
即ちAl0.3Ga0.7Asの組成とした。ノンドープ
GaAs層14の厚みは6000Åである。n型
AlGaAs層15はドナーとしてシリコンを2×
1018cm-3だけドープしてあり、その厚みは600Å
である。この層15もAl0.3Ga0.7Asの組成を有し
ている。これらAlGaAs層13、及び15が互い
に同一の混晶比を有するようにすると、特に
MBE法による多層成長を行なう場合好都合であ
る。即ち、Alの分子線強度は経時的変動を生じ
易いのに対し、高抵抗層13の成長中にAl分子
線強度をモニタし、層15に必要とされる混晶比
となるよう調整しておけば、続くGaAs層14の
成長中はAl分子線は同じ状態で発生させ続ける
がシヤツタ等の手段で遮蔽しておけばよく、次の
AlGaAs層15の成長に当つてはAl分子線の遮蔽
を解除すれば成長開始直後から所要混晶比で成長
を行なえる。HEMTではこのヘテロ接合の特性
が素子特性に決定的影響を与えるから、AlGaAs
層15の成長開始直後の組成を厳密に制御するこ
とは特に重要である。第2図では明示していない
が、AlGaAs層15はヘテロ接合面から厚さ50〜
60Åにわたつてノンドープとしておくことが、既
述の理由により望ましい。このような精密な不純
物ドーピングは、MBE法においては不純物シリ
コン分子線を遮蔽するシヤツタの開閉により容易
に実現できることが周知である。続いて成長され
るn型GaAs層16は厚さが500Åであり、n型
不純物としてシリコンが2×1018cm-3の濃度にド
ープされており、この層16は特にソース・ドレ
イン電極18,19のオーミツク接触性を改善す
る機能を有する。 First, a Cr-doped semi-insulating GaAs substrate 1 is prepared and subjected to well-known molecular beam epitaxial growth (MBE).
The semiconductor layers 12 to 16 are successively grown on the substrate 1 by the technique. Parameters such as each layer thickness and impurity concentration are as follows. Non-doped GaAs layer 12
and the thickness of the non-doped AlGaAs layer 13 is 1000 mm.
Å, and the AlAs mixed crystal ratio of the AlGaAs layer 13 is 0.3.
That is, the composition was Al 0.3 Ga 0.7 As. non-dope
The thickness of the GaAs layer 14 is 6000 Å. n-type
The AlGaAs layer 15 uses 2x silicon as a donor.
Doped by 10 18 cm -3 with a thickness of 600 Å
It is. This layer 15 also has a composition of Al 0.3 Ga 0.7 As. In particular, when these AlGaAs layers 13 and 15 have the same mixed crystal ratio,
This is convenient when performing multilayer growth using the MBE method. That is, while the molecular beam intensity of Al tends to fluctuate over time, the Al molecular beam intensity is monitored during the growth of the high-resistance layer 13 and adjusted to achieve the mixed crystal ratio required for the layer 15. If this is done, the Al molecular beams will continue to be generated in the same state during the subsequent growth of the GaAs layer 14, but they can be shielded by means such as a shutter.
When growing the AlGaAs layer 15, if the shielding of the Al molecular beam is removed, growth can be performed at the required mixed crystal ratio immediately after the start of growth. In HEMT, the characteristics of this heterojunction have a decisive influence on the device characteristics, so AlGaAs
It is particularly important to tightly control the composition of layer 15 immediately after the growth begins. Although not clearly shown in Figure 2, the AlGaAs layer 15 has a thickness of 50~
It is desirable to leave the layer undoped over 60 Å for the reasons mentioned above. It is well known that such precise impurity doping can be easily achieved in the MBE method by opening and closing a shutter that shields the impurity silicon molecular beam. The subsequently grown n-type GaAs layer 16 has a thickness of 500 Å and is doped with silicon as an n-type impurity at a concentration of 2×10 18 cm -3 . It has the function of improving the ohmic contact properties of 19.
以上の多層半導体層12〜16の連続成長が終
了した後に、表面にSiO2膜20をスパツタリン
グ等の周知の手段にて被着形成する。このSiO2
膜20を、ソース・ドレイン・コンタクト領域上
から選択的に除去し、AuGe合金を蒸着した後、
この合金膜をソース・ドレイン電極18,19の
形状にパターニングしてから、オーミツク接触を
確保するため熱処理を施して合金化を行なう。
AuGe合金単層の代わりに、AuGe―Auの多層電
極構成としてもよい。次にゲート電極を形成すべ
き領域において、SiO2膜20を選択エツチング
して窓開きし、引続きGaAsのエツチングを実施
して、AlGaAs層15が表出した時点でエツチン
グを停止する。ここでTi,Pt,Auを連続蒸着
し、第2図に示す如くエツチング溝内のAlGaAs
層15表出部にこの多層金属膜17が残るように
パターニングして、ゲート電極17を形成し、完
成する。尚、ゲート電極17のパターニングのた
めには、SiO2膜20及びn型GaAs層16の選択
エツチングに使用したフオト・レジスト膜をその
まま残した状態で、ゲート用多層金属の連続蒸着
を実施後、フオト・レジスト層をその上の金属膜
もろとも除去する所謂リフトオフ法を適用しても
よい。 After the above-described continuous growth of the multilayer semiconductor layers 12 to 16 is completed, a SiO 2 film 20 is deposited on the surface by well-known means such as sputtering. This SiO2
After selectively removing the film 20 from above the source/drain contact regions and depositing the AuGe alloy,
This alloy film is patterned into the shape of the source/drain electrodes 18, 19, and then heat treated to form an alloy in order to ensure ohmic contact.
Instead of a single layer of AuGe alloy, a multilayer electrode structure of AuGe-Au may be used. Next, in the region where the gate electrode is to be formed, the SiO 2 film 20 is selectively etched to open a window, and then GaAs is etched, and the etching is stopped when the AlGaAs layer 15 is exposed. Here, Ti, Pt, and Au are continuously deposited, and the AlGaAs in the etching groove is removed as shown in Figure 2.
The multilayer metal film 17 is patterned so as to remain on the exposed portion of the layer 15 to form a gate electrode 17, and the process is completed. In order to pattern the gate electrode 17, the photoresist film used for the selective etching of the SiO 2 film 20 and the n-type GaAs layer 16 is left as is, and after continuous vapor deposition of a multilayer metal for the gate, A so-called lift-off method may be applied to remove the photoresist layer together with the metal film thereon.
かくして製作された第2図の半導体装置は、特
に製造工程中不可欠の種々の熱処理に対して、ノ
ンドープAlGaAs層13を持たない構造の装置に
比較して、電子蓄積層21における電子移動度の
低下に基因する特性劣化が少ないことが確認され
た。尚第2図においては、AuGe合金電極18,
19と下地半導体との合金化領域は示していない
が、電子蓄積層21との導通を図るため、層1
4,15間のヘテロ接合界面に達するまで熱処理
による合金化が施されているものである。 The thus manufactured semiconductor device shown in FIG. 2 has a lower electron mobility in the electron storage layer 21 compared to a device having a structure without the non-doped AlGaAs layer 13, especially during various heat treatments essential during the manufacturing process. It was confirmed that there was little characteristic deterioration due to In addition, in FIG. 2, the AuGe alloy electrode 18,
Although the alloyed region between layer 19 and the underlying semiconductor is not shown, the layer 1
Alloying is performed by heat treatment until the heterojunction interface between 4 and 15 is reached.
本発明によるノンドープAlGaAs層13による
電子移動度低下防止の効果を明確化するための実
験結果につき、次に説明する。この実験は、第2
図に示すHEMTと同様の多層半導体構造を形成
した基板に対し、種々の温度にて熱処理を施した
後に、電子蓄積層における電子移動度を測定し
て、移動度低下傾向を評価したものである。本発
明の効果をより一層顕著にすべく、試料としては
厚さ1000ÅのノンドープGaAs層及び同じく1000
ÅのノンドープAlGaAs層をCrドープ半絶縁性
GaAs基板上に交互に合計4層積層し、その上に
第2図のGaAs層14に相当するノンドープ
GaAs層を厚さ4000Åに設けた点以外は、第2図
と厚さ及び不純物ドープ濃度、及びAlGaAs混晶
比が同一の多層半導体層構成の基板を作成した。
尚、AlGaAs層15に相当する層は下地GaAs層
との界面から60Åの厚さだけノンドープとした。 Experimental results for clarifying the effect of the non-doped AlGaAs layer 13 on preventing a decrease in electron mobility according to the present invention will be described below. This experiment is the second
After heat-treating a substrate with a multilayer semiconductor structure similar to the HEMT shown in the figure at various temperatures, the electron mobility in the electron storage layer was measured to evaluate the tendency for mobility to decrease. . In order to make the effects of the present invention even more remarkable, we used a non-doped GaAs layer with a thickness of 1000 Å and a 1000 Å thick layer as samples.
Cr-doped semi-insulating non-doped AlGaAs layer
A total of four layers are laminated alternately on a GaAs substrate, and a non-doped layer corresponding to the GaAs layer 14 in Fig. 2 is placed on top of the GaAs substrate.
A substrate with a multilayer semiconductor layer structure having the same thickness, impurity doping concentration, and AlGaAs mixed crystal ratio as in FIG. 2 was prepared, except that the GaAs layer was provided with a thickness of 4000 Å.
Note that the layer corresponding to the AlGaAs layer 15 was undoped by a thickness of 60 Å from the interface with the underlying GaAs layer.
比較例の試料は、第2図における層14に相当
するノンドープGaAs層を厚さ約8000Åとして半
絶縁性GaAs基板上に直接成長させた点以外は上
記試料と全く同一構成とした。 The comparative sample had exactly the same structure as the sample described above, except that a non-doped GaAs layer corresponding to layer 14 in FIG. 2 was grown directly on a semi-insulating GaAs substrate to a thickness of about 8000 Å.
MBE成長法による多層連続成長にて上述の各
試料を作成した後に、表面にスパツタリングによ
るSiO2膜を4000〜5000Åの厚さに形成してから、
H2中で15分間のアニールを各試料に対して施し
た。アニール後の各試料に対し、n型AlGaAs層
との界面においてノンドープGaAs層側に発生し
ている電子蓄積層での電子移動度μと、そこでの
電子面濃度Nsとを測定した。この測定結果を第
3図に示す。同図にて横軸はアニール温度であ
り、as―grは成長したまま、つまりアニールなし
の状態を示しており、縦軸は移動度μと電子面濃
度Nsを示している。尚、測定は各試料を77〓に
冷却した状態で行なつている。 After creating each of the above-mentioned samples by continuous multilayer growth using the MBE growth method, a SiO 2 film with a thickness of 4000 to 5000 Å was formed on the surface by sputtering.
A 15 minute anneal in H 2 was applied to each sample. For each sample after annealing, the electron mobility μ in the electron storage layer generated on the non-doped GaAs layer side at the interface with the n-type AlGaAs layer and the electron surface concentration Ns therein were measured. The measurement results are shown in FIG. In the figure, the horizontal axis is the annealing temperature, as-gr shows the state as grown, that is, without annealing, and the vertical axis shows the mobility μ and the electron surface concentration Ns. The measurements were conducted with each sample cooled to 77°C.
第3図において、本発明を適用した試料は白点
で、比較例は黒点で測定結果を示してある。この
グラフから明らかなように、熱処理時の温度が高
い程、電子蓄積層における電子面濃度Nsは増大
し、同時に電子移動度μは低下する。このことか
ら、熱処理に伴つてn型AlGaAs層から電子蓄積
層部分ヘシリコンが拡散していることが推察され
る。一方、本発明試料と比較例とを比較してみる
と、熱処理なしのときには両試料間で電子移動度
μに殆んど差異がないのに対し、700℃の熱処理
を経た後には、比較例でのμは54000(cm2/V・
sec)であるのに対し、本発明試料では62000
(cm2/V・sec)と明瞭な差を生じ、730℃の熱処
理後は前者で19000(cm2/V・sec)に対し後者で
27000(cm2/V・sec)と顕著な相違を生じている。
このことから、本発明によつて設けたノンドープ
AlGaAs層は、半絶縁性GaAs基板中の深い準位
を作る不純物が電子蓄積層中へ這い上るのを抑制
する効果を有し、それにより熱処理に伴う移動度
の低下を緩和する優れた効果を奏するものと考え
られる。 In FIG. 3, the measurement results are shown by white dots for the sample to which the present invention is applied, and by black dots for the comparative example. As is clear from this graph, as the temperature during heat treatment increases, the electron surface concentration Ns in the electron storage layer increases, and at the same time, the electron mobility μ decreases. From this, it is inferred that silicon diffuses from the n-type AlGaAs layer to the electron storage layer portion as a result of heat treatment. On the other hand, when comparing the inventive sample and the comparative example, it is found that there is almost no difference in electron mobility μ between the two samples without heat treatment, but after heat treatment at 700°C, the comparative example μ is 54000 (cm 2 /V・
sec), whereas in the sample of the present invention it was 62000
(cm 2 /V・sec), and after heat treatment at 730°C, the former had a value of 19000 (cm 2 /V・sec), while the latter had a
27000 (cm 2 /V·sec), which is a remarkable difference.
From this, it can be seen that the non-doped
The AlGaAs layer has the effect of suppressing impurities that create deep levels in the semi-insulating GaAs substrate from creeping up into the electron storage layer, and thereby has an excellent effect of mitigating the decrease in mobility caused by heat treatment. It is thought that it is played.
以上の実験から、本発明による半導体装置
(HEMT)は、特にその製造工程中の熱処理によ
つて本来高電子移動度であるべき電子蓄積層での
電子移動度が低下する傾向が抑えられ、高速動作
特性を確保できることが判る。そして、第2図の
説明では言及していないが、HEMTの実用化を
更に進める場合、例えばオーミツク・コンタクト
性の改善やFETのピンチ・オフ電圧(ゲート闘
値電圧)の調整等のため、電子蓄積層へは影響し
ない程度に浅く不純物のイオン注入を行なう工程
は極めて有用であり、かかるイオン注入技術の適
用により集積回路化も容易になるなど、イオン注
入技術を駆使する必要があり、その場合に本発明
は益々有用なものである。即ち、イオン注入を行
なえば、注入不純物の活性化のためのアニールが
不可欠であり、その下限温度がGaAs或いは
AlGaAsの場合ほぼ700℃であるから、他の製造
工程の低温化を何如に工夫しても、電子移動度の
顕著な低下は避けられない。700℃以上の熱処理
が製造工程中に含まれる場合の大幅な電子移動度
の低下は、本発明を適用することにより、著しく
緩和されることが第3図より明らかであろう。 From the above experiments, it was found that the semiconductor device (HEMT) according to the present invention suppresses the tendency for the electron mobility in the electron storage layer, which should originally have high electron mobility, to decrease, especially due to heat treatment during the manufacturing process, and allows high speed operation. It can be seen that the operating characteristics can be secured. Although not mentioned in the explanation of Fig. 2, if the practical application of HEMT is to be further advanced, electronic The process of shallowly implanting impurity ions without affecting the storage layer is extremely useful, and the application of such ion implantation technology facilitates the integration of circuits, so it is necessary to make full use of ion implantation technology. The present invention is increasingly useful. In other words, if ion implantation is performed, annealing is essential to activate the implanted impurities, and the lower limit temperature is
In the case of AlGaAs, the temperature is approximately 700°C, so no matter how much effort is made to lower the temperature in other manufacturing processes, a significant decrease in electron mobility cannot be avoided. It is clear from FIG. 3 that the significant decrease in electron mobility that occurs when heat treatment at 700° C. or higher is included in the manufacturing process can be significantly alleviated by applying the present invention.
以上のように、本発明は低不純物濃度のGaAs
層とn型のAlGaAs層とのヘテロ接合において発
生する高移動度電子蓄積層を導電チヤネルとして
利用する半導体装置(HEMT)において、半絶
縁性基板からの深い準位を形成する不純物が這い
上るのを防止すべく、少なくとも1層のノンドー
プAlGaAs層を介在させるものであり、これによ
つて加熱工程に起因する電子移動度の低下を緩和
し、もつて良好な高速動作特性を確保するもので
ある。 As described above, the present invention is based on GaAs with low impurity concentration.
In a semiconductor device (HEMT) that uses a high-mobility electron storage layer generated at a heterojunction between an n-type AlGaAs layer and an n-type AlGaAs layer as a conductive channel, impurities that form a deep level from a semi-insulating substrate creep up. In order to prevent this, at least one non-doped AlGaAs layer is interposed, thereby mitigating the decrease in electron mobility caused by the heating process and ensuring good high-speed operation characteristics. .
尚、通常のn型GaAs層を導電チヤネルとする
シヨツトキ・ゲート型FETにおいては、高抵抗
AlGaAs層をバツフア層として半絶縁性基板との
間に介在させることは、例えば特開昭54−12261
号公報にも開示されているが、このような公知の
バツフア層とは上述の本発明によるノンドープ
AlGaAs層は全く別の機能、作用効果を奏するこ
とは以上の説明から明白であろう。また、上記実
施例では、電子蓄積層を形成すべきGaAs層を全
てノンドープとしたが、HEMTの動作原理から
考えてこの層の不純物濃度は電子供給用のn型
AlGaAs層のドナー濃度と比べて1桁以上小さい
ような低不純物濃度であれば、電子蓄積層での電
子移動度改善の効果は生じて来るのであり、本発
明はこのような不純物濃度関係を有するHEMT
にも及ぶものである。 In addition, in a shot gate type FET that uses a normal n-type GaAs layer as a conductive channel, it has a high resistance.
The interposition of an AlGaAs layer as a buffer layer between a semi-insulating substrate is disclosed in, for example, Japanese Patent Laid-Open No. 54-12261.
As disclosed in the above-mentioned publication, such a known buffer layer is the non-doped buffer layer according to the present invention described above.
It is clear from the above explanation that the AlGaAs layer has completely different functions and effects. In addition, in the above example, the GaAs layer that forms the electron storage layer is all non-doped, but considering the operating principle of HEMT, the impurity concentration of this layer is n-type for electron supply.
If the impurity concentration is low, which is one order of magnitude lower than the donor concentration of the AlGaAs layer, the effect of improving electron mobility in the electron storage layer will occur, and the present invention has such an impurity concentration relationship. HEMT
It also extends to
第1図は従来の高電子移動度トランジスタ
(HEMT)の構造断面図、第2図は本発明実施例
の半導体装置の構造断面図、第3図は本発明の効
果を表わすための実験効果を示すグラフであつ
て、熱処理温度とその熱処理後の電子蓄積層にお
ける電子移動度及び電子面濃度との関係を示す。
11…半絶縁性GaAs基板、12,14…ノン
ドープGaAs層、13…ノンドープAlGaAs層、
15…n型AlGaAs層、16…n型GaAs層、1
7…ゲート用多層電極、18,19…ソース・ド
レイン電極、21…電子蓄積層。
FIG. 1 is a cross-sectional view of the structure of a conventional high electron mobility transistor (HEMT), FIG. 2 is a cross-sectional view of the structure of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a graph showing the relationship between the heat treatment temperature and the electron mobility and electron surface concentration in the electron storage layer after the heat treatment. 11... Semi-insulating GaAs substrate, 12, 14... Non-doped GaAs layer, 13... Non-doped AlGaAs layer,
15...n-type AlGaAs layer, 16...n-type GaAs layer, 1
7... Multilayer electrode for gate, 18, 19... Source/drain electrode, 21... Electron storage layer.
Claims (1)
プのGaAs層と、該GaAs層上にヘテロ接合を形
成して設けられn型の不純物を含有するAlGaAs
層とを有し、該ヘテロ接合界面に沿つて前記
GaAs層に発生する高電子移動度の電子蓄積層を
導電チヤネルとする半導体装置であつて、前記基
板と前記GaAs層との間で、且つ前記ヘテロ接合
界面の前記電子蓄積層からは該GaAs層を介して
離間した位置に実質的にノンドープのAlGaAs層
を介在させたことを特徴とする半導体装置。1 On a semi-insulating GaAs substrate, a substantially non-doped GaAs layer and an AlGaAs layer containing an n-type impurity are provided by forming a heterojunction on the GaAs layer.
a layer along the heterojunction interface;
A semiconductor device in which an electron storage layer with high electron mobility generated in a GaAs layer serves as a conductive channel, the GaAs layer being connected between the substrate and the GaAs layer and from the electron storage layer at the heterojunction interface. 1. A semiconductor device characterized in that a substantially non-doped AlGaAs layer is interposed at a position spaced apart from each other.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8399581A JPS57198661A (en) | 1981-06-01 | 1981-06-01 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8399581A JPS57198661A (en) | 1981-06-01 | 1981-06-01 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57198661A JPS57198661A (en) | 1982-12-06 |
JPS6354231B2 true JPS6354231B2 (en) | 1988-10-27 |
Family
ID=13818109
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8399581A Granted JPS57198661A (en) | 1981-06-01 | 1981-06-01 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57198661A (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59123271A (en) * | 1982-12-28 | 1984-07-17 | Fujitsu Ltd | Manufacture of compound semiconductor device |
JPS6149476A (en) * | 1984-08-17 | 1986-03-11 | Sony Corp | Field-effect transistor |
KR900001394B1 (en) * | 1985-04-05 | 1990-03-09 | Fujitsu Ltd | Super high frequency intergrated circuit device |
JPS61253869A (en) * | 1985-05-02 | 1986-11-11 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
JPH01143271A (en) * | 1987-11-27 | 1989-06-05 | Matsushita Electric Ind Co Ltd | Manufacture of hetero junction type field-effect transistor |
JP2655490B2 (en) * | 1994-10-28 | 1997-09-17 | 日本電気株式会社 | Method for manufacturing semiconductor device |
-
1981
- 1981-06-01 JP JP8399581A patent/JPS57198661A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS57198661A (en) | 1982-12-06 |
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