JPS6149476A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To inhibit a short-channel effect by forming a barrier to carriers passing through a channel by a hetero-junction oppositely shaped to the channel. CONSTITUTION:An additional semiconductor layer 12, a first semiconductor layer 14 forming a channel 13 by a two demensional electron gas layer, and a second semiconductor layer 15, an energy gap thereof is larger than the layer 14 and which shapes a hetero-junction 16 between the layer 14 and itself, are grown on a substrate 11 in succession, thus constituting a semiconductor base body 18. A Schottky gate metal 17 shaping a Schottky junction 16 on the interface between the layer 15 and itself is applied onto the layer 15. Source and drain electrodes 9 and 20 are formed on both sides of the metal 17. According to the constitution, barriers by the hetero-junction are formed while facing the channel, thus confining carriers into the channel, then inhibiting a direct proceeding toward a drain from a source of carriers by a short channel effect.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor (FET), and particularly to a FET suitable for application to an FET made of a compound semiconductor.

[Prior art]

In an insulated gate field effect transistor (Mis-PET), a problem arises from a current caused by the so-called Shaw 1-channel effect, that is, a current caused by carriers flowing directly from the source to the drain without passing through the channel.

On the other hand, in FET "ζ", secondary electron gas channel type FET (TEGNET), or JP-A-57-1
High electron mobility F E disclosed in Publication No. 76773
T (HEMT) has been proposed. These, TEG
Since NET and IIEMT are based on substantially the same principle, they will be hereinafter referred to as IBMT and will be explained.

For example, in the n-AlGaAs/GaAs heterojunction,
AlGaAs is depleted, and a two-dimensional layer due to electron accumulation, so-called two-dimensional electron gas (TEG), is formed on the GaAs side, and a high carrier concentration is obtained even though impurity doping is not performed on the GaAs side. Therefore, high electron mobility can be obtained. That is, when increasing the amount of donor doping to increase the carrier concentration, the increase in the amount of donors causes an increase in the number of ionization centers, resulting in a decrease in mobility t. is avoided and high electron mobility is obtained. This is called modulation doping, and using this phenomenon, n-Al
A HEMT is a device in which a Schottky metal electrode is provided on GaAs, and the carrier density on the GaAs side is controlled by the voltage applied to the metal electrode. That is,
As shown in Fig. 4, this HEMT also has a Schottky gate metal (11/n-8 IGaAs(2) (donor concentration N21 dielectric constant ε2. thickness d2 e)/no impurity doped). Undoped 81GaAs (
8) A structure of (thickness e)/undoped GaAs (31 (permittivity ε1) is provided on, for example, a GaAs substrate (4). (5) is a structure of metal +11 and n-AI GaAs (
(6) breaks the heterojunction formed between n-^IGaAs (2) and GaAs (3).

The undoped ^IGaAsJi (81) is provided here to separate the channel and the donor ionized in n-AlGaAs to improve electron mobility.

Figure 5 shows the Schottky junction (5) of this HEMT,
The energy band structure in the vicinity of the heterojunction (6) is broken, and in this case, L is confined in the Peter field in the direction perpendicular to this plane.
Second-order electronic force 1. ．． ．． Keya, e/l/ (7
1 Ka 4 formation, wow.

This channel (7) has high electron mobility as described above, so the HEMT with this configuration is a high-speed FET.
It has come into the limelight as a

However, even in such a HEMT, the short channel effect poses a problem.

Conventionally, general MIS-FE that does not rely on a two-dimensional electron gas layer
In order to suppress the short channel effect in T, a semiconductor region of a conductivity type different from the conductivity type of the channel, for example, a p-type semiconductor region in the case of an n-channel FET, is placed in the semiconductor gas opposite to the channel. It is configured by providing . This semiconductor region is formed by deep ion implantation of p-type impurity ions into the semiconductor substrate or by epitaxial growth.

[Problem that the invention seeks to solve]

As described above, when providing a means for suppressing the short channel effect in an FET, a region doped with impurities is provided, but providing this region is not preferable. That is, when this region is formed by ion implantation, the tedious work of ion implantation increases, which reduces mass productivity. Further, when this region is formed by epitaxial growth, there is a problem that the impurity remains in the epitaxial growth apparatus and affects the characteristics of the subsequent epitaxial growth layer.

The present invention makes it possible to suppress short channel effects without causing such inconveniences, and is particularly applicable to compound semiconductor FETs, such as Schottky gate FETs (MESPETs), or two-dimensional electron FETs. IEM (e.g. as mentioned above) with gas channels
This is useful when applied to T.

Means for Solving Problem C] The present invention provides a semiconductor layer in which a channel, for example, the aforementioned two-dimensional electron gas channel, is formed, on the side opposite to the side on which the gate electrode for controlling this channel is arranged. Specifically, an additional semiconductor layer having a larger energy gap than the semiconductor layer in which the channel is formed is provided on the deep side of the semiconductor substrate to form a heterojunction between both semiconductor layers.

[Effect]

As described above, in the present invention, a barrier to carriers passing through the channel is formed by a heterojunction provided opposite to the channel, thereby confining the carriers in the channel. flow directly from the source to the drain through the semiconductor body.

〔Example〕

The case where the present invention is applied to FIEMT will be explained with reference to FIG. In this example, semi-insulating GaA
A substrate (11) made of s single crystal is provided, on which an additional semiconductor layer (12), a first semiconductor layer (14) forming a channel (13) by a two-dimensional electron gas layer, and this first semiconductor layer (14) are provided. A second semiconductor layer (15) having a larger energy gap than the semiconductor layer (14) and forming a heterojunction (16) therebetween is successively epitaxially grown to form a semiconductor substrate (18). . These semiconductor layers (12)
(14) and (15) are, for example, MOCVD (Me
tal Organic Chemical νapor
Deposition method, or M B E (Mo
They can be formed sequentially and continuously by a regular beam epitaxy method.

Further, on the second semiconductor layer (15), a Schottky gate metal (17) such as a Ti/pt/^U metal layer is deposited to form a Schottky junction (16) at the interface therewith. Then, on both sides of this gate metal (17), for example, Au-Ge/Au is applied so as to reach the additional conductor layer (12).
Source and drain electrodes (19) formed by alloying metal layers
) and (20) are formed.

The semiconductor layer (14) is made of, for example, a GaAs layer, and is a semiconductor! (15) is made of, for example, n-type AlGaAs, and the additional semiconductor 1 (12) is made of, for example, ^lGaAs, which has a larger energy gap than the semiconductor 1iiJ (14).

Then, a carrier-confining heterojunction (21) is formed between the semiconductor layer (12) and the additional semiconductor layer (14).

In the example of FIG. 1, an undoped layer is not interposed between the semiconductor layers (14) and (15), but as explained in FIG. It is also possible to provide undoped e.g. ^1GaAJf which separates the ionized donors from the channel (13).

FIG. 2 shows an energy band model of the IIEMT having the configuration shown in FIG. 1. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals. As is clear from this, a barrier is formed by the heterojunction (21) opposite the channel (13), thereby confining carriers, in this case electrons, within the channel (13).

As mentioned above, a barrier is formed by the heterojunction (21) facing the channel (13), but the position of the heterojunction (2) in this case, that is, the thickness of the additional semiconductor layer (14) is , the thickness of the two-dimensional electron gas layer, that is, the thickness of the channel (13), is several tens of meters high, so it is larger than this, and the barrier is formed as close as possible to this channel (13). It is good if there are only about 1 person.

In the above example, the present invention is applied to a HEMT, but other FETs, such as a double heterojunction structure (which similarly has a two-dimensional electron gas channel type FET configuration but does not adopt a Schottky gate type configuration) From F Dll
-MIS-PUT). This D
The I-MIS-FET will be explained, but in order to make it easier to understand, please refer to FIG.
Consider T.

In HEMT, the difference QV in each potential between the Jittky gate metal side and the GaAs side of n-8lGaAs
2 is related to the electric field Ei2 on the AlGaAs side of the heterojunction -qd2Ei2 and the width of n-AlGaAs (d2
−e) is expressed as the sum of 2ε2 (d2−c)2. That is, V2
= d2[ii2+VP2...(11
Also, in Fig. 5, ζ, v2+ΔEc-φM −VG +Ep −・[31
(From Equations 11 and (3)...(According to Gauss's theorem, the left side of Equation (3) is equal to the charge density existing on the GaAs side of the heterojunction. Because HEMT uses undoped GaAs, , there is no space charge due to ionized donors or acceptors.Therefore, this charge density is only the contribution of the carrier density of the channel.In other words, if ns is the sheet carrier density, then qns = t2Ei2= -(VG -Voff
-Ep)...(5).

Here, Voffmiφgate−ΔEc−■P2 ・・・(
6) In this equation (4), EP2 is usually a small value of 0.1 V or less, so it will be ignored. Also (4
), where 82/d2 is the capacity of AlGaAs[if
Since it is c+, qnS! II:C+ (Ve Voff)
(71, which is a well-known formula for the old 5-FET. Here, Voff is the threshold voltage 11 v th
When looking at this vth from equation (6), there are two terms: (φi−ΔEc) and VF6. Here, (φ□-ΔEc) is the difference between the barrier height of the Schottky junction and the barrier height of the heterojunction, and this is an amount that depends on the combination of each material (M-1-3), As mentioned above, vP2 is the potential difference carried by the ionized donors, ie, the space charges, in AlGaAs.

Furthermore, to be more specific about the threshold voltage vth of this HEMT, it is now ^10.3 Ga as an nlGaAs layer.
o, w A s, ΔEc: 0.32V φMγ1. i3V ε2 character 11.560, φ■-ΔECn0.8■, so if AlG
Since aAs is -0, it becomes a normally-off FET with a vth bowl of 0.8 . Therefore, in this HEMT, Al
By doping GaAs with donor impurities and giving a finite value to VF6, vth 0. Alternatively, Vth<0 (normally on) will be obtained. -However, this H
In EMT, φH≠ΔEC, for example, φ
Since i-ΔEc is 0°8■, v th< o
In order to obtain a normally-on FET of n
-The intermediate amount of AlGaAs is relatively thick. However, when forming a heterointerface using n-ΔlGaAs doped with impurities at a relatively high concentration, for example, during heating during heat treatment during the manufacturing process, n - Redistribution of donors in AlGaAs occurs, which leads to instability such as deterioration of FET characteristics, especially electron mobility of two-dimensional electron gas.

In comparison, the DH-Mis-FET configuration has v th
) There is a large degree of freedom in selecting values, and for example, vth<o can be easily set. Figure 3 shows this D)l
- In the case of the old 5-FET configuration, in FIG. 3, parts corresponding to those in FIG. 1 are given the same reference numerals, and repeated explanation will be omitted. That is, in this DH-MIS-FET, the Schottky junction (16) in FIG. 1 is replaced by a heterojunction (26) (hereinafter referred to as heterojunction (16)).
is called a first heterojunction, and the third semiconductor layer (26) forms a second heterojunction.
7), and this third semiconductor layer (27) itself is used as a gate electrode, or a gate electrode (28) is ohmically deposited on this semiconductor layer (27).

Also in this case, an additional semiconductor layer (27) having a larger energy gap than the first semiconductor layer (14) is provided in contact with the first semiconductor layer (14).

And here, (
14), (15) and (27) each have respective conduction band bottom levels Ect+ EC2 and EC
3 is such that Ecz2Ec3<EC2, that is, generally each semiconductor layer (14), (1,5) and (
27), each energy gap or forbidden band width is expressed as Eg1. When Egt and Eg3, Egi YakuEg
3<Egt, and the required barriers ΔECI and Δ are set between the second and first semiconductor layers and between the second and third semiconductor layers, respectively.
This constitutes a DI-Mis-FET having a double heterostructure gate portion in which first and second heterojunctions (16) and 26) having ECM are formed. . DH-MIS-Fl with this configuration! T is the first semiconductor layer (14) which is depleted on the second semiconductor layer (15) side during operation and whose first heterojunction (16) has a low impurity concentration.
A channel (13) with a two-dimensional electron gas layer is likewise constructed on the side. Now, for example, the first semiconductor layer (13) is
The third
The semiconductor layer (27) is, for example, the first semiconductor layer (14)
The second semiconductor rft is made of GaAs, which is the same material as
(15) H $ 1 and Him 3 (D semiconductor layer (1
4) The energy gap is larger than that of Egt = Eg3<
Let us consider the case where Egt is used and the second and third semiconductors 1tj (15) and (27) are each doped with a donor impurity.

In this case, the first and third semiconductors on both sides sandwiching the second semiconductor layer (15)! Since (14) and (27) are made of the same material, compound semiconductor GaAs, the height of the barrier of both the first and second heterojunctions ΔECI
and ΔEcI are almost the same.

Even in the DH-old 5-PET with such a configuration,
A channel (13) formed by a two-dimensional electron gas layer in an undoped, i.e., low impurity concentration first semiconductor layer (14)
Therefore, high electron mobility can be obtained and a commercial speed FET can be obtained.

Then, ζ, the threshold voltage V th (Voff ) in this 0-old MIS-FET is expressed as ΔE
When CI and ΔEcn, vth-ΔECM-ΔEar-VP2 = (6
'), and since ΔEcm and ΔEar are here, vth is almost determined by VF6. Immediately, (2)
As explained in Eq., the second semiconductor I'! Since it is determined by the donor concentration N2 in (15), its thickness d2 e), and the dielectric constant ε2, the donor concentration N2
Setting of VF6 by selecting 2, therefore vth
Therefore, it is possible to easily obtain v th < o.

In addition, in the above-mentioned DI (-MIS-FET), the first and third
This is a case where the semiconductor layers (27) and (14) are made of the same material, but Egx < Eg3 < Eg
2 and ΔEIJ<ΔEcI, similarly (6
'), we can obtain v th< o.

On each side mentioned above, the FET has a channel formed by a two-dimensional electron gas layer, but the channel is formed by the compound semiconductor layer itself such as GaAs, and the channel is formed by the depletion layer from the Schottky gate junction formed therein. The present invention can also be applied to nine MES-FETs etc. by controlling the thickness of the MES-FET.

〔Effect of the invention〕

As described above, according to the present invention, carriers are confined by a heterojunction corresponding to the channel portion, so that it is possible to suppress carriers from directly heading from the source to the drain due to the short channel effect.

Since this carrier confinement is performed by a heterojunction instead of a PN junction as in the conventional method, the confinement can be achieved reliably and the inconvenience caused by doping with impurities mentioned at the beginning can be avoided. ,
In particular, MOCVII, such as FET made of compound semiconductors,
When forming by MBE method etc., this additional semiconductor layer can be formed as a series of steps in MOCVD of other semiconductor layers, MBE method etc., so the workability is improved (41
It is also possible to avoid causing a 4-code.

[Brief explanation of drawings]

Fig. 1 is an enlarged cross-sectional view of an example of a field effect transistor according to the present invention, Fig. 52 is an energy band model diagram thereof, and Fig. 3) 3'7+ is another example of a field effect transistor according to the present invention. Route expansion 11 “Facing 1, 4th
Nu1 is an enlarged cross-sectional view of a conventional field effect transistor, and Figure 5 is an energy band model diagram thereof. (11)...root, (12)...additional semiconductor layer, (13)...channel, (14)...first
semiconductor layer, (15)... second semiconductor layer, (18
)...Semiconductor base, (27)...Third semiconductor layer. Same Hidemori Matsukuma 61.54, 1 qH;', 4.1. )i Figure 5

Claims (1)

[Claims] An additional semiconductor layer, which has a larger energy gap than the semiconductor layer in which the channel is formed, is opposite to the semiconductor layer in which the channel is formed, and is in contact with the side opposite to the side on which the gate electrode controlling the channel is arranged. A field-effect transistor comprising: