JPS6356711B2 - - Google Patents
Info
- Publication number
- JPS6356711B2 JPS6356711B2 JP14999081A JP14999081A JPS6356711B2 JP S6356711 B2 JPS6356711 B2 JP S6356711B2 JP 14999081 A JP14999081 A JP 14999081A JP 14999081 A JP14999081 A JP 14999081A JP S6356711 B2 JPS6356711 B2 JP S6356711B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gallium arsenide
- source
- forming
- electron
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 claims description 39
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 20
- 239000012535 impurity Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 19
- 239000013078 crystal Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 230000007547 defect Effects 0.000 claims description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 239000010931 gold Substances 0.000 description 17
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 12
- 229910052737 gold Inorganic materials 0.000 description 12
- 238000003860 storage Methods 0.000 description 7
- 230000005533 two-dimensional electron gas Effects 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関する。詳し
くは、本特許出願の出願人のなした特許出願（特
願昭55−82035号）に係る高電子移動度トランジ
スタの製造方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device. Specifically, the present invention relates to an improvement in a method for manufacturing a high electron mobility transistor, which is related to a patent application filed by the applicant of the present patent application (Japanese Patent Application No. 82035/1982).
高電子移動度トランジスタとは電子親和力の相
異なる２種の半導体を接合することにより形成さ
れる一つのヘテロ接合面の近傍に発生する電子蓄
積層（二次元電子ガス）の電子濃度を制御電極に
印加される電圧によつて制御して、制御電極を挾
んで設けられた１対の出力電極間に前記の電子蓄
積層（二次元電子ガス）によつて形成される導電
路のインピーダンスを制御する能動的半導体装置
をいう。 A high electron mobility transistor uses the electron concentration of an electron storage layer (two-dimensional electron gas) generated near a single heterojunction surface formed by joining two types of semiconductors with different electron affinities as a control electrode. The impedance of the conductive path formed by the electron storage layer (two-dimensional electron gas) between a pair of output electrodes provided with the control electrode in between is controlled by the applied voltage. An active semiconductor device.
高電子移動度トランジスタの大きな特徴は、上
記の電子蓄積層（二次元電子ガス）の電子移動度
が、不純物散乱による効果が電子移動度を抑制す
る主因となるような低い温度例えば77〓におい
て、極めて大きくなることである。上記の電子蓄
積層（二次元電子ガス）は、不純物ドープを必要
としない電子親和力の大きな半導体層（チヤンネ
ル層）中ではあるが、ヘテロ接合のごく近傍に、
ごく薄く、約100Å以内の範囲に発生するので、
不純物ドープを必要とする電子親和力の小さな半
導体よりなる層（電子供給層）から空間的に分離
され、その電子移動度は不純物散乱によつて影響
されない。そこで、この不純物散乱による効果が
電子移動度の増大を阻むこととなるような低温に
おいて、極めて大きな電子移動度が実現されるこ
とになる。この電子移動度の改善は通常のＮ型
（１×1017cm-3）GaAsに比して10倍程度又はそれ
以上であることが実験的に確認されている。 A major feature of high electron mobility transistors is that the electron mobility of the above-mentioned electron storage layer (two-dimensional electron gas) is low at temperatures such as 77㎓, where the effect of impurity scattering is the main cause of suppressing the electron mobility. It will become extremely large. The above electron storage layer (two-dimensional electron gas) is in a semiconductor layer (channel layer) with a high electron affinity that does not require impurity doping, but is located very close to the heterojunction.
Since it is extremely thin and occurs within a range of about 100 Å,
It is spatially separated from a layer (electron supply layer) made of a semiconductor with low electron affinity that requires impurity doping, and its electron mobility is not affected by impurity scattering. Therefore, extremely high electron mobility is achieved at low temperatures where the effect of impurity scattering prevents an increase in electron mobility. It has been experimentally confirmed that this improvement in electron mobility is about 10 times or more compared to normal N-type (1×10 17 cm −3 ) GaAs.
高電子移動度トランジスタを構成しうる半導体
の組み合せは、格子定数が近似しており、電子親
和力の差が大きく、かつエネルギーギヤツプの差
が大きいという条件を満足すればたりるのでいく
つか存在する。そのうち、本発明はＮ型のアルミ
ニユウムガリユウム砒素（AlGaAs）を電子供給
層としノンドープの砒化ガリユウム（GaAs）を
チヤンネル層とする場合の改良である。 There are several combinations of semiconductors that can constitute a high electron mobility transistor, as long as they have similar lattice constants, a large difference in electron affinity, and a large difference in energy gap. do. Among these, the present invention is an improvement in the case where N-type aluminum gallium arsenide (AlGaAs) is used as the electron supply layer and undoped gallium arsenide (GaAs) is used as the channel layer.
又、高電子移動度トランジスタは、電子親和力
の大きな半導体層（チヤンネル層）を上層にする
か下層にするかにより２種類に分類され、前者に
あつては、電子親和力の大きな半導体層（チヤン
ネル層）の金属学的厚さと電子親和力の小さな半
導体層（電子供給層）の金属学的厚さとの比が、
層構造によつて決定される特定の値より大きいか
小さいかにより、ノーマリオン型（デプレツシヨ
ンモード）又はノーマリオフ型（エンハンスメン
トモード）となる。又後者にあつては、電子親和
力の小さな半導体層（電子供給層）の金属学的厚
さが、層構造によつて決定される特定の値より大
きいか小さいかによりノーマリオン型又はノーマ
リオフ型となる。そのうち、本発明はチヤンネル
層が下層で供給層が上層である場合の改良であ
る。 In addition, high electron mobility transistors are classified into two types depending on whether a semiconductor layer with a large electron affinity (channel layer) is used as an upper layer or a lower layer. ) and the metallurgical thickness of the semiconductor layer with small electron affinity (electron supply layer) is
Depending on whether the value is larger or smaller than a specific value determined by the layer structure, it is a normally-on type (depression mode) or a normally-off type (enhancement mode). In the latter case, it is classified as normally-on type or normally-off type depending on whether the metallurgical thickness of the semiconductor layer (electron supply layer) with low electron affinity is larger or smaller than a specific value determined by the layer structure. Become. Among them, the present invention is an improvement in the case where the channel layer is the lower layer and the supply layer is the upper layer.
かかる構成を有する高電子移動度トランジスタ
にあつて、ソース・ドレイン電極と導電媒体であ
る電子蓄積層（二次元電子ガス）との導通は、従
来、金／金ゲルマニユウム（Au／AuGe）等の
ソース・ドレイン電極形成材の合金化によつてな
されていたが、アルミニユウムガリユウム砒素
（AlGaAs）はオーミツク接触が形成しにくい半
導体であるから、特にソース・ドレイン電極が附
着される層がアルミニユウムガリユウム砒素
（AlGaAs）である場合、満足すべき結果が得ら
れていなかつた。そこで、この電子供給層である
アルミニユウムガリユウム砒素（AlGaAs）層と
チヤンネル層である砒化ガリユウム（GaAs）層
の一部とを除去し、チヤンネル層である砒化ガリ
ユウム（GaAs）層上に直接ソース・ドレイン電
極を形成する手法が採られていたが、この場合当
然メサ型となるため、集積化の妨げになるという
欠点があつた。 In a high electron mobility transistor having such a configuration, conduction between the source/drain electrodes and the electron storage layer (two-dimensional electron gas), which is a conductive medium, has conventionally been achieved using a source such as gold/gold germanium (Au/AuGe).・Although aluminum gallium arsenide (AlGaAs) is a semiconductor in which ohmic contact is difficult to form, it is difficult to form ohmic contacts, so the layer to which the source and drain electrodes are attached is made of aluminum gallium arsenide. In the case of aluminum arsenide (AlGaAs), satisfactory results were not obtained. Therefore, the aluminum gallium arsenide (AlGaAs) layer, which is the electron supply layer, and part of the gallium arsenide (GaAs) layer, which is the channel layer, are removed, and a source is placed directly on the gallium arsenide (GaAs) layer, which is the channel layer. - A method was adopted in which the drain electrode was formed, but in this case it was naturally mesa-shaped, which had the disadvantage of hindering integration.
本発明の目的はこの欠点を解消することにあ
り、Ｎ型のアルミニユウムガリユウム砒素
（AlGaAs）の単結晶層よりなる電子供給層を上
層とし、実質的に不純物を含有しない砒化ガリユ
ウム（GaAs）の単結晶層よりなるチヤンネル層
を下層とするプレーナ型の高電子移動度トランジ
スタにおいて、ソース・ドレイン領域のコンタク
ト抵抗の低い高電子移動度トランジスタの製造方
法を提供することにある。 The purpose of the present invention is to eliminate this drawback, and the upper layer is an electron supply layer made of a single crystal layer of N-type aluminum gallium arsenide (AlGaAs), and is made of gallium arsenide (GaAs) containing substantially no impurities. An object of the present invention is to provide a method for manufacturing a planar type high electron mobility transistor having a channel layer formed of a single crystal layer as the lower layer, in which the contact resistance of the source/drain region is low.
その要旨は、クローム（Cr）等がドープされ
半絶縁性の砒化ガリユウム（GaAs）よりなる基
板上に、モレキユラービームエピタキシヤル成長
法を使用して実質的に不純物を含有しない砒化ガ
リユウム（GaAs）単結晶層よりなるチヤンネル
層と、不純物を含有しないアルミニユウムガリユ
ウム砒素（AlGaAs）単結晶層よりなるバツフア
層とＮ型のアルミニユウムガリユウム砒素
（AlGaAs）単結晶層よりなる電子供給層とをつ
づけて形成し、その最上層であるアルミニユウム
ガリユウム砒素（AlGaAs）単結晶層上のソー
ス・ドレイン形成領域以外の領域にマスクを形成
し、このマスクを使用して、選択的に前記ソー
ス・ドレイン形成領域にて、前記電子供給層から
チヤンネル層に至るまでの深さに欠陥を発生させ
るためのプロトン（H+）を注入し、この領域の
アルミニユウムガリユウム砒素（AlGaAs）層と
砒化ガリユウム（GaAs）層とに欠陥を発生させ
てから、上記のマスクを除去しそれに代えて窒化
アルミニユウム（AlN）層よりなる保護膜を全
面に形成し、700℃程度の温度で熱処理を施こし、
前工程で結晶欠陥を発生させた領域のアルミニユ
ウムガリユウム砒素（AlGaAs）層から、Ｎ型不
純物であるシリコン（Si）を、対接する領域の、
ひとしく結晶欠陥を含む砒化ガリユウム
（GaAs）層中に増速拡散させ、アルミニユウム
ガリユウム砒素（AlGaAs）層と砒化ガリユウム
（GaAs）層との間のコンタクト抵抗を減少させ
てから、上記の窒化アルミニユウム（AlN）よ
りなる保護膜を除去し、以下通常の手法をもつて
金／金ゲルマニユウム（Au／AuGe）等よりな
るソース・ドレイン電極を形成の上これを合金化
してコンタクト抵抗の低いソース・ドレイン電極
を形成し、つづいて、ソース・ドレイン電極に挾
まれたゲート電極形成領域に通常の手法をもつて
ゲート電極を形成することにある。プロトン注入
の条件は注入されるイオンの有する加速エネルギ
ーと注入されるイオンの到達する深さに関する
「LSS理論」にもとづき、アルミニユウムガリユ
ウム砒素（AlGaAs）よりなる電子供給層とバツ
フア層との厚さを考慮の上、注入されるイオンの
密度がバツフア層とチヤンネル層との界面附近に
おいて最大となるように選択すればよい。更に具
体的には上記アルミニユウムガリユウム砒素
（AlGaAs）層の厚さが0.2μｍの場合、50KeV程
度以上の加速エネルギーをもつてイオン注入する
ことが望ましい。又、チヤンネル層と電子供給層
との間に介在するバツフア層の機能は、ソース・
ドレイン領域にシリコン（Si）を増速拡散させる
ためになす700℃程度の熱処理において、ゲート
領域下部のチヤンネル層に電子供給層から不純物
が拡散して電子蓄積層（二次元電子ガス）の電子
移動度が減少することを防止することにある。 The gist of this is that gallium arsenide (GaAs), which contains virtually no impurities, is grown on a substrate made of semi-insulating gallium arsenide (GaAs) doped with chromium (Cr) etc. using the molecular beam epitaxial growth method. ) A channel layer made of a single crystal layer, a buffer layer made of an aluminum gallium arsenide (AlGaAs) single crystal layer containing no impurities, and an electron supply layer made of an N-type aluminum gallium arsenide (AlGaAs) single crystal layer. A mask is formed on the uppermost layer of the aluminum gallium arsenide (AlGaAs) single crystal layer in a region other than the source/drain formation region, and this mask is used to selectively form the source. - In the drain formation region, protons (H + ) are injected to generate defects in the depth from the electron supply layer to the channel layer, and the aluminum gallium arsenide (AlGaAs) layer and arsenide in this region are injected. After creating defects in the gallium (GaAs) layer, the above mask is removed and a protective film made of aluminum nitride (AlN) layer is formed over the entire surface in its place, followed by heat treatment at a temperature of approximately 700°C.
Silicon (Si), which is an N-type impurity, is added from the aluminum gallium arsenide (AlGaAs) layer in the area where crystal defects were generated in the previous process to the opposing area.
The above-mentioned aluminum nitride is diffused at increased speed into the gallium arsenide (GaAs) layer, which equally contains crystal defects, to reduce the contact resistance between the aluminum gallium arsenide (AlGaAs) layer and the gallium arsenide (GaAs) layer. The protective film made of (AlN) is removed, and source/drain electrodes made of gold/gold germanium (Au/AuGe) are then formed using the usual method and then alloyed to form source/drain electrodes with low contact resistance. The method is to form an electrode, and then to form a gate electrode in a gate electrode formation region sandwiched between source and drain electrodes using a conventional method. The conditions for proton implantation are based on the "LSS theory" regarding the acceleration energy of the implanted ions and the depth that the implanted ions reach, and the thickness of the electron supply layer and buffer layer made of aluminum gallium arsenide (AlGaAs). Taking into consideration the stability, the density of implanted ions may be selected so as to be maximized near the interface between the buffer layer and the channel layer. More specifically, when the thickness of the aluminum gallium arsenide (AlGaAs) layer is 0.2 μm, it is desirable to implant ions with an acceleration energy of about 50 KeV or more. In addition, the function of the buffer layer interposed between the channel layer and the electron supply layer is
During heat treatment at approximately 700°C to accelerate diffusion of silicon (Si) into the drain region, impurities diffuse from the electron supply layer into the channel layer at the bottom of the gate region, causing electron movement in the electron storage layer (two-dimensional electron gas). The purpose is to prevent the degree from decreasing.
以下、図面を参照しつつ、本発明の一実施例に
係る半導体装置具体的には高電子移動度トランジ
スタの製造方法を説明し、本発明の構成と特有の
効果とを明らかにする。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device, specifically a high electron mobility transistor, according to an embodiment of the present invention will be explained with reference to the drawings, and the structure and unique effects of the present invention will be clarified.
第１図参照
モレキユラービームエピタキシヤル成長法を使
用して、クローム（Cr）等のドープされた半絶
縁性砒化ガリユウム（GaAs）基板１上に、ノン
ドープの砒化ガリユウム（GaAs）層（チヤンネ
ル層）２と、ノンドープで50〜60Å程度の厚さを
有するアルミニユウムガリユウム砒素
（AlGaAs）層（バツフア層）３と、シリコン
（Si）が1018／cm3程度にドープされ厚さが0.2μｍ
程度のアルミニユウムガリユウム砒素
（AlGaAs）層（電子供給層）４とをつづけて形
成する。バツフア層３の機能は上記のとおり、モ
レキユラービームエピタキシヤル成長工程中と熱
処理工程中にゲート下部領域での不純物拡散を防
止することにある。Refer to Figure 1 Using a molecular beam epitaxial growth method, a non-doped gallium arsenide (GaAs) layer (channel layer ) 2, a non-doped aluminum gallium arsenide (AlGaAs) layer (buffer layer) 3 with a thickness of about 50 to 60 Å, and a silicon (Si) doped layer of about 10 18 /cm 3 with a thickness of 0.2 μm.
Then, an aluminum gallium arsenide (AlGaAs) layer (electron supply layer) 4 is formed. As described above, the function of the buffer layer 3 is to prevent impurity diffusion in the region below the gate during the molecular beam epitaxial growth process and the heat treatment process.
第２図参照
フオトリソグラフイー法を使用して、ソース・
ドレイン領域を除いて電子供給層４上にマスク層
５を形成し、50KeV程度のエネルギーと１×
1016／cm2程度のドーズ量をもつてプロトン（H+）
を注入する。このエネルギーによつてバツフア層
３とチヤンネル層２との界面近辺に最大量の結晶
欠陥を含む領域６が発生する。See Figure 2 Using photolithography, the source
A mask layer 5 is formed on the electron supply layer 4 except for the drain region, and an energy of about 50 KeV and 1×
Protons (H + ) with a dose of about 10 16 /cm 2
inject. This energy generates a region 6 containing the largest amount of crystal defects near the interface between the buffer layer 3 and the channel layer 2.
第３図参照
マスク層５を除去した後、スパツタリングによ
つて厚さ1000Å程度の窒化アルミニユウム
（AlN）よりなる保護膜７を形成して700℃程度
の温度で熱処理する。この保護膜７が存在しない
と電子供給層４をなすアルミニユウムガリユウム
砒素（AlGaAs）の砒素（As）が昇華したりして
電子供給層４を破損する。この熱処理工程におい
て、前工程で結晶欠陥の発生した領域６の砒化ガ
リユウム（GaAs）領域でＮ型不純物であるシリ
コン（Si）が増速拡散して、Ｎ型の砒化ガリユウ
ム（GaAs）領域６′が形成され、このソース・
ドレイン形成領域において電子供給層４とチヤン
ネル層２との間のコンタクト抵抗が低下する。Refer to FIG. 3. After removing the mask layer 5, a protective film 7 made of aluminum nitride (AlN) with a thickness of about 1000 Å is formed by sputtering and heat treated at a temperature of about 700°C. If this protective film 7 does not exist, arsenic (As) of aluminum gallium arsenide (AlGaAs) forming the electron supply layer 4 will sublimate and damage the electron supply layer 4. In this heat treatment step, silicon (Si), which is an N-type impurity, diffuses at an accelerated rate in the gallium arsenide (GaAs) region 6 where crystal defects have occurred in the previous step, and the N-type gallium arsenide (GaAs) region 6' is formed and this source
The contact resistance between the electron supply layer 4 and the channel layer 2 is reduced in the drain formation region.
第４図参照
保護膜７を熱燐酸（H3PO4）等を使用して溶
融除去した後、再びフオトリソグラフイー法を使
用してソース・ドレイン領域以外の電子供給層４
上領域をマスク８をもつて覆い、金／金ゲルマニ
ユウム（Au／AuGe）等の金属層９を蒸着して
これを400〜450℃で合金化する。上記の工程で、
Ｎ型の砒化ガリユウム（GaAs）領域６′がすで
に形成されているので、ソース・ドレイン形成領
域においては、金／金ゲルマニユウム（Au／
AuGe）層９と電子蓄積層（二次元電子ガス）と
のコンタクト抵抗は非常に低くなる。Refer to Figure 4. After removing the protective film 7 by melting it using hot phosphoric acid (H 3 PO 4 ), etc., the electron supply layer 4 other than the source/drain regions is removed again using the photolithography method.
The upper region is covered with a mask 8, and a metal layer 9 such as gold/gold germanium (Au/AuGe) is deposited and alloyed at 400-450°C. In the above process,
Since the N-type gallium arsenide (GaAs) region 6' has already been formed, gold/gold germanium (Au/
The contact resistance between the AuGe layer 9 and the electron storage layer (two-dimensional electron gas) becomes extremely low.
第５図参照
ソース・ドレイン領域上以外からマスク層８と
その上に形成された金／金ゲルマニユウム
（Au／AuGe）層９とを除去して、ソース・ドレ
イン電極９を完成する。Refer to FIG. 5. The mask layer 8 and the gold/gold germanium (Au/AuGe) layer 9 formed thereon are removed from areas other than the source/drain regions to complete the source/drain electrodes 9.
第６図参照
フオトリソグラフイー法を使用してゲート形成
領域上以外をマスク（図示せず。）で覆い、アル
ミニユウム（Al）等を蒸着の後、リフトオフ法
でゲート領域上以外からマスクとアルミニユウム
（Al）層とを除去し、ゲート１０を完成する。Refer to Figure 6. Using the photolithography method, cover the area other than the gate formation area with a mask (not shown), evaporate aluminum (Al), etc., and then use the lift-off method to cover the area other than the gate formation area with a mask (not shown). Al) layer is removed to complete the gate 10.
以上説明せるとおり、本発明によれば、Ｎ型の
アルミニユウムガリユウム砒素（AlGaAs）の単
結晶層よりなる電子供給層を上層とし、実質的に
不純物を含有しない砒化ガリユウム（GaAs）の
単結晶層よりなるチヤンネル層を下層とするプレ
ーナ型の高電子移動度トランジスタにおいて、ソ
ース・ドレイン形成領域の電子供給層とチヤンネ
ル層との界面近傍にプロトン（H+）注入をなし
て意識的に結晶欠陥を作成し、ソース・ドレイン
形成領域のチヤンネル層中に電子供給層中からＮ
型不純物を増速拡散させた後、ソース・ドレイン
電極の形成と合金化とをなすことを特徴とする、
ソース・ドレイン領域のコンタクト抵抗の低い高
電子移動度トランジスタを製造する方法を提供す
ることができる。 As explained above, according to the present invention, an electron supply layer made of an N-type single crystal layer of aluminum gallium arsenide (AlGaAs) is formed as an upper layer, and a single crystal of gallium arsenide (GaAs) containing substantially no impurities is provided. In a planar high electron mobility transistor with a channel layer as the lower layer, protons (H + ) are injected near the interface between the electron supply layer and the channel layer in the source/drain formation region to intentionally eliminate crystal defects. N is added from the electron supply layer to the channel layer in the source/drain formation region.
The method is characterized in that after accelerated diffusion of type impurities, formation of source/drain electrodes and alloying are performed.
A method for manufacturing a high electron mobility transistor with low contact resistance in source/drain regions can be provided.
第１，２，３，４，５，６図は本発明の一実施
例に係る半導体装置具体的にはプレーナ型高電子
移動度トランジスタの主要工程における基板断面
図である。
１……クロームドープされた半絶縁性砒化ガリ
ユウム基板、２……チヤンネル層（実質的に不純
物を含有しないガリユウム砒素単結晶層）、３…
…バツフア層（実質的に不純物を含有しないアル
ミニユウムガリユウム砒素層）、４……電子供給
層（Ｎ型のアルミニユウムガリユウム砒素層）、
５……マスク層（フオトレジスト層）、６……大
量に結晶欠陥を含む領域、６′……Ｎ型の砒化ガ
リユウム領域、７……窒化アルミニユウムよりな
る保護膜、８……マスク層（フオトレジスト層）、
９……ソース・ドレイン電極層（金／金ゲルマニ
ユウム層）、１０……ゲート電極層（アルミニユ
ウム層）。
1, 2, 3, 4, 5, and 6 are cross-sectional views of a semiconductor device, specifically, a planar type high electron mobility transistor, in main steps of a semiconductor device according to an embodiment of the present invention. 1... Chrome-doped semi-insulating gallium arsenide substrate, 2... Channel layer (gallium arsenide single crystal layer substantially free of impurities), 3...
... Buffer layer (aluminum gallium arsenide layer containing substantially no impurities), 4... Electron supply layer (N-type aluminum gallium arsenide layer),
5...Mask layer (photoresist layer), 6...Region containing a large amount of crystal defects, 6'...N-type gallium arsenide region, 7...Protective film made of aluminum nitride, 8...Mask layer (photoresist layer) resist layer),
9... Source/drain electrode layer (gold/gold germanium layer), 10... Gate electrode layer (aluminum layer).
Claims (1)
実質的に不純物を含有しない砒化ガリユウムの単
結晶層よりなるチヤンネル層を形成し、該チヤン
ネル層上に実質的に不純物を含有しないアルミニ
ユウムガリユウム砒素の単結晶層よりなるバツフ
ア層を形成し、該バツフア層上にＮ型のアルミニ
ユウムガリユウム砒素の単結晶よりなる電子供給
層を形成し、前記電子供給層のソース・ドレイン
形成領域以外の領域上にマスクを形成し、該マス
クを使用して選択的に前記ソース・ドレイン形成
領域にて、前記電子供給層からチヤンネル層に至
るまでの深さに欠陥を発生させるためのプロトン
を注入し、その後プロトン注入領域で不純物拡散
が生じるのに十分な温度をもつて熱処理を施した
後、前記電子供給層のソース・ドレイン形成領域
上にソース・ドレイン電極を形成し、該ソース・
ドレイン電極に挟まれたゲート電極形成領域に金
属層を形成してゲート電極を完成する工程よりな
る、半導体装置の製造方法。1 Forming a channel layer made of a single crystal layer of gallium arsenide substantially free of impurities on a substrate made of semi-insulating gallium arsenide, and depositing aluminum gallium arsenide substantially free of impurities on the channel layer. forming a buffer layer made of a single crystal layer of N-type aluminum gallium arsenide on the buffer layer; forming an electron supply layer made of an N-type aluminum gallium arsenide single crystal; forming a mask thereon, using the mask to selectively inject protons into the source/drain formation region to generate defects at a depth from the electron supply layer to the channel layer; After that, heat treatment is performed at a temperature sufficient to cause impurity diffusion in the proton injection region, and then source/drain electrodes are formed on the source/drain forming regions of the electron supply layer.
A method for manufacturing a semiconductor device comprising a step of forming a metal layer in a gate electrode formation region sandwiched between drain electrodes to complete a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14999081A JPS5851575A (en) | 1981-09-22 | 1981-09-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14999081A JPS5851575A (en) | 1981-09-22 | 1981-09-22 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5851575A JPS5851575A (en) | 1983-03-26 |
| JPS6356711B2 true JPS6356711B2 (en) | 1988-11-09 |
Family
ID=15487049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14999081A Granted JPS5851575A (en) | 1981-09-22 | 1981-09-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5851575A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0614563B2 (en) * | 1985-04-15 | 1994-02-23 | 猛 小林 | Semiconductor device |
| US5381027A (en) * | 1988-01-26 | 1995-01-10 | Hitachi, Ltd. | Semiconductor device having a heterojunction and a two dimensional gas as an active layer |
| EP2953167A1 (en) * | 2014-06-05 | 2015-12-09 | Nxp B.V. | Semiconductor heterojunction device |
| KR102248478B1 (en) | 2014-09-18 | 2021-05-06 | 인텔 코포레이션 | Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon cmos-compatible semiconductor devices |
| KR102203497B1 (en) | 2014-09-25 | 2021-01-15 | 인텔 코포레이션 | Iii-n epitaxial device structures on free standing silicon mesas |
| US10243069B2 (en) * | 2014-10-30 | 2019-03-26 | Intel Corporation | Gallium nitride transistor having a source/drain structure including a single-crystal portion abutting a 2D electron gas |
| EP3235005A4 (en) | 2014-12-18 | 2018-09-12 | Intel Corporation | N-channel gallium nitride transistors |
| WO2019066953A1 (en) | 2017-09-29 | 2019-04-04 | Intel Corporation | Group iii-nitride (iii-n) devices with reduced contact resistance and their methods of fabrication |
| CN109841676A (en) * | 2019-03-21 | 2019-06-04 | 华南理工大学 | Supplementary doping realizes normally-off GaN HEMT device and preparation method thereof |
-
1981
- 1981-09-22 JP JP14999081A patent/JPS5851575A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5851575A (en) | 1983-03-26 |
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