JPH0583616A - Digital interpolating device - Google Patents

Abstract

PURPOSE:T accelerate digital interpolating processing and to reduce a circuit scale. CONSTITUTION:Word lines W0-W4 and bit lines B0-B14 are derived from a memory array in which memory cells are arranged in matrix shape. One of the word lines W0-W4 is designated by a select signal from a row decoder 2. Plural output lines O0-O6 are provided. The output lines 00-06 are coupled with the bit lines B0-B14 by select signals S0-S20 from a common column decoder 4 selectively. The select signals S0-S20 couple the bit lines B0-B7 with input/ output lines I0-I03, respectively so as to shift the bit lines one by one. The output lines 00-06 are connected to the input terminal of an interpolation circuit 5, and adjacent plural pieces of picture element data are inputted to the interpolation circuit 5 with one time of access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to use, for example, a multi-port memory in which a plurality of ports are derived from one semiconductor memory array to perform interpolation for correcting image data distortion. The present invention relates to a digital interpolation device.

[0002]

2. Description of the Related Art Since an image taken by a fisheye lens is distorted, the image pickup signal is converted into a digital signal and the distortion is corrected by digital signal processing. In addition, camera shake when shooting with a video camera is corrected by digital signal processing. This camera shake correction is a process of detecting a motion vector caused by the camera shake and shifting the image frame by the amount of the motion vector. When the image frame is shifted, a region where the captured image does not exist is generated, so that the process of enlarging the captured image is performed in advance. Not limited to image stabilization,
The image enlargement process may be performed by a special effect generator or the like. Image reduction may also be required. In the distortion correction, enlargement, and reduction of these images, data interpolated from the original image data is generated.

[0003]

Thus, in digital processing of images, interpolators are used in various cases. The interpolation device is a process of multiplying a plurality of neighboring pixel data by weighting coefficients and adding the multiplication results. Conventionally, the memory that stores image data and the circuit that performs the interpolation calculation access only one data per cycle, and interpolation cannot be performed in real time.
In other words, if a plurality of pixel data can be simultaneously supplied to the interpolation circuit in one cycle, the speed of interpolation processing can be increased.

Therefore, an object of the present invention is to provide a digital interpolating device capable of simultaneously supplying a plurality of pixel data to an interpolating circuit by a multiport memory having a plurality of output ports and performing high speed processing. To do.

Another object of the present invention is to provide a digital interpolating device capable of interpolating an audio signal or a video signal by means of a multiport memory whose circuit scale is not so large.

[0006]

In a multiport memory according to the present invention, a plurality of memory cells are arranged in a matrix form, and first lines W0 to W4 for selecting one of rows or columns in the memory cells. , A memory array (1) from which a second line B0 to B14 for selecting the other row or column in the memory cell is derived, and a select signal for selecting the first line W0 to W4 Shared by the first decoder (2) for outputting, a plurality of output ports O0-O6 connected to the second lines B0-B14, and a plurality of output ports O0-O6. , The second line B0
A second decoder (4) for generating select signals S0 to S20 for selecting B14, and an output port O0
To an interpolator (5) to which read data of the memory array (1) from O6 is supplied, the second lines B0 to B1
The select signals S0 to S20 for selecting 4 connect the second lines B0 to B14 at positions shifted one by one to the plurality of output ports O0 to O6, respectively, and interpolate the circuit (5). Is a digital interpolation device characterized by generating output data by interpolating a plurality of neighboring data supplied from a plurality of output ports O0 to O6.

[0007]

A plurality of output ports O0 to O6 are provided, and a plurality of neighboring data are simultaneously given to the interpolation circuit 5 from this. Therefore, the interpolation calculation is performed in parallel, and the speed of the interpolation processing can be increased. Further, since the second decoder 4 is shared by the plurality of output ports O0 to O6, the circuit scale is small. In the output ports O0 to O6, a plurality of data in the vicinity are simultaneously read at positions corresponding to those activated in the select signals S0 to S20, and the read data are sent to the interpolation circuit 5. Given.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 denotes a semiconductor memory array in which memory cells are arranged in a matrix. In this embodiment, the memory array 1 is composed of memory cells of 5 rows × 15 columns. Word lines W0, W1, W2, W3, W4 for selecting each row of the memory array 1 and bit lines B0, B1, ... For selecting each column thereof.
B14 is derived. For bit lines B0-B14,
Seven output lines O0, O1, ..., O6 are connected in parallel. In FIG. 1, the sense amplifier, a place where the load is heavy, such as a strong buffer to be connected to the word line, are not shown because they are not related to the gist of the present invention. Each row of the memory array 1 indicates the line direction of the video signal, and pixel data (1 sample) is written in each memory cell. The write configuration is omitted for simplicity, but video data is written to the memory array 1 through an input port that also serves as an output port or is separate.

The row decoder 2 is connected to the word lines W0 to W4.
Select signal is selectively supplied, and one of the word lines (rows) is selected. A control signal from the control circuit 3 is supplied to the row decoder 2, and the control circuit 3 is also coupled to the column decoder 4. The control circuit 3 supplies, for example, the upper bits of the address to the row decoder 2, and the control circuit 3 supplies the lower bits to the column decoder 4.

The select signal from the row decoder 2 selects one row, while the select signals S0 to S20 from the column decoder 4 are supplied to a plurality of bit lines. That is, the select signal S0 is supplied to the bit line B0, the select signal S1 is supplied to the bit lines B0 and B1, the select signal S2 is supplied to the bit lines B0, B1 and B2,
The select signal S3 is supplied to the bit lines B0, B1, B2, B3, and the select signals are supplied to the bit lines so that the bit lines are sequentially shifted one by one.

In FIG. 1, for example, a simple expression is used in which the bit line, for example, B14 and the output line O0 are orthogonal to each other, and the supply line of the select signal S20 diagonally crosses this intersection. This is the bit line B, as shown enlarged in FIG.
A switching element SW is provided between 14 and the output line O0, and the switching element SW is turned on by an active select signal S20. When the switching element SW is turned on, the bit line B14 and the output O0 are coupled, and the data from the memory cell connected to the bit line B14 can be read to the output line O0.

Each pixel data stored in each (5 × 15) matrix memory cell is represented by ai, j (i
= 0, 1, 2, 3, 4, j = 0, 1, 2, ..., 1
It is represented by 4). As an example, the row decoder 2 may be the word line W.
When a select signal for selecting 0 is output, 15 memory cells connected to this word line W0 are designated. At the same time, the column decoder 4 causes the column lines B0, B1,
... When the select signal S6 for selecting B6 is activated, the memory cells from the first column to the seventh column of the first row are accessed. Therefore, from these memory cells
The pixel data of 0,0, a0,1, ..., A0,6 are output lines O
0 to O6 are read. That is, seven consecutive pixel data a0,0 to a0,6 on the same line can be read simultaneously.

The output lines O0 to O6 are connected to a plurality of input terminals of the interpolation circuit 5. The interpolation circuit 5 multiplies the seven pixel data by a weighting coefficient corresponding to each position and adds the multiplication output to generate interpolation data at the output terminal 6. A control signal from the control circuit 3 is supplied to the interpolation circuit 5 in order to control the timing of the interpolation calculation.

The operation of the above-described embodiment of the present invention will be described, for example, in the case of performing interpolation for correcting distortion of an image taken through a wide-angle lens. In FIG. 2, which shows a partial area of one image, the dots indicate the original pixel data a0 stored in the memory array 1,
0 to a4,14. Interpolation outputs b0 to b11 are formed from the (5 × 15) pixel data, and the image distortion is corrected.

The output order of the interpolation output is b0, b1, ...
.., b11. To form each interpolated output, the original data ai, j near that position is used. The data a i, j required for this interpolation is, as shown in FIG. 3, bk (k = 0, 1,
The data is within the range of (± 2 pixels) with 2, 2, ..., 11) as the center. Therefore, 16 original pixel data are required to generate each interpolated output.

FIG. 4 shows the range of pixel data required to generate the interpolated output b0 in FIG. Hereinafter, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG.
2, FIG. 13, FIG. 14, and FIG. 15 show the interpolation outputs b1, b2,
The ranges of pixel data required to generate b3, ..., B11 are shown respectively.

The operation when the configuration according to the present invention shown in FIG. 1 is applied to the above-mentioned interpolation processing is shown in order from FIG. 16 onward. FIG. 16 shows the processing of the first cycle, in which the memory cells indicated by thick lines in the figure are accessed. That is, the word line W0 is designated by the row decoder 2 and the select signal S6 from the column decoder 4 is activated, whereby the bit lines B0 to B6 and the output lines O0 to O0.
Is combined with O6. As a result, the pixel data a0,0 to a0,6 of the first line stored in the memory array 1 are read out and supplied to the interpolation circuit 5.

In the next second cycle, as shown in FIG. 17, the word line W1 is designated and the select signal S6 is activated. Therefore, the seven pixel data a1,0 to a1,6 of the second line are read from the memory array 1 and supplied to the interpolation circuit 5. In the third cycle, as shown in FIG. 18, the word line W2 is designated and the select signal S6 is activated. Therefore, the seven pixel data a2,0 to a2,6 of the third line are read from the memory array 1 and supplied to the interpolation circuit 5. In the fourth cycle, as shown in FIG. 19, the word line W3 is designated and the select signal S6 is activated. Therefore, the seven pixel data a3,0 to a3,6 of the fourth line are read from the memory array 1 and supplied to the interpolation circuit 5.

At the end of this fourth cycle, as shown in FIG.
Original pixel data necessary for the interpolation calculation shown in FIGS. 5, 6 and 7 are supplied to the interpolation circuit 5. Therefore, the interpolation circuit 5 can generate the interpolation outputs b0, b1, b2, b3. The interpolation calculation is to multiply each of 16 original pixel data by a coefficient and add the multiplication result. This coefficient corresponds to the positional relationship between the interpolation output and the original pixel data. The interpolation output is taken out to the output terminal 6 of the interpolation circuit 5. The interpolation output may be temporarily stored in the memory and output at a constant rate.

20 to 23 sequentially show the access operation of the memory array 1 from the fifth cycle to the eighth cycle. By this operation, the second line, the third line, the fourth line
Pixel data (a1,3 to a1,9) (a2,3 to a2,9) (a3,3 to a3,9) included in the line and the fifth line, respectively.
) (A4,3 to a4,9) are read from the memory array 1. Therefore, the pixel data necessary for generating the interpolation outputs b4 to b7 shown in FIGS. 8 to 11 are supplied to the interpolation circuit 5. These interpolated outputs are generated at the end of the eighth cycle.

24 to 27 sequentially show the access operation of the memory array 1 from the ninth cycle to the twelfth cycle. By this operation, the pixel data (a0,8 to a0,14) (a1,8 to a1,14) (a2,8 to a contained in the first line, the second line, the third line and the fourth line, respectively)
2,14) (a3,8 to a3,14) are read from the memory array 1. Therefore, the pixel data necessary for generating the interpolation outputs b8 to b11 shown in FIGS. 12 to 15 are supplied to the interpolation circuit 5. These interpolated outputs are generated at the end of the 12th cycle.

In order to write pixel data to the memory array 1, one input line is connected to the bit line derived from the memory array 1, a column decoder 4 and another input column decoder are provided, and this input column is provided. A configuration can be adopted in which one bit line is designated by the decoder.

Further, as shown in FIG. 28, a structure having a serial input port SI can be adopted. Serial input data from the input terminal 8 (SI) is supplied to the shift register 7. The parallel output of the shift register 7 is connected to the bit lines b10 to b24 of the memory array 1. The 15 pieces of data input to the shift register 7 are simultaneously written to the 15 memory cells connected to one word line designated by the row decoder 2.

The above-mentioned operation is performed when performing the interpolation as shown in FIG. 2, but the operation is not limited to this, and the image is enlarged,
It is also possible to perform interpolation calculation for reduction or the like.

[0025]

According to the present invention, a plurality of pixel data in the vicinity can be simultaneously supplied to the circuit for performing the interpolation calculation by one access, and the interpolation processing can be performed at high speed. Further, according to the present invention, the column decoder can be shared by a plurality of input / output ports, and the circuit scale can be reduced as compared with the case where a column decoder is provided for each input / output port.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a schematic diagram used to describe an interpolation process to which the present invention can be applied.

FIG. 3 is a schematic diagram showing a range of pixel data required for interpolation processing.

FIG. 4 is a schematic diagram showing a range of pixel data required to generate an interpolation output b0.

FIG. 5 is a schematic diagram showing a range of pixel data required to generate an interpolation output b1.

FIG. 6 is a schematic diagram showing a range of pixel data required to generate an interpolation output b2.

FIG. 7 is a schematic diagram showing a range of pixel data required to generate an interpolation output b3.

FIG. 8 is a schematic diagram showing a range of pixel data required to generate an interpolation output b4.

FIG. 9 is a schematic diagram showing a range of pixel data required to generate an interpolation output b5.

FIG. 10 is a schematic diagram showing a range of pixel data required to generate an interpolation output b6.

FIG. 11 is a schematic diagram showing a range of pixel data required to generate an interpolation output b7.

FIG. 12 is a schematic diagram showing a range of pixel data required to generate an interpolation output b8.

FIG. 13 is a schematic diagram showing a range of pixel data required to generate an interpolation output b9.

FIG. 14 is a schematic diagram showing a range of pixel data required to generate an interpolation output b10.

FIG. 15 is a schematic diagram showing a range of pixel data required to generate an interpolation output b11.

FIG. 16 is a block diagram used for explaining the operation of the first cycle of the embodiment of the present invention.

FIG. 17 is a block diagram used for explaining the operation of the second cycle of the embodiment of the present invention.

FIG. 18 is a block diagram used for explaining the operation of the third cycle of the embodiment of the present invention.

FIG. 19 is a block diagram used for explaining the operation of the fourth cycle of the embodiment of the present invention.

FIG. 20 is a block diagram used for explaining the operation of the fifth cycle of the embodiment of the present invention.

FIG. 21 is a block diagram used for explaining the operation of the sixth cycle of the embodiment of the present invention.

FIG. 22 is a block diagram used for explaining the operation of the seventh cycle of the embodiment of the present invention.

FIG. 23 is a block diagram used for explaining an operation of the eighth cycle of the embodiment of the present invention.

FIG. 24 is a block diagram used for explaining the operation of the ninth cycle of the embodiment of the present invention.

FIG. 25 is a block diagram used for explaining the operation of the 10th cycle of the embodiment of the present invention.

FIG. 26 is a block diagram used for explaining the operation of the 11th cycle of the embodiment of the present invention.

FIG. 27 is a block diagram used for explaining the operation of the twelfth cycle of the embodiment of the present invention.

FIG. 28 is a block diagram of another embodiment of the present invention.

[Explanation of symbols]

 1 memory array 2 row decoder 4 column decoder 5 interpolation circuit W0 to W4 word line B0 to B14 bit line O0 to O6 output line

Claims (1)

[Claims] 1. A plurality of memory cells are arranged in a matrix, and a first line for selecting one of the rows or columns in the memory cells and the other of the rows or columns in the memory cells are selected. And a first decoder for generating a select signal for selecting the first line, and a plurality of memory arrays connected to the second line. And the second output port is shared by the second output port and the second output port.
A second decoder for generating a select signal for selecting the second line, and an interpolation circuit to which the read data of the memory array from the output port is supplied, for selecting the second line Select signal is coupled to each of the plurality of output ports by the second line at a position shifted one by one, and the interpolator circuit supplies a plurality of neighboring signals supplied from the plurality of output ports. A digital interpolating device characterized by generating output data by interpolating data.